FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci.c
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: releng/9.2/sys/dev/pci/pci.c 253273 2013-07-12 16:41:58Z marius $");
31
32 #include "opt_bus.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
40 #include <sys/conf.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
45
46 #include <vm/vm.h>
47 #include <vm/pmap.h>
48 #include <vm/vm_extern.h>
49
50 #include <sys/bus.h>
51 #include <machine/bus.h>
52 #include <sys/rman.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
55
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
58 #endif
59
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
64
65 #include <dev/usb/controller/xhcireg.h>
66 #include <dev/usb/controller/ehcireg.h>
67 #include <dev/usb/controller/ohcireg.h>
68 #include <dev/usb/controller/uhcireg.h>
69
70 #include "pcib_if.h"
71 #include "pci_if.h"
72
73 /*
74 * XXX: Due to a limitation of the bus_dma_tag_create() API, we cannot
75 * specify a 4GB boundary on 32-bit targets. Usually this does not
76 * matter as it is ok to use a boundary of 0 on these systems.
77 * However, in the case of PAE, DMA addresses can cross a 4GB
78 * boundary, so as a workaround use a 2GB boundary.
79 */
80 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
81 #ifdef PAE
82 #define PCI_DMA_BOUNDARY 0x80000000
83 #else
84 #define PCI_DMA_BOUNDARY 0x100000000
85 #endif
86 #endif
87
88 #define PCIR_IS_BIOS(cfg, reg) \
89 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
90 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
91
92 static int pci_has_quirk(uint32_t devid, int quirk);
93 static pci_addr_t pci_mapbase(uint64_t mapreg);
94 static const char *pci_maptype(uint64_t mapreg);
95 static int pci_mapsize(uint64_t testval);
96 static int pci_maprange(uint64_t mapreg);
97 static pci_addr_t pci_rombase(uint64_t mapreg);
98 static int pci_romsize(uint64_t testval);
99 static void pci_fixancient(pcicfgregs *cfg);
100 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
101
102 static int pci_porten(device_t dev);
103 static int pci_memen(device_t dev);
104 static void pci_assign_interrupt(device_t bus, device_t dev,
105 int force_route);
106 static int pci_add_map(device_t bus, device_t dev, int reg,
107 struct resource_list *rl, int force, int prefetch);
108 static int pci_probe(device_t dev);
109 static int pci_attach(device_t dev);
110 static void pci_load_vendor_data(void);
111 static int pci_describe_parse_line(char **ptr, int *vendor,
112 int *device, char **desc);
113 static char *pci_describe_device(device_t dev);
114 static bus_dma_tag_t pci_get_dma_tag(device_t bus, device_t dev);
115 static int pci_modevent(module_t mod, int what, void *arg);
116 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
117 pcicfgregs *cfg);
118 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
119 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
120 int reg, uint32_t *data);
121 #if 0
122 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
123 int reg, uint32_t data);
124 #endif
125 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
126 static void pci_disable_msi(device_t dev);
127 static void pci_enable_msi(device_t dev, uint64_t address,
128 uint16_t data);
129 static void pci_enable_msix(device_t dev, u_int index,
130 uint64_t address, uint32_t data);
131 static void pci_mask_msix(device_t dev, u_int index);
132 static void pci_unmask_msix(device_t dev, u_int index);
133 static int pci_msi_blacklisted(void);
134 static int pci_msix_blacklisted(void);
135 static void pci_resume_msi(device_t dev);
136 static void pci_resume_msix(device_t dev);
137 static int pci_remap_intr_method(device_t bus, device_t dev,
138 u_int irq);
139
140 static device_method_t pci_methods[] = {
141 /* Device interface */
142 DEVMETHOD(device_probe, pci_probe),
143 DEVMETHOD(device_attach, pci_attach),
144 DEVMETHOD(device_detach, bus_generic_detach),
145 DEVMETHOD(device_shutdown, bus_generic_shutdown),
146 DEVMETHOD(device_suspend, pci_suspend),
147 DEVMETHOD(device_resume, pci_resume),
148
149 /* Bus interface */
150 DEVMETHOD(bus_print_child, pci_print_child),
151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
152 DEVMETHOD(bus_read_ivar, pci_read_ivar),
153 DEVMETHOD(bus_write_ivar, pci_write_ivar),
154 DEVMETHOD(bus_driver_added, pci_driver_added),
155 DEVMETHOD(bus_setup_intr, pci_setup_intr),
156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
157
158 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
159 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
160 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
161 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
162 DEVMETHOD(bus_delete_resource, pci_delete_resource),
163 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
164 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
165 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
166 DEVMETHOD(bus_activate_resource, pci_activate_resource),
167 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
168 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
169 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
170 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
171
172 /* PCI interface */
173 DEVMETHOD(pci_read_config, pci_read_config_method),
174 DEVMETHOD(pci_write_config, pci_write_config_method),
175 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
176 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
177 DEVMETHOD(pci_enable_io, pci_enable_io_method),
178 DEVMETHOD(pci_disable_io, pci_disable_io_method),
179 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
180 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
181 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
182 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
183 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
184 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
185 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
186 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
187 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
188 DEVMETHOD(pci_release_msi, pci_release_msi_method),
189 DEVMETHOD(pci_msi_count, pci_msi_count_method),
190 DEVMETHOD(pci_msix_count, pci_msix_count_method),
191
192 DEVMETHOD_END
193 };
194
195 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
196
197 static devclass_t pci_devclass;
198 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
199 MODULE_VERSION(pci, 1);
200
201 static char *pci_vendordata;
202 static size_t pci_vendordata_size;
203
204 struct pci_quirk {
205 uint32_t devid; /* Vendor/device of the card */
206 int type;
207 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
208 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
209 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
210 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
211 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
212 int arg1;
213 int arg2;
214 };
215
216 static const struct pci_quirk pci_quirks[] = {
217 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
218 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
219 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
220 /* As does the Serverworks OSB4 (the SMBus mapping register) */
221 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
222
223 /*
224 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
225 * or the CMIC-SL (AKA ServerWorks GC_LE).
226 */
227 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
228 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229
230 /*
231 * MSI doesn't work on earlier Intel chipsets including
232 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
233 */
234 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241
242 /*
243 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
244 * bridge.
245 */
246 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
247
248 /*
249 * MSI-X allocation doesn't work properly for devices passed through
250 * by VMware up to at least ESXi 5.1.
251 */
252 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */
253 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */
254
255 /*
256 * Some virtualization environments emulate an older chipset
257 * but support MSI just fine. QEMU uses the Intel 82440.
258 */
259 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
260
261 /*
262 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
263 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
264 * It prevents us from attaching hpet(4) when the bit is unset.
265 * Note this quirk only affects SB600 revision A13 and earlier.
266 * For SB600 A21 and later, firmware must set the bit to hide it.
267 * For SB700 and later, it is unused and hardcoded to zero.
268 */
269 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
270
271 { 0 }
272 };
273
274 /* map register information */
275 #define PCI_MAPMEM 0x01 /* memory map */
276 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
277 #define PCI_MAPPORT 0x04 /* port map */
278
279 struct devlist pci_devq;
280 uint32_t pci_generation;
281 uint32_t pci_numdevs = 0;
282 static int pcie_chipset, pcix_chipset;
283
284 /* sysctl vars */
285 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
286
287 static int pci_enable_io_modes = 1;
288 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
289 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
290 &pci_enable_io_modes, 1,
291 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
292 enable these bits correctly. We'd like to do this all the time, but there\n\
293 are some peripherals that this causes problems with.");
294
295 static int pci_do_realloc_bars = 0;
296 TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars);
297 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW,
298 &pci_do_realloc_bars, 0,
299 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan.");
300
301 static int pci_do_power_nodriver = 0;
302 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
303 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
304 &pci_do_power_nodriver, 0,
305 "Place a function into D3 state when no driver attaches to it. 0 means\n\
306 disable. 1 means conservatively place devices into D3 state. 2 means\n\
307 agressively place devices into D3 state. 3 means put absolutely everything\n\
308 in D3 state.");
309
310 int pci_do_power_resume = 1;
311 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
312 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
313 &pci_do_power_resume, 1,
314 "Transition from D3 -> D0 on resume.");
315
316 int pci_do_power_suspend = 1;
317 TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend);
318 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW,
319 &pci_do_power_suspend, 1,
320 "Transition from D0 -> D3 on suspend.");
321
322 static int pci_do_msi = 1;
323 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
324 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
325 "Enable support for MSI interrupts");
326
327 static int pci_do_msix = 1;
328 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
329 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
330 "Enable support for MSI-X interrupts");
331
332 static int pci_honor_msi_blacklist = 1;
333 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
334 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
335 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
336
337 #if defined(__i386__) || defined(__amd64__)
338 static int pci_usb_takeover = 1;
339 #else
340 static int pci_usb_takeover = 0;
341 #endif
342 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
343 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
344 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
345 Disable this if you depend on BIOS emulation of USB devices, that is\n\
346 you use USB devices (like keyboard or mouse) but do not load USB drivers");
347
348 static int
349 pci_has_quirk(uint32_t devid, int quirk)
350 {
351 const struct pci_quirk *q;
352
353 for (q = &pci_quirks[0]; q->devid; q++) {
354 if (q->devid == devid && q->type == quirk)
355 return (1);
356 }
357 return (0);
358 }
359
360 /* Find a device_t by bus/slot/function in domain 0 */
361
362 device_t
363 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
364 {
365
366 return (pci_find_dbsf(0, bus, slot, func));
367 }
368
369 /* Find a device_t by domain/bus/slot/function */
370
371 device_t
372 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
373 {
374 struct pci_devinfo *dinfo;
375
376 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
377 if ((dinfo->cfg.domain == domain) &&
378 (dinfo->cfg.bus == bus) &&
379 (dinfo->cfg.slot == slot) &&
380 (dinfo->cfg.func == func)) {
381 return (dinfo->cfg.dev);
382 }
383 }
384
385 return (NULL);
386 }
387
388 /* Find a device_t by vendor/device ID */
389
390 device_t
391 pci_find_device(uint16_t vendor, uint16_t device)
392 {
393 struct pci_devinfo *dinfo;
394
395 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
396 if ((dinfo->cfg.vendor == vendor) &&
397 (dinfo->cfg.device == device)) {
398 return (dinfo->cfg.dev);
399 }
400 }
401
402 return (NULL);
403 }
404
405 device_t
406 pci_find_class(uint8_t class, uint8_t subclass)
407 {
408 struct pci_devinfo *dinfo;
409
410 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
411 if (dinfo->cfg.baseclass == class &&
412 dinfo->cfg.subclass == subclass) {
413 return (dinfo->cfg.dev);
414 }
415 }
416
417 return (NULL);
418 }
419
420 static int
421 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
422 {
423 va_list ap;
424 int retval;
425
426 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
427 cfg->func);
428 va_start(ap, fmt);
429 retval += vprintf(fmt, ap);
430 va_end(ap);
431 return (retval);
432 }
433
434 /* return base address of memory or port map */
435
436 static pci_addr_t
437 pci_mapbase(uint64_t mapreg)
438 {
439
440 if (PCI_BAR_MEM(mapreg))
441 return (mapreg & PCIM_BAR_MEM_BASE);
442 else
443 return (mapreg & PCIM_BAR_IO_BASE);
444 }
445
446 /* return map type of memory or port map */
447
448 static const char *
449 pci_maptype(uint64_t mapreg)
450 {
451
452 if (PCI_BAR_IO(mapreg))
453 return ("I/O Port");
454 if (mapreg & PCIM_BAR_MEM_PREFETCH)
455 return ("Prefetchable Memory");
456 return ("Memory");
457 }
458
459 /* return log2 of map size decoded for memory or port map */
460
461 static int
462 pci_mapsize(uint64_t testval)
463 {
464 int ln2size;
465
466 testval = pci_mapbase(testval);
467 ln2size = 0;
468 if (testval != 0) {
469 while ((testval & 1) == 0)
470 {
471 ln2size++;
472 testval >>= 1;
473 }
474 }
475 return (ln2size);
476 }
477
478 /* return base address of device ROM */
479
480 static pci_addr_t
481 pci_rombase(uint64_t mapreg)
482 {
483
484 return (mapreg & PCIM_BIOS_ADDR_MASK);
485 }
486
487 /* return log2 of map size decided for device ROM */
488
489 static int
490 pci_romsize(uint64_t testval)
491 {
492 int ln2size;
493
494 testval = pci_rombase(testval);
495 ln2size = 0;
496 if (testval != 0) {
497 while ((testval & 1) == 0)
498 {
499 ln2size++;
500 testval >>= 1;
501 }
502 }
503 return (ln2size);
504 }
505
506 /* return log2 of address range supported by map register */
507
508 static int
509 pci_maprange(uint64_t mapreg)
510 {
511 int ln2range = 0;
512
513 if (PCI_BAR_IO(mapreg))
514 ln2range = 32;
515 else
516 switch (mapreg & PCIM_BAR_MEM_TYPE) {
517 case PCIM_BAR_MEM_32:
518 ln2range = 32;
519 break;
520 case PCIM_BAR_MEM_1MB:
521 ln2range = 20;
522 break;
523 case PCIM_BAR_MEM_64:
524 ln2range = 64;
525 break;
526 }
527 return (ln2range);
528 }
529
530 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
531
532 static void
533 pci_fixancient(pcicfgregs *cfg)
534 {
535 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
536 return;
537
538 /* PCI to PCI bridges use header type 1 */
539 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
540 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
541 }
542
543 /* extract header type specific config data */
544
545 static void
546 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
547 {
548 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
549 switch (cfg->hdrtype & PCIM_HDRTYPE) {
550 case PCIM_HDRTYPE_NORMAL:
551 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
552 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
553 cfg->nummaps = PCI_MAXMAPS_0;
554 break;
555 case PCIM_HDRTYPE_BRIDGE:
556 cfg->nummaps = PCI_MAXMAPS_1;
557 break;
558 case PCIM_HDRTYPE_CARDBUS:
559 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
560 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
561 cfg->nummaps = PCI_MAXMAPS_2;
562 break;
563 }
564 #undef REG
565 }
566
567 /* read configuration header into pcicfgregs structure */
568 struct pci_devinfo *
569 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
570 {
571 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
572 pcicfgregs *cfg = NULL;
573 struct pci_devinfo *devlist_entry;
574 struct devlist *devlist_head;
575
576 devlist_head = &pci_devq;
577
578 devlist_entry = NULL;
579
580 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
581 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
582 if (devlist_entry == NULL)
583 return (NULL);
584
585 cfg = &devlist_entry->cfg;
586
587 cfg->domain = d;
588 cfg->bus = b;
589 cfg->slot = s;
590 cfg->func = f;
591 cfg->vendor = REG(PCIR_VENDOR, 2);
592 cfg->device = REG(PCIR_DEVICE, 2);
593 cfg->cmdreg = REG(PCIR_COMMAND, 2);
594 cfg->statreg = REG(PCIR_STATUS, 2);
595 cfg->baseclass = REG(PCIR_CLASS, 1);
596 cfg->subclass = REG(PCIR_SUBCLASS, 1);
597 cfg->progif = REG(PCIR_PROGIF, 1);
598 cfg->revid = REG(PCIR_REVID, 1);
599 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
600 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
601 cfg->lattimer = REG(PCIR_LATTIMER, 1);
602 cfg->intpin = REG(PCIR_INTPIN, 1);
603 cfg->intline = REG(PCIR_INTLINE, 1);
604
605 cfg->mingnt = REG(PCIR_MINGNT, 1);
606 cfg->maxlat = REG(PCIR_MAXLAT, 1);
607
608 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
609 cfg->hdrtype &= ~PCIM_MFDEV;
610 STAILQ_INIT(&cfg->maps);
611
612 pci_fixancient(cfg);
613 pci_hdrtypedata(pcib, b, s, f, cfg);
614
615 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
616 pci_read_cap(pcib, cfg);
617
618 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
619
620 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
621 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
622 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
623 devlist_entry->conf.pc_sel.pc_func = cfg->func;
624 devlist_entry->conf.pc_hdr = cfg->hdrtype;
625
626 devlist_entry->conf.pc_subvendor = cfg->subvendor;
627 devlist_entry->conf.pc_subdevice = cfg->subdevice;
628 devlist_entry->conf.pc_vendor = cfg->vendor;
629 devlist_entry->conf.pc_device = cfg->device;
630
631 devlist_entry->conf.pc_class = cfg->baseclass;
632 devlist_entry->conf.pc_subclass = cfg->subclass;
633 devlist_entry->conf.pc_progif = cfg->progif;
634 devlist_entry->conf.pc_revid = cfg->revid;
635
636 pci_numdevs++;
637 pci_generation++;
638 }
639 return (devlist_entry);
640 #undef REG
641 }
642
643 static void
644 pci_read_cap(device_t pcib, pcicfgregs *cfg)
645 {
646 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
647 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
648 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
649 uint64_t addr;
650 #endif
651 uint32_t val;
652 int ptr, nextptr, ptrptr;
653
654 switch (cfg->hdrtype & PCIM_HDRTYPE) {
655 case PCIM_HDRTYPE_NORMAL:
656 case PCIM_HDRTYPE_BRIDGE:
657 ptrptr = PCIR_CAP_PTR;
658 break;
659 case PCIM_HDRTYPE_CARDBUS:
660 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
661 break;
662 default:
663 return; /* no extended capabilities support */
664 }
665 nextptr = REG(ptrptr, 1); /* sanity check? */
666
667 /*
668 * Read capability entries.
669 */
670 while (nextptr != 0) {
671 /* Sanity check */
672 if (nextptr > 255) {
673 printf("illegal PCI extended capability offset %d\n",
674 nextptr);
675 return;
676 }
677 /* Find the next entry */
678 ptr = nextptr;
679 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
680
681 /* Process this entry */
682 switch (REG(ptr + PCICAP_ID, 1)) {
683 case PCIY_PMG: /* PCI power management */
684 if (cfg->pp.pp_cap == 0) {
685 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
686 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
687 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
688 if ((nextptr - ptr) > PCIR_POWER_DATA)
689 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
690 }
691 break;
692 case PCIY_HT: /* HyperTransport */
693 /* Determine HT-specific capability type. */
694 val = REG(ptr + PCIR_HT_COMMAND, 2);
695
696 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
697 cfg->ht.ht_slave = ptr;
698
699 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
700 switch (val & PCIM_HTCMD_CAP_MASK) {
701 case PCIM_HTCAP_MSI_MAPPING:
702 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
703 /* Sanity check the mapping window. */
704 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
705 4);
706 addr <<= 32;
707 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
708 4);
709 if (addr != MSI_INTEL_ADDR_BASE)
710 device_printf(pcib,
711 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
712 cfg->domain, cfg->bus,
713 cfg->slot, cfg->func,
714 (long long)addr);
715 } else
716 addr = MSI_INTEL_ADDR_BASE;
717
718 cfg->ht.ht_msimap = ptr;
719 cfg->ht.ht_msictrl = val;
720 cfg->ht.ht_msiaddr = addr;
721 break;
722 }
723 #endif
724 break;
725 case PCIY_MSI: /* PCI MSI */
726 cfg->msi.msi_location = ptr;
727 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
728 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
729 PCIM_MSICTRL_MMC_MASK)>>1);
730 break;
731 case PCIY_MSIX: /* PCI MSI-X */
732 cfg->msix.msix_location = ptr;
733 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
734 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
735 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
736 val = REG(ptr + PCIR_MSIX_TABLE, 4);
737 cfg->msix.msix_table_bar = PCIR_BAR(val &
738 PCIM_MSIX_BIR_MASK);
739 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
740 val = REG(ptr + PCIR_MSIX_PBA, 4);
741 cfg->msix.msix_pba_bar = PCIR_BAR(val &
742 PCIM_MSIX_BIR_MASK);
743 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
744 break;
745 case PCIY_VPD: /* PCI Vital Product Data */
746 cfg->vpd.vpd_reg = ptr;
747 break;
748 case PCIY_SUBVENDOR:
749 /* Should always be true. */
750 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
751 PCIM_HDRTYPE_BRIDGE) {
752 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
753 cfg->subvendor = val & 0xffff;
754 cfg->subdevice = val >> 16;
755 }
756 break;
757 case PCIY_PCIX: /* PCI-X */
758 /*
759 * Assume we have a PCI-X chipset if we have
760 * at least one PCI-PCI bridge with a PCI-X
761 * capability. Note that some systems with
762 * PCI-express or HT chipsets might match on
763 * this check as well.
764 */
765 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
766 PCIM_HDRTYPE_BRIDGE)
767 pcix_chipset = 1;
768 break;
769 case PCIY_EXPRESS: /* PCI-express */
770 /*
771 * Assume we have a PCI-express chipset if we have
772 * at least one PCI-express device.
773 */
774 pcie_chipset = 1;
775 break;
776 default:
777 break;
778 }
779 }
780
781 #if defined(__powerpc__)
782 /*
783 * Enable the MSI mapping window for all HyperTransport
784 * slaves. PCI-PCI bridges have their windows enabled via
785 * PCIB_MAP_MSI().
786 */
787 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
788 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
789 device_printf(pcib,
790 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
791 cfg->domain, cfg->bus, cfg->slot, cfg->func);
792 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
793 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
794 2);
795 }
796 #endif
797 /* REG and WREG use carry through to next functions */
798 }
799
800 /*
801 * PCI Vital Product Data
802 */
803
804 #define PCI_VPD_TIMEOUT 1000000
805
806 static int
807 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
808 {
809 int count = PCI_VPD_TIMEOUT;
810
811 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
812
813 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
814
815 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
816 if (--count < 0)
817 return (ENXIO);
818 DELAY(1); /* limit looping */
819 }
820 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
821
822 return (0);
823 }
824
825 #if 0
826 static int
827 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
828 {
829 int count = PCI_VPD_TIMEOUT;
830
831 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
832
833 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
834 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
835 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
836 if (--count < 0)
837 return (ENXIO);
838 DELAY(1); /* limit looping */
839 }
840
841 return (0);
842 }
843 #endif
844
845 #undef PCI_VPD_TIMEOUT
846
847 struct vpd_readstate {
848 device_t pcib;
849 pcicfgregs *cfg;
850 uint32_t val;
851 int bytesinval;
852 int off;
853 uint8_t cksum;
854 };
855
856 static int
857 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
858 {
859 uint32_t reg;
860 uint8_t byte;
861
862 if (vrs->bytesinval == 0) {
863 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
864 return (ENXIO);
865 vrs->val = le32toh(reg);
866 vrs->off += 4;
867 byte = vrs->val & 0xff;
868 vrs->bytesinval = 3;
869 } else {
870 vrs->val = vrs->val >> 8;
871 byte = vrs->val & 0xff;
872 vrs->bytesinval--;
873 }
874
875 vrs->cksum += byte;
876 *data = byte;
877 return (0);
878 }
879
880 static void
881 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
882 {
883 struct vpd_readstate vrs;
884 int state;
885 int name;
886 int remain;
887 int i;
888 int alloc, off; /* alloc/off for RO/W arrays */
889 int cksumvalid;
890 int dflen;
891 uint8_t byte;
892 uint8_t byte2;
893
894 /* init vpd reader */
895 vrs.bytesinval = 0;
896 vrs.off = 0;
897 vrs.pcib = pcib;
898 vrs.cfg = cfg;
899 vrs.cksum = 0;
900
901 state = 0;
902 name = remain = i = 0; /* shut up stupid gcc */
903 alloc = off = 0; /* shut up stupid gcc */
904 dflen = 0; /* shut up stupid gcc */
905 cksumvalid = -1;
906 while (state >= 0) {
907 if (vpd_nextbyte(&vrs, &byte)) {
908 state = -2;
909 break;
910 }
911 #if 0
912 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
913 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
914 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
915 #endif
916 switch (state) {
917 case 0: /* item name */
918 if (byte & 0x80) {
919 if (vpd_nextbyte(&vrs, &byte2)) {
920 state = -2;
921 break;
922 }
923 remain = byte2;
924 if (vpd_nextbyte(&vrs, &byte2)) {
925 state = -2;
926 break;
927 }
928 remain |= byte2 << 8;
929 if (remain > (0x7f*4 - vrs.off)) {
930 state = -1;
931 printf(
932 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
933 cfg->domain, cfg->bus, cfg->slot,
934 cfg->func, remain);
935 }
936 name = byte & 0x7f;
937 } else {
938 remain = byte & 0x7;
939 name = (byte >> 3) & 0xf;
940 }
941 switch (name) {
942 case 0x2: /* String */
943 cfg->vpd.vpd_ident = malloc(remain + 1,
944 M_DEVBUF, M_WAITOK);
945 i = 0;
946 state = 1;
947 break;
948 case 0xf: /* End */
949 state = -1;
950 break;
951 case 0x10: /* VPD-R */
952 alloc = 8;
953 off = 0;
954 cfg->vpd.vpd_ros = malloc(alloc *
955 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
956 M_WAITOK | M_ZERO);
957 state = 2;
958 break;
959 case 0x11: /* VPD-W */
960 alloc = 8;
961 off = 0;
962 cfg->vpd.vpd_w = malloc(alloc *
963 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
964 M_WAITOK | M_ZERO);
965 state = 5;
966 break;
967 default: /* Invalid data, abort */
968 state = -1;
969 break;
970 }
971 break;
972
973 case 1: /* Identifier String */
974 cfg->vpd.vpd_ident[i++] = byte;
975 remain--;
976 if (remain == 0) {
977 cfg->vpd.vpd_ident[i] = '\0';
978 state = 0;
979 }
980 break;
981
982 case 2: /* VPD-R Keyword Header */
983 if (off == alloc) {
984 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
985 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
986 M_DEVBUF, M_WAITOK | M_ZERO);
987 }
988 cfg->vpd.vpd_ros[off].keyword[0] = byte;
989 if (vpd_nextbyte(&vrs, &byte2)) {
990 state = -2;
991 break;
992 }
993 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
994 if (vpd_nextbyte(&vrs, &byte2)) {
995 state = -2;
996 break;
997 }
998 dflen = byte2;
999 if (dflen == 0 &&
1000 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1001 2) == 0) {
1002 /*
1003 * if this happens, we can't trust the rest
1004 * of the VPD.
1005 */
1006 printf(
1007 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1008 cfg->domain, cfg->bus, cfg->slot,
1009 cfg->func, dflen);
1010 cksumvalid = 0;
1011 state = -1;
1012 break;
1013 } else if (dflen == 0) {
1014 cfg->vpd.vpd_ros[off].value = malloc(1 *
1015 sizeof(*cfg->vpd.vpd_ros[off].value),
1016 M_DEVBUF, M_WAITOK);
1017 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1018 } else
1019 cfg->vpd.vpd_ros[off].value = malloc(
1020 (dflen + 1) *
1021 sizeof(*cfg->vpd.vpd_ros[off].value),
1022 M_DEVBUF, M_WAITOK);
1023 remain -= 3;
1024 i = 0;
1025 /* keep in sync w/ state 3's transistions */
1026 if (dflen == 0 && remain == 0)
1027 state = 0;
1028 else if (dflen == 0)
1029 state = 2;
1030 else
1031 state = 3;
1032 break;
1033
1034 case 3: /* VPD-R Keyword Value */
1035 cfg->vpd.vpd_ros[off].value[i++] = byte;
1036 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1037 "RV", 2) == 0 && cksumvalid == -1) {
1038 if (vrs.cksum == 0)
1039 cksumvalid = 1;
1040 else {
1041 if (bootverbose)
1042 printf(
1043 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1044 cfg->domain, cfg->bus,
1045 cfg->slot, cfg->func,
1046 vrs.cksum);
1047 cksumvalid = 0;
1048 state = -1;
1049 break;
1050 }
1051 }
1052 dflen--;
1053 remain--;
1054 /* keep in sync w/ state 2's transistions */
1055 if (dflen == 0)
1056 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1057 if (dflen == 0 && remain == 0) {
1058 cfg->vpd.vpd_rocnt = off;
1059 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1060 off * sizeof(*cfg->vpd.vpd_ros),
1061 M_DEVBUF, M_WAITOK | M_ZERO);
1062 state = 0;
1063 } else if (dflen == 0)
1064 state = 2;
1065 break;
1066
1067 case 4:
1068 remain--;
1069 if (remain == 0)
1070 state = 0;
1071 break;
1072
1073 case 5: /* VPD-W Keyword Header */
1074 if (off == alloc) {
1075 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1076 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1077 M_DEVBUF, M_WAITOK | M_ZERO);
1078 }
1079 cfg->vpd.vpd_w[off].keyword[0] = byte;
1080 if (vpd_nextbyte(&vrs, &byte2)) {
1081 state = -2;
1082 break;
1083 }
1084 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1085 if (vpd_nextbyte(&vrs, &byte2)) {
1086 state = -2;
1087 break;
1088 }
1089 cfg->vpd.vpd_w[off].len = dflen = byte2;
1090 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1091 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1092 sizeof(*cfg->vpd.vpd_w[off].value),
1093 M_DEVBUF, M_WAITOK);
1094 remain -= 3;
1095 i = 0;
1096 /* keep in sync w/ state 6's transistions */
1097 if (dflen == 0 && remain == 0)
1098 state = 0;
1099 else if (dflen == 0)
1100 state = 5;
1101 else
1102 state = 6;
1103 break;
1104
1105 case 6: /* VPD-W Keyword Value */
1106 cfg->vpd.vpd_w[off].value[i++] = byte;
1107 dflen--;
1108 remain--;
1109 /* keep in sync w/ state 5's transistions */
1110 if (dflen == 0)
1111 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1112 if (dflen == 0 && remain == 0) {
1113 cfg->vpd.vpd_wcnt = off;
1114 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1115 off * sizeof(*cfg->vpd.vpd_w),
1116 M_DEVBUF, M_WAITOK | M_ZERO);
1117 state = 0;
1118 } else if (dflen == 0)
1119 state = 5;
1120 break;
1121
1122 default:
1123 printf("pci%d:%d:%d:%d: invalid state: %d\n",
1124 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1125 state);
1126 state = -1;
1127 break;
1128 }
1129 }
1130
1131 if (cksumvalid == 0 || state < -1) {
1132 /* read-only data bad, clean up */
1133 if (cfg->vpd.vpd_ros != NULL) {
1134 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1135 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1136 free(cfg->vpd.vpd_ros, M_DEVBUF);
1137 cfg->vpd.vpd_ros = NULL;
1138 }
1139 }
1140 if (state < -1) {
1141 /* I/O error, clean up */
1142 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1143 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1144 if (cfg->vpd.vpd_ident != NULL) {
1145 free(cfg->vpd.vpd_ident, M_DEVBUF);
1146 cfg->vpd.vpd_ident = NULL;
1147 }
1148 if (cfg->vpd.vpd_w != NULL) {
1149 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1150 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1151 free(cfg->vpd.vpd_w, M_DEVBUF);
1152 cfg->vpd.vpd_w = NULL;
1153 }
1154 }
1155 cfg->vpd.vpd_cached = 1;
1156 #undef REG
1157 #undef WREG
1158 }
1159
1160 int
1161 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1162 {
1163 struct pci_devinfo *dinfo = device_get_ivars(child);
1164 pcicfgregs *cfg = &dinfo->cfg;
1165
1166 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1167 pci_read_vpd(device_get_parent(dev), cfg);
1168
1169 *identptr = cfg->vpd.vpd_ident;
1170
1171 if (*identptr == NULL)
1172 return (ENXIO);
1173
1174 return (0);
1175 }
1176
1177 int
1178 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1179 const char **vptr)
1180 {
1181 struct pci_devinfo *dinfo = device_get_ivars(child);
1182 pcicfgregs *cfg = &dinfo->cfg;
1183 int i;
1184
1185 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1186 pci_read_vpd(device_get_parent(dev), cfg);
1187
1188 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1189 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1190 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1191 *vptr = cfg->vpd.vpd_ros[i].value;
1192 return (0);
1193 }
1194
1195 *vptr = NULL;
1196 return (ENXIO);
1197 }
1198
1199 /*
1200 * Find the requested extended capability and return the offset in
1201 * configuration space via the pointer provided. The function returns
1202 * 0 on success and error code otherwise.
1203 */
1204 int
1205 pci_find_extcap_method(device_t dev, device_t child, int capability,
1206 int *capreg)
1207 {
1208 struct pci_devinfo *dinfo = device_get_ivars(child);
1209 pcicfgregs *cfg = &dinfo->cfg;
1210 u_int32_t status;
1211 u_int8_t ptr;
1212
1213 /*
1214 * Check the CAP_LIST bit of the PCI status register first.
1215 */
1216 status = pci_read_config(child, PCIR_STATUS, 2);
1217 if (!(status & PCIM_STATUS_CAPPRESENT))
1218 return (ENXIO);
1219
1220 /*
1221 * Determine the start pointer of the capabilities list.
1222 */
1223 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1224 case PCIM_HDRTYPE_NORMAL:
1225 case PCIM_HDRTYPE_BRIDGE:
1226 ptr = PCIR_CAP_PTR;
1227 break;
1228 case PCIM_HDRTYPE_CARDBUS:
1229 ptr = PCIR_CAP_PTR_2;
1230 break;
1231 default:
1232 /* XXX: panic? */
1233 return (ENXIO); /* no extended capabilities support */
1234 }
1235 ptr = pci_read_config(child, ptr, 1);
1236
1237 /*
1238 * Traverse the capabilities list.
1239 */
1240 while (ptr != 0) {
1241 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1242 if (capreg != NULL)
1243 *capreg = ptr;
1244 return (0);
1245 }
1246 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1247 }
1248
1249 return (ENOENT);
1250 }
1251
1252 /*
1253 * Support for MSI-X message interrupts.
1254 */
1255 void
1256 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1257 {
1258 struct pci_devinfo *dinfo = device_get_ivars(dev);
1259 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1260 uint32_t offset;
1261
1262 KASSERT(msix->msix_table_len > index, ("bogus index"));
1263 offset = msix->msix_table_offset + index * 16;
1264 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1265 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1266 bus_write_4(msix->msix_table_res, offset + 8, data);
1267
1268 /* Enable MSI -> HT mapping. */
1269 pci_ht_map_msi(dev, address);
1270 }
1271
1272 void
1273 pci_mask_msix(device_t dev, u_int index)
1274 {
1275 struct pci_devinfo *dinfo = device_get_ivars(dev);
1276 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1277 uint32_t offset, val;
1278
1279 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1280 offset = msix->msix_table_offset + index * 16 + 12;
1281 val = bus_read_4(msix->msix_table_res, offset);
1282 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1283 val |= PCIM_MSIX_VCTRL_MASK;
1284 bus_write_4(msix->msix_table_res, offset, val);
1285 }
1286 }
1287
1288 void
1289 pci_unmask_msix(device_t dev, u_int index)
1290 {
1291 struct pci_devinfo *dinfo = device_get_ivars(dev);
1292 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1293 uint32_t offset, val;
1294
1295 KASSERT(msix->msix_table_len > index, ("bogus index"));
1296 offset = msix->msix_table_offset + index * 16 + 12;
1297 val = bus_read_4(msix->msix_table_res, offset);
1298 if (val & PCIM_MSIX_VCTRL_MASK) {
1299 val &= ~PCIM_MSIX_VCTRL_MASK;
1300 bus_write_4(msix->msix_table_res, offset, val);
1301 }
1302 }
1303
1304 int
1305 pci_pending_msix(device_t dev, u_int index)
1306 {
1307 struct pci_devinfo *dinfo = device_get_ivars(dev);
1308 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1309 uint32_t offset, bit;
1310
1311 KASSERT(msix->msix_table_len > index, ("bogus index"));
1312 offset = msix->msix_pba_offset + (index / 32) * 4;
1313 bit = 1 << index % 32;
1314 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1315 }
1316
1317 /*
1318 * Restore MSI-X registers and table during resume. If MSI-X is
1319 * enabled then walk the virtual table to restore the actual MSI-X
1320 * table.
1321 */
1322 static void
1323 pci_resume_msix(device_t dev)
1324 {
1325 struct pci_devinfo *dinfo = device_get_ivars(dev);
1326 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1327 struct msix_table_entry *mte;
1328 struct msix_vector *mv;
1329 int i;
1330
1331 if (msix->msix_alloc > 0) {
1332 /* First, mask all vectors. */
1333 for (i = 0; i < msix->msix_msgnum; i++)
1334 pci_mask_msix(dev, i);
1335
1336 /* Second, program any messages with at least one handler. */
1337 for (i = 0; i < msix->msix_table_len; i++) {
1338 mte = &msix->msix_table[i];
1339 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1340 continue;
1341 mv = &msix->msix_vectors[mte->mte_vector - 1];
1342 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1343 pci_unmask_msix(dev, i);
1344 }
1345 }
1346 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1347 msix->msix_ctrl, 2);
1348 }
1349
1350 /*
1351 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1352 * returned in *count. After this function returns, each message will be
1353 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1354 */
1355 int
1356 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1357 {
1358 struct pci_devinfo *dinfo = device_get_ivars(child);
1359 pcicfgregs *cfg = &dinfo->cfg;
1360 struct resource_list_entry *rle;
1361 int actual, error, i, irq, max;
1362
1363 /* Don't let count == 0 get us into trouble. */
1364 if (*count == 0)
1365 return (EINVAL);
1366
1367 /* If rid 0 is allocated, then fail. */
1368 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1369 if (rle != NULL && rle->res != NULL)
1370 return (ENXIO);
1371
1372 /* Already have allocated messages? */
1373 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1374 return (ENXIO);
1375
1376 /* If MSI-X is blacklisted for this system, fail. */
1377 if (pci_msix_blacklisted())
1378 return (ENXIO);
1379
1380 /* MSI-X capability present? */
1381 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1382 return (ENODEV);
1383
1384 /* Make sure the appropriate BARs are mapped. */
1385 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1386 cfg->msix.msix_table_bar);
1387 if (rle == NULL || rle->res == NULL ||
1388 !(rman_get_flags(rle->res) & RF_ACTIVE))
1389 return (ENXIO);
1390 cfg->msix.msix_table_res = rle->res;
1391 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1392 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1393 cfg->msix.msix_pba_bar);
1394 if (rle == NULL || rle->res == NULL ||
1395 !(rman_get_flags(rle->res) & RF_ACTIVE))
1396 return (ENXIO);
1397 }
1398 cfg->msix.msix_pba_res = rle->res;
1399
1400 if (bootverbose)
1401 device_printf(child,
1402 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1403 *count, cfg->msix.msix_msgnum);
1404 max = min(*count, cfg->msix.msix_msgnum);
1405 for (i = 0; i < max; i++) {
1406 /* Allocate a message. */
1407 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1408 if (error) {
1409 if (i == 0)
1410 return (error);
1411 break;
1412 }
1413 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1414 irq, 1);
1415 }
1416 actual = i;
1417
1418 if (bootverbose) {
1419 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1420 if (actual == 1)
1421 device_printf(child, "using IRQ %lu for MSI-X\n",
1422 rle->start);
1423 else {
1424 int run;
1425
1426 /*
1427 * Be fancy and try to print contiguous runs of
1428 * IRQ values as ranges. 'irq' is the previous IRQ.
1429 * 'run' is true if we are in a range.
1430 */
1431 device_printf(child, "using IRQs %lu", rle->start);
1432 irq = rle->start;
1433 run = 0;
1434 for (i = 1; i < actual; i++) {
1435 rle = resource_list_find(&dinfo->resources,
1436 SYS_RES_IRQ, i + 1);
1437
1438 /* Still in a run? */
1439 if (rle->start == irq + 1) {
1440 run = 1;
1441 irq++;
1442 continue;
1443 }
1444
1445 /* Finish previous range. */
1446 if (run) {
1447 printf("-%d", irq);
1448 run = 0;
1449 }
1450
1451 /* Start new range. */
1452 printf(",%lu", rle->start);
1453 irq = rle->start;
1454 }
1455
1456 /* Unfinished range? */
1457 if (run)
1458 printf("-%d", irq);
1459 printf(" for MSI-X\n");
1460 }
1461 }
1462
1463 /* Mask all vectors. */
1464 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1465 pci_mask_msix(child, i);
1466
1467 /* Allocate and initialize vector data and virtual table. */
1468 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1469 M_DEVBUF, M_WAITOK | M_ZERO);
1470 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1471 M_DEVBUF, M_WAITOK | M_ZERO);
1472 for (i = 0; i < actual; i++) {
1473 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1474 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1475 cfg->msix.msix_table[i].mte_vector = i + 1;
1476 }
1477
1478 /* Update control register to enable MSI-X. */
1479 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1480 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1481 cfg->msix.msix_ctrl, 2);
1482
1483 /* Update counts of alloc'd messages. */
1484 cfg->msix.msix_alloc = actual;
1485 cfg->msix.msix_table_len = actual;
1486 *count = actual;
1487 return (0);
1488 }
1489
1490 /*
1491 * By default, pci_alloc_msix() will assign the allocated IRQ
1492 * resources consecutively to the first N messages in the MSI-X table.
1493 * However, device drivers may want to use different layouts if they
1494 * either receive fewer messages than they asked for, or they wish to
1495 * populate the MSI-X table sparsely. This method allows the driver
1496 * to specify what layout it wants. It must be called after a
1497 * successful pci_alloc_msix() but before any of the associated
1498 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1499 *
1500 * The 'vectors' array contains 'count' message vectors. The array
1501 * maps directly to the MSI-X table in that index 0 in the array
1502 * specifies the vector for the first message in the MSI-X table, etc.
1503 * The vector value in each array index can either be 0 to indicate
1504 * that no vector should be assigned to a message slot, or it can be a
1505 * number from 1 to N (where N is the count returned from a
1506 * succcessful call to pci_alloc_msix()) to indicate which message
1507 * vector (IRQ) to be used for the corresponding message.
1508 *
1509 * On successful return, each message with a non-zero vector will have
1510 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1511 * 1. Additionally, if any of the IRQs allocated via the previous
1512 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1513 * will be freed back to the system automatically.
1514 *
1515 * For example, suppose a driver has a MSI-X table with 6 messages and
1516 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1517 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1518 * C. After the call to pci_alloc_msix(), the device will be setup to
1519 * have an MSI-X table of ABC--- (where - means no vector assigned).
1520 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1521 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1522 * be freed back to the system. This device will also have valid
1523 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1524 *
1525 * In any case, the SYS_RES_IRQ rid X will always map to the message
1526 * at MSI-X table index X - 1 and will only be valid if a vector is
1527 * assigned to that table entry.
1528 */
1529 int
1530 pci_remap_msix_method(device_t dev, device_t child, int count,
1531 const u_int *vectors)
1532 {
1533 struct pci_devinfo *dinfo = device_get_ivars(child);
1534 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1535 struct resource_list_entry *rle;
1536 int i, irq, j, *used;
1537
1538 /*
1539 * Have to have at least one message in the table but the
1540 * table can't be bigger than the actual MSI-X table in the
1541 * device.
1542 */
1543 if (count == 0 || count > msix->msix_msgnum)
1544 return (EINVAL);
1545
1546 /* Sanity check the vectors. */
1547 for (i = 0; i < count; i++)
1548 if (vectors[i] > msix->msix_alloc)
1549 return (EINVAL);
1550
1551 /*
1552 * Make sure there aren't any holes in the vectors to be used.
1553 * It's a big pain to support it, and it doesn't really make
1554 * sense anyway. Also, at least one vector must be used.
1555 */
1556 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1557 M_ZERO);
1558 for (i = 0; i < count; i++)
1559 if (vectors[i] != 0)
1560 used[vectors[i] - 1] = 1;
1561 for (i = 0; i < msix->msix_alloc - 1; i++)
1562 if (used[i] == 0 && used[i + 1] == 1) {
1563 free(used, M_DEVBUF);
1564 return (EINVAL);
1565 }
1566 if (used[0] != 1) {
1567 free(used, M_DEVBUF);
1568 return (EINVAL);
1569 }
1570
1571 /* Make sure none of the resources are allocated. */
1572 for (i = 0; i < msix->msix_table_len; i++) {
1573 if (msix->msix_table[i].mte_vector == 0)
1574 continue;
1575 if (msix->msix_table[i].mte_handlers > 0)
1576 return (EBUSY);
1577 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1578 KASSERT(rle != NULL, ("missing resource"));
1579 if (rle->res != NULL)
1580 return (EBUSY);
1581 }
1582
1583 /* Free the existing resource list entries. */
1584 for (i = 0; i < msix->msix_table_len; i++) {
1585 if (msix->msix_table[i].mte_vector == 0)
1586 continue;
1587 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1588 }
1589
1590 /*
1591 * Build the new virtual table keeping track of which vectors are
1592 * used.
1593 */
1594 free(msix->msix_table, M_DEVBUF);
1595 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1596 M_DEVBUF, M_WAITOK | M_ZERO);
1597 for (i = 0; i < count; i++)
1598 msix->msix_table[i].mte_vector = vectors[i];
1599 msix->msix_table_len = count;
1600
1601 /* Free any unused IRQs and resize the vectors array if necessary. */
1602 j = msix->msix_alloc - 1;
1603 if (used[j] == 0) {
1604 struct msix_vector *vec;
1605
1606 while (used[j] == 0) {
1607 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1608 msix->msix_vectors[j].mv_irq);
1609 j--;
1610 }
1611 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1612 M_WAITOK);
1613 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1614 (j + 1));
1615 free(msix->msix_vectors, M_DEVBUF);
1616 msix->msix_vectors = vec;
1617 msix->msix_alloc = j + 1;
1618 }
1619 free(used, M_DEVBUF);
1620
1621 /* Map the IRQs onto the rids. */
1622 for (i = 0; i < count; i++) {
1623 if (vectors[i] == 0)
1624 continue;
1625 irq = msix->msix_vectors[vectors[i]].mv_irq;
1626 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1627 irq, 1);
1628 }
1629
1630 if (bootverbose) {
1631 device_printf(child, "Remapped MSI-X IRQs as: ");
1632 for (i = 0; i < count; i++) {
1633 if (i != 0)
1634 printf(", ");
1635 if (vectors[i] == 0)
1636 printf("---");
1637 else
1638 printf("%d",
1639 msix->msix_vectors[vectors[i]].mv_irq);
1640 }
1641 printf("\n");
1642 }
1643
1644 return (0);
1645 }
1646
1647 static int
1648 pci_release_msix(device_t dev, device_t child)
1649 {
1650 struct pci_devinfo *dinfo = device_get_ivars(child);
1651 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1652 struct resource_list_entry *rle;
1653 int i;
1654
1655 /* Do we have any messages to release? */
1656 if (msix->msix_alloc == 0)
1657 return (ENODEV);
1658
1659 /* Make sure none of the resources are allocated. */
1660 for (i = 0; i < msix->msix_table_len; i++) {
1661 if (msix->msix_table[i].mte_vector == 0)
1662 continue;
1663 if (msix->msix_table[i].mte_handlers > 0)
1664 return (EBUSY);
1665 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1666 KASSERT(rle != NULL, ("missing resource"));
1667 if (rle->res != NULL)
1668 return (EBUSY);
1669 }
1670
1671 /* Update control register to disable MSI-X. */
1672 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1673 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1674 msix->msix_ctrl, 2);
1675
1676 /* Free the resource list entries. */
1677 for (i = 0; i < msix->msix_table_len; i++) {
1678 if (msix->msix_table[i].mte_vector == 0)
1679 continue;
1680 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1681 }
1682 free(msix->msix_table, M_DEVBUF);
1683 msix->msix_table_len = 0;
1684
1685 /* Release the IRQs. */
1686 for (i = 0; i < msix->msix_alloc; i++)
1687 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1688 msix->msix_vectors[i].mv_irq);
1689 free(msix->msix_vectors, M_DEVBUF);
1690 msix->msix_alloc = 0;
1691 return (0);
1692 }
1693
1694 /*
1695 * Return the max supported MSI-X messages this device supports.
1696 * Basically, assuming the MD code can alloc messages, this function
1697 * should return the maximum value that pci_alloc_msix() can return.
1698 * Thus, it is subject to the tunables, etc.
1699 */
1700 int
1701 pci_msix_count_method(device_t dev, device_t child)
1702 {
1703 struct pci_devinfo *dinfo = device_get_ivars(child);
1704 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1705
1706 if (pci_do_msix && msix->msix_location != 0)
1707 return (msix->msix_msgnum);
1708 return (0);
1709 }
1710
1711 /*
1712 * HyperTransport MSI mapping control
1713 */
1714 void
1715 pci_ht_map_msi(device_t dev, uint64_t addr)
1716 {
1717 struct pci_devinfo *dinfo = device_get_ivars(dev);
1718 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1719
1720 if (!ht->ht_msimap)
1721 return;
1722
1723 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1724 ht->ht_msiaddr >> 20 == addr >> 20) {
1725 /* Enable MSI -> HT mapping. */
1726 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1727 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1728 ht->ht_msictrl, 2);
1729 }
1730
1731 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1732 /* Disable MSI -> HT mapping. */
1733 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1734 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1735 ht->ht_msictrl, 2);
1736 }
1737 }
1738
1739 int
1740 pci_get_max_read_req(device_t dev)
1741 {
1742 int cap;
1743 uint16_t val;
1744
1745 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1746 return (0);
1747 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1748 val &= PCIEM_CTL_MAX_READ_REQUEST;
1749 val >>= 12;
1750 return (1 << (val + 7));
1751 }
1752
1753 int
1754 pci_set_max_read_req(device_t dev, int size)
1755 {
1756 int cap;
1757 uint16_t val;
1758
1759 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1760 return (0);
1761 if (size < 128)
1762 size = 128;
1763 if (size > 4096)
1764 size = 4096;
1765 size = (1 << (fls(size) - 1));
1766 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1767 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
1768 val |= (fls(size) - 8) << 12;
1769 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
1770 return (size);
1771 }
1772
1773 /*
1774 * Support for MSI message signalled interrupts.
1775 */
1776 void
1777 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1778 {
1779 struct pci_devinfo *dinfo = device_get_ivars(dev);
1780 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1781
1782 /* Write data and address values. */
1783 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1784 address & 0xffffffff, 4);
1785 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1786 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1787 address >> 32, 4);
1788 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1789 data, 2);
1790 } else
1791 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1792 2);
1793
1794 /* Enable MSI in the control register. */
1795 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1796 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1797 2);
1798
1799 /* Enable MSI -> HT mapping. */
1800 pci_ht_map_msi(dev, address);
1801 }
1802
1803 void
1804 pci_disable_msi(device_t dev)
1805 {
1806 struct pci_devinfo *dinfo = device_get_ivars(dev);
1807 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1808
1809 /* Disable MSI -> HT mapping. */
1810 pci_ht_map_msi(dev, 0);
1811
1812 /* Disable MSI in the control register. */
1813 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1814 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1815 2);
1816 }
1817
1818 /*
1819 * Restore MSI registers during resume. If MSI is enabled then
1820 * restore the data and address registers in addition to the control
1821 * register.
1822 */
1823 static void
1824 pci_resume_msi(device_t dev)
1825 {
1826 struct pci_devinfo *dinfo = device_get_ivars(dev);
1827 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1828 uint64_t address;
1829 uint16_t data;
1830
1831 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1832 address = msi->msi_addr;
1833 data = msi->msi_data;
1834 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1835 address & 0xffffffff, 4);
1836 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1837 pci_write_config(dev, msi->msi_location +
1838 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1839 pci_write_config(dev, msi->msi_location +
1840 PCIR_MSI_DATA_64BIT, data, 2);
1841 } else
1842 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1843 data, 2);
1844 }
1845 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1846 2);
1847 }
1848
1849 static int
1850 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1851 {
1852 struct pci_devinfo *dinfo = device_get_ivars(dev);
1853 pcicfgregs *cfg = &dinfo->cfg;
1854 struct resource_list_entry *rle;
1855 struct msix_table_entry *mte;
1856 struct msix_vector *mv;
1857 uint64_t addr;
1858 uint32_t data;
1859 int error, i, j;
1860
1861 /*
1862 * Handle MSI first. We try to find this IRQ among our list
1863 * of MSI IRQs. If we find it, we request updated address and
1864 * data registers and apply the results.
1865 */
1866 if (cfg->msi.msi_alloc > 0) {
1867
1868 /* If we don't have any active handlers, nothing to do. */
1869 if (cfg->msi.msi_handlers == 0)
1870 return (0);
1871 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1872 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1873 i + 1);
1874 if (rle->start == irq) {
1875 error = PCIB_MAP_MSI(device_get_parent(bus),
1876 dev, irq, &addr, &data);
1877 if (error)
1878 return (error);
1879 pci_disable_msi(dev);
1880 dinfo->cfg.msi.msi_addr = addr;
1881 dinfo->cfg.msi.msi_data = data;
1882 pci_enable_msi(dev, addr, data);
1883 return (0);
1884 }
1885 }
1886 return (ENOENT);
1887 }
1888
1889 /*
1890 * For MSI-X, we check to see if we have this IRQ. If we do,
1891 * we request the updated mapping info. If that works, we go
1892 * through all the slots that use this IRQ and update them.
1893 */
1894 if (cfg->msix.msix_alloc > 0) {
1895 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1896 mv = &cfg->msix.msix_vectors[i];
1897 if (mv->mv_irq == irq) {
1898 error = PCIB_MAP_MSI(device_get_parent(bus),
1899 dev, irq, &addr, &data);
1900 if (error)
1901 return (error);
1902 mv->mv_address = addr;
1903 mv->mv_data = data;
1904 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1905 mte = &cfg->msix.msix_table[j];
1906 if (mte->mte_vector != i + 1)
1907 continue;
1908 if (mte->mte_handlers == 0)
1909 continue;
1910 pci_mask_msix(dev, j);
1911 pci_enable_msix(dev, j, addr, data);
1912 pci_unmask_msix(dev, j);
1913 }
1914 }
1915 }
1916 return (ENOENT);
1917 }
1918
1919 return (ENOENT);
1920 }
1921
1922 /*
1923 * Returns true if the specified device is blacklisted because MSI
1924 * doesn't work.
1925 */
1926 int
1927 pci_msi_device_blacklisted(device_t dev)
1928 {
1929
1930 if (!pci_honor_msi_blacklist)
1931 return (0);
1932
1933 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
1934 }
1935
1936 /*
1937 * Determine if MSI is blacklisted globally on this system. Currently,
1938 * we just check for blacklisted chipsets as represented by the
1939 * host-PCI bridge at device 0:0:0. In the future, it may become
1940 * necessary to check other system attributes, such as the kenv values
1941 * that give the motherboard manufacturer and model number.
1942 */
1943 static int
1944 pci_msi_blacklisted(void)
1945 {
1946 device_t dev;
1947
1948 if (!pci_honor_msi_blacklist)
1949 return (0);
1950
1951 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1952 if (!(pcie_chipset || pcix_chipset)) {
1953 if (vm_guest != VM_GUEST_NO) {
1954 /*
1955 * Whitelist older chipsets in virtual
1956 * machines known to support MSI.
1957 */
1958 dev = pci_find_bsf(0, 0, 0);
1959 if (dev != NULL)
1960 return (!pci_has_quirk(pci_get_devid(dev),
1961 PCI_QUIRK_ENABLE_MSI_VM));
1962 }
1963 return (1);
1964 }
1965
1966 dev = pci_find_bsf(0, 0, 0);
1967 if (dev != NULL)
1968 return (pci_msi_device_blacklisted(dev));
1969 return (0);
1970 }
1971
1972 /*
1973 * Returns true if the specified device is blacklisted because MSI-X
1974 * doesn't work. Note that this assumes that if MSI doesn't work,
1975 * MSI-X doesn't either.
1976 */
1977 int
1978 pci_msix_device_blacklisted(device_t dev)
1979 {
1980
1981 if (!pci_honor_msi_blacklist)
1982 return (0);
1983
1984 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
1985 return (1);
1986
1987 return (pci_msi_device_blacklisted(dev));
1988 }
1989
1990 /*
1991 * Determine if MSI-X is blacklisted globally on this system. If MSI
1992 * is blacklisted, assume that MSI-X is as well. Check for additional
1993 * chipsets where MSI works but MSI-X does not.
1994 */
1995 static int
1996 pci_msix_blacklisted(void)
1997 {
1998 device_t dev;
1999
2000 if (!pci_honor_msi_blacklist)
2001 return (0);
2002
2003 dev = pci_find_bsf(0, 0, 0);
2004 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2005 PCI_QUIRK_DISABLE_MSIX))
2006 return (1);
2007
2008 return (pci_msi_blacklisted());
2009 }
2010
2011 /*
2012 * Attempt to allocate *count MSI messages. The actual number allocated is
2013 * returned in *count. After this function returns, each message will be
2014 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2015 */
2016 int
2017 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2018 {
2019 struct pci_devinfo *dinfo = device_get_ivars(child);
2020 pcicfgregs *cfg = &dinfo->cfg;
2021 struct resource_list_entry *rle;
2022 int actual, error, i, irqs[32];
2023 uint16_t ctrl;
2024
2025 /* Don't let count == 0 get us into trouble. */
2026 if (*count == 0)
2027 return (EINVAL);
2028
2029 /* If rid 0 is allocated, then fail. */
2030 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2031 if (rle != NULL && rle->res != NULL)
2032 return (ENXIO);
2033
2034 /* Already have allocated messages? */
2035 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2036 return (ENXIO);
2037
2038 /* If MSI is blacklisted for this system, fail. */
2039 if (pci_msi_blacklisted())
2040 return (ENXIO);
2041
2042 /* MSI capability present? */
2043 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2044 return (ENODEV);
2045
2046 if (bootverbose)
2047 device_printf(child,
2048 "attempting to allocate %d MSI vectors (%d supported)\n",
2049 *count, cfg->msi.msi_msgnum);
2050
2051 /* Don't ask for more than the device supports. */
2052 actual = min(*count, cfg->msi.msi_msgnum);
2053
2054 /* Don't ask for more than 32 messages. */
2055 actual = min(actual, 32);
2056
2057 /* MSI requires power of 2 number of messages. */
2058 if (!powerof2(actual))
2059 return (EINVAL);
2060
2061 for (;;) {
2062 /* Try to allocate N messages. */
2063 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2064 actual, irqs);
2065 if (error == 0)
2066 break;
2067 if (actual == 1)
2068 return (error);
2069
2070 /* Try N / 2. */
2071 actual >>= 1;
2072 }
2073
2074 /*
2075 * We now have N actual messages mapped onto SYS_RES_IRQ
2076 * resources in the irqs[] array, so add new resources
2077 * starting at rid 1.
2078 */
2079 for (i = 0; i < actual; i++)
2080 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2081 irqs[i], irqs[i], 1);
2082
2083 if (bootverbose) {
2084 if (actual == 1)
2085 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2086 else {
2087 int run;
2088
2089 /*
2090 * Be fancy and try to print contiguous runs
2091 * of IRQ values as ranges. 'run' is true if
2092 * we are in a range.
2093 */
2094 device_printf(child, "using IRQs %d", irqs[0]);
2095 run = 0;
2096 for (i = 1; i < actual; i++) {
2097
2098 /* Still in a run? */
2099 if (irqs[i] == irqs[i - 1] + 1) {
2100 run = 1;
2101 continue;
2102 }
2103
2104 /* Finish previous range. */
2105 if (run) {
2106 printf("-%d", irqs[i - 1]);
2107 run = 0;
2108 }
2109
2110 /* Start new range. */
2111 printf(",%d", irqs[i]);
2112 }
2113
2114 /* Unfinished range? */
2115 if (run)
2116 printf("-%d", irqs[actual - 1]);
2117 printf(" for MSI\n");
2118 }
2119 }
2120
2121 /* Update control register with actual count. */
2122 ctrl = cfg->msi.msi_ctrl;
2123 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2124 ctrl |= (ffs(actual) - 1) << 4;
2125 cfg->msi.msi_ctrl = ctrl;
2126 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2127
2128 /* Update counts of alloc'd messages. */
2129 cfg->msi.msi_alloc = actual;
2130 cfg->msi.msi_handlers = 0;
2131 *count = actual;
2132 return (0);
2133 }
2134
2135 /* Release the MSI messages associated with this device. */
2136 int
2137 pci_release_msi_method(device_t dev, device_t child)
2138 {
2139 struct pci_devinfo *dinfo = device_get_ivars(child);
2140 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2141 struct resource_list_entry *rle;
2142 int error, i, irqs[32];
2143
2144 /* Try MSI-X first. */
2145 error = pci_release_msix(dev, child);
2146 if (error != ENODEV)
2147 return (error);
2148
2149 /* Do we have any messages to release? */
2150 if (msi->msi_alloc == 0)
2151 return (ENODEV);
2152 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2153
2154 /* Make sure none of the resources are allocated. */
2155 if (msi->msi_handlers > 0)
2156 return (EBUSY);
2157 for (i = 0; i < msi->msi_alloc; i++) {
2158 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2159 KASSERT(rle != NULL, ("missing MSI resource"));
2160 if (rle->res != NULL)
2161 return (EBUSY);
2162 irqs[i] = rle->start;
2163 }
2164
2165 /* Update control register with 0 count. */
2166 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2167 ("%s: MSI still enabled", __func__));
2168 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2169 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2170 msi->msi_ctrl, 2);
2171
2172 /* Release the messages. */
2173 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2174 for (i = 0; i < msi->msi_alloc; i++)
2175 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2176
2177 /* Update alloc count. */
2178 msi->msi_alloc = 0;
2179 msi->msi_addr = 0;
2180 msi->msi_data = 0;
2181 return (0);
2182 }
2183
2184 /*
2185 * Return the max supported MSI messages this device supports.
2186 * Basically, assuming the MD code can alloc messages, this function
2187 * should return the maximum value that pci_alloc_msi() can return.
2188 * Thus, it is subject to the tunables, etc.
2189 */
2190 int
2191 pci_msi_count_method(device_t dev, device_t child)
2192 {
2193 struct pci_devinfo *dinfo = device_get_ivars(child);
2194 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2195
2196 if (pci_do_msi && msi->msi_location != 0)
2197 return (msi->msi_msgnum);
2198 return (0);
2199 }
2200
2201 /* free pcicfgregs structure and all depending data structures */
2202
2203 int
2204 pci_freecfg(struct pci_devinfo *dinfo)
2205 {
2206 struct devlist *devlist_head;
2207 struct pci_map *pm, *next;
2208 int i;
2209
2210 devlist_head = &pci_devq;
2211
2212 if (dinfo->cfg.vpd.vpd_reg) {
2213 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2214 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2215 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2216 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2217 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2218 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2219 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2220 }
2221 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2222 free(pm, M_DEVBUF);
2223 }
2224 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2225 free(dinfo, M_DEVBUF);
2226
2227 /* increment the generation count */
2228 pci_generation++;
2229
2230 /* we're losing one device */
2231 pci_numdevs--;
2232 return (0);
2233 }
2234
2235 /*
2236 * PCI power manangement
2237 */
2238 int
2239 pci_set_powerstate_method(device_t dev, device_t child, int state)
2240 {
2241 struct pci_devinfo *dinfo = device_get_ivars(child);
2242 pcicfgregs *cfg = &dinfo->cfg;
2243 uint16_t status;
2244 int result, oldstate, highest, delay;
2245
2246 if (cfg->pp.pp_cap == 0)
2247 return (EOPNOTSUPP);
2248
2249 /*
2250 * Optimize a no state change request away. While it would be OK to
2251 * write to the hardware in theory, some devices have shown odd
2252 * behavior when going from D3 -> D3.
2253 */
2254 oldstate = pci_get_powerstate(child);
2255 if (oldstate == state)
2256 return (0);
2257
2258 /*
2259 * The PCI power management specification states that after a state
2260 * transition between PCI power states, system software must
2261 * guarantee a minimal delay before the function accesses the device.
2262 * Compute the worst case delay that we need to guarantee before we
2263 * access the device. Many devices will be responsive much more
2264 * quickly than this delay, but there are some that don't respond
2265 * instantly to state changes. Transitions to/from D3 state require
2266 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2267 * is done below with DELAY rather than a sleeper function because
2268 * this function can be called from contexts where we cannot sleep.
2269 */
2270 highest = (oldstate > state) ? oldstate : state;
2271 if (highest == PCI_POWERSTATE_D3)
2272 delay = 10000;
2273 else if (highest == PCI_POWERSTATE_D2)
2274 delay = 200;
2275 else
2276 delay = 0;
2277 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2278 & ~PCIM_PSTAT_DMASK;
2279 result = 0;
2280 switch (state) {
2281 case PCI_POWERSTATE_D0:
2282 status |= PCIM_PSTAT_D0;
2283 break;
2284 case PCI_POWERSTATE_D1:
2285 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2286 return (EOPNOTSUPP);
2287 status |= PCIM_PSTAT_D1;
2288 break;
2289 case PCI_POWERSTATE_D2:
2290 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2291 return (EOPNOTSUPP);
2292 status |= PCIM_PSTAT_D2;
2293 break;
2294 case PCI_POWERSTATE_D3:
2295 status |= PCIM_PSTAT_D3;
2296 break;
2297 default:
2298 return (EINVAL);
2299 }
2300
2301 if (bootverbose)
2302 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2303 state);
2304
2305 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2306 if (delay)
2307 DELAY(delay);
2308 return (0);
2309 }
2310
2311 int
2312 pci_get_powerstate_method(device_t dev, device_t child)
2313 {
2314 struct pci_devinfo *dinfo = device_get_ivars(child);
2315 pcicfgregs *cfg = &dinfo->cfg;
2316 uint16_t status;
2317 int result;
2318
2319 if (cfg->pp.pp_cap != 0) {
2320 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2321 switch (status & PCIM_PSTAT_DMASK) {
2322 case PCIM_PSTAT_D0:
2323 result = PCI_POWERSTATE_D0;
2324 break;
2325 case PCIM_PSTAT_D1:
2326 result = PCI_POWERSTATE_D1;
2327 break;
2328 case PCIM_PSTAT_D2:
2329 result = PCI_POWERSTATE_D2;
2330 break;
2331 case PCIM_PSTAT_D3:
2332 result = PCI_POWERSTATE_D3;
2333 break;
2334 default:
2335 result = PCI_POWERSTATE_UNKNOWN;
2336 break;
2337 }
2338 } else {
2339 /* No support, device is always at D0 */
2340 result = PCI_POWERSTATE_D0;
2341 }
2342 return (result);
2343 }
2344
2345 /*
2346 * Some convenience functions for PCI device drivers.
2347 */
2348
2349 static __inline void
2350 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2351 {
2352 uint16_t command;
2353
2354 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2355 command |= bit;
2356 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2357 }
2358
2359 static __inline void
2360 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2361 {
2362 uint16_t command;
2363
2364 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2365 command &= ~bit;
2366 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2367 }
2368
2369 int
2370 pci_enable_busmaster_method(device_t dev, device_t child)
2371 {
2372 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2373 return (0);
2374 }
2375
2376 int
2377 pci_disable_busmaster_method(device_t dev, device_t child)
2378 {
2379 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2380 return (0);
2381 }
2382
2383 int
2384 pci_enable_io_method(device_t dev, device_t child, int space)
2385 {
2386 uint16_t bit;
2387
2388 switch(space) {
2389 case SYS_RES_IOPORT:
2390 bit = PCIM_CMD_PORTEN;
2391 break;
2392 case SYS_RES_MEMORY:
2393 bit = PCIM_CMD_MEMEN;
2394 break;
2395 default:
2396 return (EINVAL);
2397 }
2398 pci_set_command_bit(dev, child, bit);
2399 return (0);
2400 }
2401
2402 int
2403 pci_disable_io_method(device_t dev, device_t child, int space)
2404 {
2405 uint16_t bit;
2406
2407 switch(space) {
2408 case SYS_RES_IOPORT:
2409 bit = PCIM_CMD_PORTEN;
2410 break;
2411 case SYS_RES_MEMORY:
2412 bit = PCIM_CMD_MEMEN;
2413 break;
2414 default:
2415 return (EINVAL);
2416 }
2417 pci_clear_command_bit(dev, child, bit);
2418 return (0);
2419 }
2420
2421 /*
2422 * New style pci driver. Parent device is either a pci-host-bridge or a
2423 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2424 */
2425
2426 void
2427 pci_print_verbose(struct pci_devinfo *dinfo)
2428 {
2429
2430 if (bootverbose) {
2431 pcicfgregs *cfg = &dinfo->cfg;
2432
2433 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2434 cfg->vendor, cfg->device, cfg->revid);
2435 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2436 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2437 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2438 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2439 cfg->mfdev);
2440 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2441 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2442 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2443 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2444 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2445 if (cfg->intpin > 0)
2446 printf("\tintpin=%c, irq=%d\n",
2447 cfg->intpin +'a' -1, cfg->intline);
2448 if (cfg->pp.pp_cap) {
2449 uint16_t status;
2450
2451 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2452 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2453 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2454 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2455 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2456 status & PCIM_PSTAT_DMASK);
2457 }
2458 if (cfg->msi.msi_location) {
2459 int ctrl;
2460
2461 ctrl = cfg->msi.msi_ctrl;
2462 printf("\tMSI supports %d message%s%s%s\n",
2463 cfg->msi.msi_msgnum,
2464 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2465 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2466 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2467 }
2468 if (cfg->msix.msix_location) {
2469 printf("\tMSI-X supports %d message%s ",
2470 cfg->msix.msix_msgnum,
2471 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2472 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2473 printf("in map 0x%x\n",
2474 cfg->msix.msix_table_bar);
2475 else
2476 printf("in maps 0x%x and 0x%x\n",
2477 cfg->msix.msix_table_bar,
2478 cfg->msix.msix_pba_bar);
2479 }
2480 }
2481 }
2482
2483 static int
2484 pci_porten(device_t dev)
2485 {
2486 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2487 }
2488
2489 static int
2490 pci_memen(device_t dev)
2491 {
2492 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2493 }
2494
2495 static void
2496 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2497 {
2498 struct pci_devinfo *dinfo;
2499 pci_addr_t map, testval;
2500 int ln2range;
2501 uint16_t cmd;
2502
2503 /*
2504 * The device ROM BAR is special. It is always a 32-bit
2505 * memory BAR. Bit 0 is special and should not be set when
2506 * sizing the BAR.
2507 */
2508 dinfo = device_get_ivars(dev);
2509 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2510 map = pci_read_config(dev, reg, 4);
2511 pci_write_config(dev, reg, 0xfffffffe, 4);
2512 testval = pci_read_config(dev, reg, 4);
2513 pci_write_config(dev, reg, map, 4);
2514 *mapp = map;
2515 *testvalp = testval;
2516 return;
2517 }
2518
2519 map = pci_read_config(dev, reg, 4);
2520 ln2range = pci_maprange(map);
2521 if (ln2range == 64)
2522 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2523
2524 /*
2525 * Disable decoding via the command register before
2526 * determining the BAR's length since we will be placing it in
2527 * a weird state.
2528 */
2529 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2530 pci_write_config(dev, PCIR_COMMAND,
2531 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2532
2533 /*
2534 * Determine the BAR's length by writing all 1's. The bottom
2535 * log_2(size) bits of the BAR will stick as 0 when we read
2536 * the value back.
2537 */
2538 pci_write_config(dev, reg, 0xffffffff, 4);
2539 testval = pci_read_config(dev, reg, 4);
2540 if (ln2range == 64) {
2541 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2542 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2543 }
2544
2545 /*
2546 * Restore the original value of the BAR. We may have reprogrammed
2547 * the BAR of the low-level console device and when booting verbose,
2548 * we need the console device addressable.
2549 */
2550 pci_write_config(dev, reg, map, 4);
2551 if (ln2range == 64)
2552 pci_write_config(dev, reg + 4, map >> 32, 4);
2553 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2554
2555 *mapp = map;
2556 *testvalp = testval;
2557 }
2558
2559 static void
2560 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2561 {
2562 struct pci_devinfo *dinfo;
2563 int ln2range;
2564
2565 /* The device ROM BAR is always a 32-bit memory BAR. */
2566 dinfo = device_get_ivars(dev);
2567 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2568 ln2range = 32;
2569 else
2570 ln2range = pci_maprange(pm->pm_value);
2571 pci_write_config(dev, pm->pm_reg, base, 4);
2572 if (ln2range == 64)
2573 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2574 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2575 if (ln2range == 64)
2576 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2577 pm->pm_reg + 4, 4) << 32;
2578 }
2579
2580 struct pci_map *
2581 pci_find_bar(device_t dev, int reg)
2582 {
2583 struct pci_devinfo *dinfo;
2584 struct pci_map *pm;
2585
2586 dinfo = device_get_ivars(dev);
2587 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2588 if (pm->pm_reg == reg)
2589 return (pm);
2590 }
2591 return (NULL);
2592 }
2593
2594 int
2595 pci_bar_enabled(device_t dev, struct pci_map *pm)
2596 {
2597 struct pci_devinfo *dinfo;
2598 uint16_t cmd;
2599
2600 dinfo = device_get_ivars(dev);
2601 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2602 !(pm->pm_value & PCIM_BIOS_ENABLE))
2603 return (0);
2604 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2605 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2606 return ((cmd & PCIM_CMD_MEMEN) != 0);
2607 else
2608 return ((cmd & PCIM_CMD_PORTEN) != 0);
2609 }
2610
2611 static struct pci_map *
2612 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2613 {
2614 struct pci_devinfo *dinfo;
2615 struct pci_map *pm, *prev;
2616
2617 dinfo = device_get_ivars(dev);
2618 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2619 pm->pm_reg = reg;
2620 pm->pm_value = value;
2621 pm->pm_size = size;
2622 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2623 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2624 reg));
2625 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2626 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2627 break;
2628 }
2629 if (prev != NULL)
2630 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2631 else
2632 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2633 return (pm);
2634 }
2635
2636 static void
2637 pci_restore_bars(device_t dev)
2638 {
2639 struct pci_devinfo *dinfo;
2640 struct pci_map *pm;
2641 int ln2range;
2642
2643 dinfo = device_get_ivars(dev);
2644 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2645 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2646 ln2range = 32;
2647 else
2648 ln2range = pci_maprange(pm->pm_value);
2649 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2650 if (ln2range == 64)
2651 pci_write_config(dev, pm->pm_reg + 4,
2652 pm->pm_value >> 32, 4);
2653 }
2654 }
2655
2656 /*
2657 * Add a resource based on a pci map register. Return 1 if the map
2658 * register is a 32bit map register or 2 if it is a 64bit register.
2659 */
2660 static int
2661 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2662 int force, int prefetch)
2663 {
2664 struct pci_map *pm;
2665 pci_addr_t base, map, testval;
2666 pci_addr_t start, end, count;
2667 int barlen, basezero, maprange, mapsize, type;
2668 uint16_t cmd;
2669 struct resource *res;
2670
2671 /*
2672 * The BAR may already exist if the device is a CardBus card
2673 * whose CIS is stored in this BAR.
2674 */
2675 pm = pci_find_bar(dev, reg);
2676 if (pm != NULL) {
2677 maprange = pci_maprange(pm->pm_value);
2678 barlen = maprange == 64 ? 2 : 1;
2679 return (barlen);
2680 }
2681
2682 pci_read_bar(dev, reg, &map, &testval);
2683 if (PCI_BAR_MEM(map)) {
2684 type = SYS_RES_MEMORY;
2685 if (map & PCIM_BAR_MEM_PREFETCH)
2686 prefetch = 1;
2687 } else
2688 type = SYS_RES_IOPORT;
2689 mapsize = pci_mapsize(testval);
2690 base = pci_mapbase(map);
2691 #ifdef __PCI_BAR_ZERO_VALID
2692 basezero = 0;
2693 #else
2694 basezero = base == 0;
2695 #endif
2696 maprange = pci_maprange(map);
2697 barlen = maprange == 64 ? 2 : 1;
2698
2699 /*
2700 * For I/O registers, if bottom bit is set, and the next bit up
2701 * isn't clear, we know we have a BAR that doesn't conform to the
2702 * spec, so ignore it. Also, sanity check the size of the data
2703 * areas to the type of memory involved. Memory must be at least
2704 * 16 bytes in size, while I/O ranges must be at least 4.
2705 */
2706 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2707 return (barlen);
2708 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2709 (type == SYS_RES_IOPORT && mapsize < 2))
2710 return (barlen);
2711
2712 /* Save a record of this BAR. */
2713 pm = pci_add_bar(dev, reg, map, mapsize);
2714 if (bootverbose) {
2715 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2716 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2717 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2718 printf(", port disabled\n");
2719 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2720 printf(", memory disabled\n");
2721 else
2722 printf(", enabled\n");
2723 }
2724
2725 /*
2726 * If base is 0, then we have problems if this architecture does
2727 * not allow that. It is best to ignore such entries for the
2728 * moment. These will be allocated later if the driver specifically
2729 * requests them. However, some removable busses look better when
2730 * all resources are allocated, so allow '' to be overriden.
2731 *
2732 * Similarly treat maps whose values is the same as the test value
2733 * read back. These maps have had all f's written to them by the
2734 * BIOS in an attempt to disable the resources.
2735 */
2736 if (!force && (basezero || map == testval))
2737 return (barlen);
2738 if ((u_long)base != base) {
2739 device_printf(bus,
2740 "pci%d:%d:%d:%d bar %#x too many address bits",
2741 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2742 pci_get_function(dev), reg);
2743 return (barlen);
2744 }
2745
2746 /*
2747 * This code theoretically does the right thing, but has
2748 * undesirable side effects in some cases where peripherals
2749 * respond oddly to having these bits enabled. Let the user
2750 * be able to turn them off (since pci_enable_io_modes is 1 by
2751 * default).
2752 */
2753 if (pci_enable_io_modes) {
2754 /* Turn on resources that have been left off by a lazy BIOS */
2755 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2756 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2757 cmd |= PCIM_CMD_PORTEN;
2758 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2759 }
2760 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2761 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2762 cmd |= PCIM_CMD_MEMEN;
2763 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2764 }
2765 } else {
2766 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2767 return (barlen);
2768 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2769 return (barlen);
2770 }
2771
2772 count = (pci_addr_t)1 << mapsize;
2773 if (basezero || base == pci_mapbase(testval)) {
2774 start = 0; /* Let the parent decide. */
2775 end = ~0ul;
2776 } else {
2777 start = base;
2778 end = base + count - 1;
2779 }
2780 resource_list_add(rl, type, reg, start, end, count);
2781
2782 /*
2783 * Try to allocate the resource for this BAR from our parent
2784 * so that this resource range is already reserved. The
2785 * driver for this device will later inherit this resource in
2786 * pci_alloc_resource().
2787 */
2788 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2789 prefetch ? RF_PREFETCHABLE : 0);
2790 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2791 /*
2792 * If the allocation fails, try to allocate a resource for
2793 * this BAR using any available range. The firmware felt
2794 * it was important enough to assign a resource, so don't
2795 * disable decoding if we can help it.
2796 */
2797 resource_list_delete(rl, type, reg);
2798 resource_list_add(rl, type, reg, 0, ~0ul, count);
2799 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2800 count, prefetch ? RF_PREFETCHABLE : 0);
2801 }
2802 if (res == NULL) {
2803 /*
2804 * If the allocation fails, delete the resource list entry
2805 * and disable decoding for this device.
2806 *
2807 * If the driver requests this resource in the future,
2808 * pci_reserve_map() will try to allocate a fresh
2809 * resource range.
2810 */
2811 resource_list_delete(rl, type, reg);
2812 pci_disable_io(dev, type);
2813 if (bootverbose)
2814 device_printf(bus,
2815 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2816 pci_get_domain(dev), pci_get_bus(dev),
2817 pci_get_slot(dev), pci_get_function(dev), reg);
2818 } else {
2819 start = rman_get_start(res);
2820 pci_write_bar(dev, pm, start);
2821 }
2822 return (barlen);
2823 }
2824
2825 /*
2826 * For ATA devices we need to decide early what addressing mode to use.
2827 * Legacy demands that the primary and secondary ATA ports sits on the
2828 * same addresses that old ISA hardware did. This dictates that we use
2829 * those addresses and ignore the BAR's if we cannot set PCI native
2830 * addressing mode.
2831 */
2832 static void
2833 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2834 uint32_t prefetchmask)
2835 {
2836 struct resource *r;
2837 int rid, type, progif;
2838 #if 0
2839 /* if this device supports PCI native addressing use it */
2840 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2841 if ((progif & 0x8a) == 0x8a) {
2842 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2843 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2844 printf("Trying ATA native PCI addressing mode\n");
2845 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2846 }
2847 }
2848 #endif
2849 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2850 type = SYS_RES_IOPORT;
2851 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2852 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2853 prefetchmask & (1 << 0));
2854 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2855 prefetchmask & (1 << 1));
2856 } else {
2857 rid = PCIR_BAR(0);
2858 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2859 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2860 0x1f7, 8, 0);
2861 rid = PCIR_BAR(1);
2862 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2863 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
2864 0x3f6, 1, 0);
2865 }
2866 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2867 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2868 prefetchmask & (1 << 2));
2869 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2870 prefetchmask & (1 << 3));
2871 } else {
2872 rid = PCIR_BAR(2);
2873 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2874 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
2875 0x177, 8, 0);
2876 rid = PCIR_BAR(3);
2877 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2878 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
2879 0x376, 1, 0);
2880 }
2881 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2882 prefetchmask & (1 << 4));
2883 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2884 prefetchmask & (1 << 5));
2885 }
2886
2887 static void
2888 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2889 {
2890 struct pci_devinfo *dinfo = device_get_ivars(dev);
2891 pcicfgregs *cfg = &dinfo->cfg;
2892 char tunable_name[64];
2893 int irq;
2894
2895 /* Has to have an intpin to have an interrupt. */
2896 if (cfg->intpin == 0)
2897 return;
2898
2899 /* Let the user override the IRQ with a tunable. */
2900 irq = PCI_INVALID_IRQ;
2901 snprintf(tunable_name, sizeof(tunable_name),
2902 "hw.pci%d.%d.%d.INT%c.irq",
2903 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2904 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2905 irq = PCI_INVALID_IRQ;
2906
2907 /*
2908 * If we didn't get an IRQ via the tunable, then we either use the
2909 * IRQ value in the intline register or we ask the bus to route an
2910 * interrupt for us. If force_route is true, then we only use the
2911 * value in the intline register if the bus was unable to assign an
2912 * IRQ.
2913 */
2914 if (!PCI_INTERRUPT_VALID(irq)) {
2915 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2916 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2917 if (!PCI_INTERRUPT_VALID(irq))
2918 irq = cfg->intline;
2919 }
2920
2921 /* If after all that we don't have an IRQ, just bail. */
2922 if (!PCI_INTERRUPT_VALID(irq))
2923 return;
2924
2925 /* Update the config register if it changed. */
2926 if (irq != cfg->intline) {
2927 cfg->intline = irq;
2928 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2929 }
2930
2931 /* Add this IRQ as rid 0 interrupt resource. */
2932 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2933 }
2934
2935 /* Perform early OHCI takeover from SMM. */
2936 static void
2937 ohci_early_takeover(device_t self)
2938 {
2939 struct resource *res;
2940 uint32_t ctl;
2941 int rid;
2942 int i;
2943
2944 rid = PCIR_BAR(0);
2945 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2946 if (res == NULL)
2947 return;
2948
2949 ctl = bus_read_4(res, OHCI_CONTROL);
2950 if (ctl & OHCI_IR) {
2951 if (bootverbose)
2952 printf("ohci early: "
2953 "SMM active, request owner change\n");
2954 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
2955 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
2956 DELAY(1000);
2957 ctl = bus_read_4(res, OHCI_CONTROL);
2958 }
2959 if (ctl & OHCI_IR) {
2960 if (bootverbose)
2961 printf("ohci early: "
2962 "SMM does not respond, resetting\n");
2963 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
2964 }
2965 /* Disable interrupts */
2966 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
2967 }
2968
2969 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2970 }
2971
2972 /* Perform early UHCI takeover from SMM. */
2973 static void
2974 uhci_early_takeover(device_t self)
2975 {
2976 struct resource *res;
2977 int rid;
2978
2979 /*
2980 * Set the PIRQD enable bit and switch off all the others. We don't
2981 * want legacy support to interfere with us XXX Does this also mean
2982 * that the BIOS won't touch the keyboard anymore if it is connected
2983 * to the ports of the root hub?
2984 */
2985 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
2986
2987 /* Disable interrupts */
2988 rid = PCI_UHCI_BASE_REG;
2989 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
2990 if (res != NULL) {
2991 bus_write_2(res, UHCI_INTR, 0);
2992 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
2993 }
2994 }
2995
2996 /* Perform early EHCI takeover from SMM. */
2997 static void
2998 ehci_early_takeover(device_t self)
2999 {
3000 struct resource *res;
3001 uint32_t cparams;
3002 uint32_t eec;
3003 uint8_t eecp;
3004 uint8_t bios_sem;
3005 uint8_t offs;
3006 int rid;
3007 int i;
3008
3009 rid = PCIR_BAR(0);
3010 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3011 if (res == NULL)
3012 return;
3013
3014 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3015
3016 /* Synchronise with the BIOS if it owns the controller. */
3017 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3018 eecp = EHCI_EECP_NEXT(eec)) {
3019 eec = pci_read_config(self, eecp, 4);
3020 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3021 continue;
3022 }
3023 bios_sem = pci_read_config(self, eecp +
3024 EHCI_LEGSUP_BIOS_SEM, 1);
3025 if (bios_sem == 0) {
3026 continue;
3027 }
3028 if (bootverbose)
3029 printf("ehci early: "
3030 "SMM active, request owner change\n");
3031
3032 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3033
3034 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3035 DELAY(1000);
3036 bios_sem = pci_read_config(self, eecp +
3037 EHCI_LEGSUP_BIOS_SEM, 1);
3038 }
3039
3040 if (bios_sem != 0) {
3041 if (bootverbose)
3042 printf("ehci early: "
3043 "SMM does not respond\n");
3044 }
3045 /* Disable interrupts */
3046 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3047 bus_write_4(res, offs + EHCI_USBINTR, 0);
3048 }
3049 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3050 }
3051
3052 /* Perform early XHCI takeover from SMM. */
3053 static void
3054 xhci_early_takeover(device_t self)
3055 {
3056 struct resource *res;
3057 uint32_t cparams;
3058 uint32_t eec;
3059 uint8_t eecp;
3060 uint8_t bios_sem;
3061 uint8_t offs;
3062 int rid;
3063 int i;
3064
3065 rid = PCIR_BAR(0);
3066 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3067 if (res == NULL)
3068 return;
3069
3070 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3071
3072 eec = -1;
3073
3074 /* Synchronise with the BIOS if it owns the controller. */
3075 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3076 eecp += XHCI_XECP_NEXT(eec) << 2) {
3077 eec = bus_read_4(res, eecp);
3078
3079 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3080 continue;
3081
3082 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3083 if (bios_sem == 0)
3084 continue;
3085
3086 if (bootverbose)
3087 printf("xhci early: "
3088 "SMM active, request owner change\n");
3089
3090 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3091
3092 /* wait a maximum of 5 second */
3093
3094 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3095 DELAY(1000);
3096 bios_sem = bus_read_1(res, eecp +
3097 XHCI_XECP_BIOS_SEM);
3098 }
3099
3100 if (bios_sem != 0) {
3101 if (bootverbose)
3102 printf("xhci early: "
3103 "SMM does not respond\n");
3104 }
3105
3106 /* Disable interrupts */
3107 offs = bus_read_1(res, XHCI_CAPLENGTH);
3108 bus_write_4(res, offs + XHCI_USBCMD, 0);
3109 bus_read_4(res, offs + XHCI_USBSTS);
3110 }
3111 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3112 }
3113
3114 void
3115 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3116 {
3117 struct pci_devinfo *dinfo;
3118 pcicfgregs *cfg;
3119 struct resource_list *rl;
3120 const struct pci_quirk *q;
3121 uint32_t devid;
3122 int i;
3123
3124 dinfo = device_get_ivars(dev);
3125 cfg = &dinfo->cfg;
3126 rl = &dinfo->resources;
3127 devid = (cfg->device << 16) | cfg->vendor;
3128
3129 /* ATA devices needs special map treatment */
3130 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3131 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3132 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3133 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3134 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3135 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3136 else
3137 for (i = 0; i < cfg->nummaps;) {
3138 /*
3139 * Skip quirked resources.
3140 */
3141 for (q = &pci_quirks[0]; q->devid != 0; q++)
3142 if (q->devid == devid &&
3143 q->type == PCI_QUIRK_UNMAP_REG &&
3144 q->arg1 == PCIR_BAR(i))
3145 break;
3146 if (q->devid != 0) {
3147 i++;
3148 continue;
3149 }
3150 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3151 prefetchmask & (1 << i));
3152 }
3153
3154 /*
3155 * Add additional, quirked resources.
3156 */
3157 for (q = &pci_quirks[0]; q->devid != 0; q++)
3158 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3159 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3160
3161 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3162 #ifdef __PCI_REROUTE_INTERRUPT
3163 /*
3164 * Try to re-route interrupts. Sometimes the BIOS or
3165 * firmware may leave bogus values in these registers.
3166 * If the re-route fails, then just stick with what we
3167 * have.
3168 */
3169 pci_assign_interrupt(bus, dev, 1);
3170 #else
3171 pci_assign_interrupt(bus, dev, 0);
3172 #endif
3173 }
3174
3175 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3176 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3177 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3178 xhci_early_takeover(dev);
3179 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3180 ehci_early_takeover(dev);
3181 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3182 ohci_early_takeover(dev);
3183 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3184 uhci_early_takeover(dev);
3185 }
3186 }
3187
3188 void
3189 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3190 {
3191 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3192 device_t pcib = device_get_parent(dev);
3193 struct pci_devinfo *dinfo;
3194 int maxslots;
3195 int s, f, pcifunchigh;
3196 uint8_t hdrtype;
3197
3198 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3199 ("dinfo_size too small"));
3200 maxslots = PCIB_MAXSLOTS(pcib);
3201 for (s = 0; s <= maxslots; s++) {
3202 pcifunchigh = 0;
3203 f = 0;
3204 DELAY(1);
3205 hdrtype = REG(PCIR_HDRTYPE, 1);
3206 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3207 continue;
3208 if (hdrtype & PCIM_MFDEV)
3209 pcifunchigh = PCI_FUNCMAX;
3210 for (f = 0; f <= pcifunchigh; f++) {
3211 dinfo = pci_read_device(pcib, domain, busno, s, f,
3212 dinfo_size);
3213 if (dinfo != NULL) {
3214 pci_add_child(dev, dinfo);
3215 }
3216 }
3217 }
3218 #undef REG
3219 }
3220
3221 void
3222 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3223 {
3224 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3225 device_set_ivars(dinfo->cfg.dev, dinfo);
3226 resource_list_init(&dinfo->resources);
3227 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3228 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3229 pci_print_verbose(dinfo);
3230 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3231 }
3232
3233 static int
3234 pci_probe(device_t dev)
3235 {
3236
3237 device_set_desc(dev, "PCI bus");
3238
3239 /* Allow other subclasses to override this driver. */
3240 return (BUS_PROBE_GENERIC);
3241 }
3242
3243 int
3244 pci_attach_common(device_t dev)
3245 {
3246 struct pci_softc *sc;
3247 int busno, domain;
3248 #ifdef PCI_DMA_BOUNDARY
3249 int error, tag_valid;
3250 #endif
3251
3252 sc = device_get_softc(dev);
3253 domain = pcib_get_domain(dev);
3254 busno = pcib_get_bus(dev);
3255 if (bootverbose)
3256 device_printf(dev, "domain=%d, physical bus=%d\n",
3257 domain, busno);
3258 #ifdef PCI_DMA_BOUNDARY
3259 tag_valid = 0;
3260 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3261 devclass_find("pci")) {
3262 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3263 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3264 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3265 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3266 if (error)
3267 device_printf(dev, "Failed to create DMA tag: %d\n",
3268 error);
3269 else
3270 tag_valid = 1;
3271 }
3272 if (!tag_valid)
3273 #endif
3274 sc->sc_dma_tag = bus_get_dma_tag(dev);
3275 return (0);
3276 }
3277
3278 static int
3279 pci_attach(device_t dev)
3280 {
3281 int busno, domain, error;
3282
3283 error = pci_attach_common(dev);
3284 if (error)
3285 return (error);
3286
3287 /*
3288 * Since there can be multiple independantly numbered PCI
3289 * busses on systems with multiple PCI domains, we can't use
3290 * the unit number to decide which bus we are probing. We ask
3291 * the parent pcib what our domain and bus numbers are.
3292 */
3293 domain = pcib_get_domain(dev);
3294 busno = pcib_get_bus(dev);
3295 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3296 return (bus_generic_attach(dev));
3297 }
3298
3299 static void
3300 pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3301 int state)
3302 {
3303 device_t child, pcib;
3304 struct pci_devinfo *dinfo;
3305 int dstate, i;
3306
3307 /*
3308 * Set the device to the given state. If the firmware suggests
3309 * a different power state, use it instead. If power management
3310 * is not present, the firmware is responsible for managing
3311 * device power. Skip children who aren't attached since they
3312 * are handled separately.
3313 */
3314 pcib = device_get_parent(dev);
3315 for (i = 0; i < numdevs; i++) {
3316 child = devlist[i];
3317 dinfo = device_get_ivars(child);
3318 dstate = state;
3319 if (device_is_attached(child) &&
3320 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3321 pci_set_powerstate(child, dstate);
3322 }
3323 }
3324
3325 int
3326 pci_suspend(device_t dev)
3327 {
3328 device_t child, *devlist;
3329 struct pci_devinfo *dinfo;
3330 int error, i, numdevs;
3331
3332 /*
3333 * Save the PCI configuration space for each child and set the
3334 * device in the appropriate power state for this sleep state.
3335 */
3336 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3337 return (error);
3338 for (i = 0; i < numdevs; i++) {
3339 child = devlist[i];
3340 dinfo = device_get_ivars(child);
3341 pci_cfg_save(child, dinfo, 0);
3342 }
3343
3344 /* Suspend devices before potentially powering them down. */
3345 error = bus_generic_suspend(dev);
3346 if (error) {
3347 free(devlist, M_TEMP);
3348 return (error);
3349 }
3350 if (pci_do_power_suspend)
3351 pci_set_power_children(dev, devlist, numdevs,
3352 PCI_POWERSTATE_D3);
3353 free(devlist, M_TEMP);
3354 return (0);
3355 }
3356
3357 int
3358 pci_resume(device_t dev)
3359 {
3360 device_t child, *devlist;
3361 struct pci_devinfo *dinfo;
3362 int error, i, numdevs;
3363
3364 /*
3365 * Set each child to D0 and restore its PCI configuration space.
3366 */
3367 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3368 return (error);
3369 if (pci_do_power_resume)
3370 pci_set_power_children(dev, devlist, numdevs,
3371 PCI_POWERSTATE_D0);
3372
3373 /* Now the device is powered up, restore its config space. */
3374 for (i = 0; i < numdevs; i++) {
3375 child = devlist[i];
3376 dinfo = device_get_ivars(child);
3377
3378 pci_cfg_restore(child, dinfo);
3379 if (!device_is_attached(child))
3380 pci_cfg_save(child, dinfo, 1);
3381 }
3382
3383 /*
3384 * Resume critical devices first, then everything else later.
3385 */
3386 for (i = 0; i < numdevs; i++) {
3387 child = devlist[i];
3388 switch (pci_get_class(child)) {
3389 case PCIC_DISPLAY:
3390 case PCIC_MEMORY:
3391 case PCIC_BRIDGE:
3392 case PCIC_BASEPERIPH:
3393 DEVICE_RESUME(child);
3394 break;
3395 }
3396 }
3397 for (i = 0; i < numdevs; i++) {
3398 child = devlist[i];
3399 switch (pci_get_class(child)) {
3400 case PCIC_DISPLAY:
3401 case PCIC_MEMORY:
3402 case PCIC_BRIDGE:
3403 case PCIC_BASEPERIPH:
3404 break;
3405 default:
3406 DEVICE_RESUME(child);
3407 }
3408 }
3409 free(devlist, M_TEMP);
3410 return (0);
3411 }
3412
3413 static void
3414 pci_load_vendor_data(void)
3415 {
3416 caddr_t data;
3417 void *ptr;
3418 size_t sz;
3419
3420 data = preload_search_by_type("pci_vendor_data");
3421 if (data != NULL) {
3422 ptr = preload_fetch_addr(data);
3423 sz = preload_fetch_size(data);
3424 if (ptr != NULL && sz != 0) {
3425 pci_vendordata = ptr;
3426 pci_vendordata_size = sz;
3427 /* terminate the database */
3428 pci_vendordata[pci_vendordata_size] = '\n';
3429 }
3430 }
3431 }
3432
3433 void
3434 pci_driver_added(device_t dev, driver_t *driver)
3435 {
3436 int numdevs;
3437 device_t *devlist;
3438 device_t child;
3439 struct pci_devinfo *dinfo;
3440 int i;
3441
3442 if (bootverbose)
3443 device_printf(dev, "driver added\n");
3444 DEVICE_IDENTIFY(driver, dev);
3445 if (device_get_children(dev, &devlist, &numdevs) != 0)
3446 return;
3447 for (i = 0; i < numdevs; i++) {
3448 child = devlist[i];
3449 if (device_get_state(child) != DS_NOTPRESENT)
3450 continue;
3451 dinfo = device_get_ivars(child);
3452 pci_print_verbose(dinfo);
3453 if (bootverbose)
3454 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3455 pci_cfg_restore(child, dinfo);
3456 if (device_probe_and_attach(child) != 0)
3457 pci_cfg_save(child, dinfo, 1);
3458 }
3459 free(devlist, M_TEMP);
3460 }
3461
3462 int
3463 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3464 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3465 {
3466 struct pci_devinfo *dinfo;
3467 struct msix_table_entry *mte;
3468 struct msix_vector *mv;
3469 uint64_t addr;
3470 uint32_t data;
3471 void *cookie;
3472 int error, rid;
3473
3474 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3475 arg, &cookie);
3476 if (error)
3477 return (error);
3478
3479 /* If this is not a direct child, just bail out. */
3480 if (device_get_parent(child) != dev) {
3481 *cookiep = cookie;
3482 return(0);
3483 }
3484
3485 rid = rman_get_rid(irq);
3486 if (rid == 0) {
3487 /* Make sure that INTx is enabled */
3488 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3489 } else {
3490 /*
3491 * Check to see if the interrupt is MSI or MSI-X.
3492 * Ask our parent to map the MSI and give
3493 * us the address and data register values.
3494 * If we fail for some reason, teardown the
3495 * interrupt handler.
3496 */
3497 dinfo = device_get_ivars(child);
3498 if (dinfo->cfg.msi.msi_alloc > 0) {
3499 if (dinfo->cfg.msi.msi_addr == 0) {
3500 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3501 ("MSI has handlers, but vectors not mapped"));
3502 error = PCIB_MAP_MSI(device_get_parent(dev),
3503 child, rman_get_start(irq), &addr, &data);
3504 if (error)
3505 goto bad;
3506 dinfo->cfg.msi.msi_addr = addr;
3507 dinfo->cfg.msi.msi_data = data;
3508 }
3509 if (dinfo->cfg.msi.msi_handlers == 0)
3510 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3511 dinfo->cfg.msi.msi_data);
3512 dinfo->cfg.msi.msi_handlers++;
3513 } else {
3514 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3515 ("No MSI or MSI-X interrupts allocated"));
3516 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3517 ("MSI-X index too high"));
3518 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3519 KASSERT(mte->mte_vector != 0, ("no message vector"));
3520 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3521 KASSERT(mv->mv_irq == rman_get_start(irq),
3522 ("IRQ mismatch"));
3523 if (mv->mv_address == 0) {
3524 KASSERT(mte->mte_handlers == 0,
3525 ("MSI-X table entry has handlers, but vector not mapped"));
3526 error = PCIB_MAP_MSI(device_get_parent(dev),
3527 child, rman_get_start(irq), &addr, &data);
3528 if (error)
3529 goto bad;
3530 mv->mv_address = addr;
3531 mv->mv_data = data;
3532 }
3533 if (mte->mte_handlers == 0) {
3534 pci_enable_msix(child, rid - 1, mv->mv_address,
3535 mv->mv_data);
3536 pci_unmask_msix(child, rid - 1);
3537 }
3538 mte->mte_handlers++;
3539 }
3540
3541 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3542 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3543 bad:
3544 if (error) {
3545 (void)bus_generic_teardown_intr(dev, child, irq,
3546 cookie);
3547 return (error);
3548 }
3549 }
3550 *cookiep = cookie;
3551 return (0);
3552 }
3553
3554 int
3555 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3556 void *cookie)
3557 {
3558 struct msix_table_entry *mte;
3559 struct resource_list_entry *rle;
3560 struct pci_devinfo *dinfo;
3561 int error, rid;
3562
3563 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3564 return (EINVAL);
3565
3566 /* If this isn't a direct child, just bail out */
3567 if (device_get_parent(child) != dev)
3568 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3569
3570 rid = rman_get_rid(irq);
3571 if (rid == 0) {
3572 /* Mask INTx */
3573 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3574 } else {
3575 /*
3576 * Check to see if the interrupt is MSI or MSI-X. If so,
3577 * decrement the appropriate handlers count and mask the
3578 * MSI-X message, or disable MSI messages if the count
3579 * drops to 0.
3580 */
3581 dinfo = device_get_ivars(child);
3582 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3583 if (rle->res != irq)
3584 return (EINVAL);
3585 if (dinfo->cfg.msi.msi_alloc > 0) {
3586 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3587 ("MSI-X index too high"));
3588 if (dinfo->cfg.msi.msi_handlers == 0)
3589 return (EINVAL);
3590 dinfo->cfg.msi.msi_handlers--;
3591 if (dinfo->cfg.msi.msi_handlers == 0)
3592 pci_disable_msi(child);
3593 } else {
3594 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3595 ("No MSI or MSI-X interrupts allocated"));
3596 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3597 ("MSI-X index too high"));
3598 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3599 if (mte->mte_handlers == 0)
3600 return (EINVAL);
3601 mte->mte_handlers--;
3602 if (mte->mte_handlers == 0)
3603 pci_mask_msix(child, rid - 1);
3604 }
3605 }
3606 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3607 if (rid > 0)
3608 KASSERT(error == 0,
3609 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3610 return (error);
3611 }
3612
3613 int
3614 pci_print_child(device_t dev, device_t child)
3615 {
3616 struct pci_devinfo *dinfo;
3617 struct resource_list *rl;
3618 int retval = 0;
3619
3620 dinfo = device_get_ivars(child);
3621 rl = &dinfo->resources;
3622
3623 retval += bus_print_child_header(dev, child);
3624
3625 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3626 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3627 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3628 if (device_get_flags(dev))
3629 retval += printf(" flags %#x", device_get_flags(dev));
3630
3631 retval += printf(" at device %d.%d", pci_get_slot(child),
3632 pci_get_function(child));
3633
3634 retval += bus_print_child_footer(dev, child);
3635
3636 return (retval);
3637 }
3638
3639 static const struct
3640 {
3641 int class;
3642 int subclass;
3643 const char *desc;
3644 } pci_nomatch_tab[] = {
3645 {PCIC_OLD, -1, "old"},
3646 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3647 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3648 {PCIC_STORAGE, -1, "mass storage"},
3649 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3650 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3651 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3652 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3653 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3654 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3655 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3656 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3657 {PCIC_STORAGE, PCIS_STORAGE_NVM, "NVM"},
3658 {PCIC_NETWORK, -1, "network"},
3659 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3660 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3661 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3662 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3663 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3664 {PCIC_DISPLAY, -1, "display"},
3665 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3666 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3667 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3668 {PCIC_MULTIMEDIA, -1, "multimedia"},
3669 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3670 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3671 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3672 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3673 {PCIC_MEMORY, -1, "memory"},
3674 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3675 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3676 {PCIC_BRIDGE, -1, "bridge"},
3677 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3678 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3679 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3680 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3681 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3682 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3683 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3684 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3685 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3686 {PCIC_SIMPLECOMM, -1, "simple comms"},
3687 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3688 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3689 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3690 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3691 {PCIC_BASEPERIPH, -1, "base peripheral"},
3692 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3693 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3694 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3695 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3696 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3697 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3698 {PCIC_INPUTDEV, -1, "input device"},
3699 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3700 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3701 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3702 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3703 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3704 {PCIC_DOCKING, -1, "docking station"},
3705 {PCIC_PROCESSOR, -1, "processor"},
3706 {PCIC_SERIALBUS, -1, "serial bus"},
3707 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3708 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3709 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3710 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3711 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3712 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3713 {PCIC_WIRELESS, -1, "wireless controller"},
3714 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3715 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3716 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3717 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3718 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3719 {PCIC_SATCOM, -1, "satellite communication"},
3720 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3721 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3722 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3723 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3724 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3725 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3726 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3727 {PCIC_DASP, -1, "dasp"},
3728 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3729 {0, 0, NULL}
3730 };
3731
3732 void
3733 pci_probe_nomatch(device_t dev, device_t child)
3734 {
3735 int i;
3736 const char *cp, *scp;
3737 char *device;
3738
3739 /*
3740 * Look for a listing for this device in a loaded device database.
3741 */
3742 if ((device = pci_describe_device(child)) != NULL) {
3743 device_printf(dev, "<%s>", device);
3744 free(device, M_DEVBUF);
3745 } else {
3746 /*
3747 * Scan the class/subclass descriptions for a general
3748 * description.
3749 */
3750 cp = "unknown";
3751 scp = NULL;
3752 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3753 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3754 if (pci_nomatch_tab[i].subclass == -1) {
3755 cp = pci_nomatch_tab[i].desc;
3756 } else if (pci_nomatch_tab[i].subclass ==
3757 pci_get_subclass(child)) {
3758 scp = pci_nomatch_tab[i].desc;
3759 }
3760 }
3761 }
3762 device_printf(dev, "<%s%s%s>",
3763 cp ? cp : "",
3764 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3765 scp ? scp : "");
3766 }
3767 printf(" at device %d.%d (no driver attached)\n",
3768 pci_get_slot(child), pci_get_function(child));
3769 pci_cfg_save(child, device_get_ivars(child), 1);
3770 }
3771
3772 /*
3773 * Parse the PCI device database, if loaded, and return a pointer to a
3774 * description of the device.
3775 *
3776 * The database is flat text formatted as follows:
3777 *
3778 * Any line not in a valid format is ignored.
3779 * Lines are terminated with newline '\n' characters.
3780 *
3781 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3782 * the vendor name.
3783 *
3784 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3785 * - devices cannot be listed without a corresponding VENDOR line.
3786 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3787 * another TAB, then the device name.
3788 */
3789
3790 /*
3791 * Assuming (ptr) points to the beginning of a line in the database,
3792 * return the vendor or device and description of the next entry.
3793 * The value of (vendor) or (device) inappropriate for the entry type
3794 * is set to -1. Returns nonzero at the end of the database.
3795 *
3796 * Note that this is slightly unrobust in the face of corrupt data;
3797 * we attempt to safeguard against this by spamming the end of the
3798 * database with a newline when we initialise.
3799 */
3800 static int
3801 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3802 {
3803 char *cp = *ptr;
3804 int left;
3805
3806 *device = -1;
3807 *vendor = -1;
3808 **desc = '\0';
3809 for (;;) {
3810 left = pci_vendordata_size - (cp - pci_vendordata);
3811 if (left <= 0) {
3812 *ptr = cp;
3813 return(1);
3814 }
3815
3816 /* vendor entry? */
3817 if (*cp != '\t' &&
3818 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3819 break;
3820 /* device entry? */
3821 if (*cp == '\t' &&
3822 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3823 break;
3824
3825 /* skip to next line */
3826 while (*cp != '\n' && left > 0) {
3827 cp++;
3828 left--;
3829 }
3830 if (*cp == '\n') {
3831 cp++;
3832 left--;
3833 }
3834 }
3835 /* skip to next line */
3836 while (*cp != '\n' && left > 0) {
3837 cp++;
3838 left--;
3839 }
3840 if (*cp == '\n' && left > 0)
3841 cp++;
3842 *ptr = cp;
3843 return(0);
3844 }
3845
3846 static char *
3847 pci_describe_device(device_t dev)
3848 {
3849 int vendor, device;
3850 char *desc, *vp, *dp, *line;
3851
3852 desc = vp = dp = NULL;
3853
3854 /*
3855 * If we have no vendor data, we can't do anything.
3856 */
3857 if (pci_vendordata == NULL)
3858 goto out;
3859
3860 /*
3861 * Scan the vendor data looking for this device
3862 */
3863 line = pci_vendordata;
3864 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3865 goto out;
3866 for (;;) {
3867 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3868 goto out;
3869 if (vendor == pci_get_vendor(dev))
3870 break;
3871 }
3872 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3873 goto out;
3874 for (;;) {
3875 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3876 *dp = 0;
3877 break;
3878 }
3879 if (vendor != -1) {
3880 *dp = 0;
3881 break;
3882 }
3883 if (device == pci_get_device(dev))
3884 break;
3885 }
3886 if (dp[0] == '\0')
3887 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3888 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3889 NULL)
3890 sprintf(desc, "%s, %s", vp, dp);
3891 out:
3892 if (vp != NULL)
3893 free(vp, M_DEVBUF);
3894 if (dp != NULL)
3895 free(dp, M_DEVBUF);
3896 return(desc);
3897 }
3898
3899 int
3900 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3901 {
3902 struct pci_devinfo *dinfo;
3903 pcicfgregs *cfg;
3904
3905 dinfo = device_get_ivars(child);
3906 cfg = &dinfo->cfg;
3907
3908 switch (which) {
3909 case PCI_IVAR_ETHADDR:
3910 /*
3911 * The generic accessor doesn't deal with failure, so
3912 * we set the return value, then return an error.
3913 */
3914 *((uint8_t **) result) = NULL;
3915 return (EINVAL);
3916 case PCI_IVAR_SUBVENDOR:
3917 *result = cfg->subvendor;
3918 break;
3919 case PCI_IVAR_SUBDEVICE:
3920 *result = cfg->subdevice;
3921 break;
3922 case PCI_IVAR_VENDOR:
3923 *result = cfg->vendor;
3924 break;
3925 case PCI_IVAR_DEVICE:
3926 *result = cfg->device;
3927 break;
3928 case PCI_IVAR_DEVID:
3929 *result = (cfg->device << 16) | cfg->vendor;
3930 break;
3931 case PCI_IVAR_CLASS:
3932 *result = cfg->baseclass;
3933 break;
3934 case PCI_IVAR_SUBCLASS:
3935 *result = cfg->subclass;
3936 break;
3937 case PCI_IVAR_PROGIF:
3938 *result = cfg->progif;
3939 break;
3940 case PCI_IVAR_REVID:
3941 *result = cfg->revid;
3942 break;
3943 case PCI_IVAR_INTPIN:
3944 *result = cfg->intpin;
3945 break;
3946 case PCI_IVAR_IRQ:
3947 *result = cfg->intline;
3948 break;
3949 case PCI_IVAR_DOMAIN:
3950 *result = cfg->domain;
3951 break;
3952 case PCI_IVAR_BUS:
3953 *result = cfg->bus;
3954 break;
3955 case PCI_IVAR_SLOT:
3956 *result = cfg->slot;
3957 break;
3958 case PCI_IVAR_FUNCTION:
3959 *result = cfg->func;
3960 break;
3961 case PCI_IVAR_CMDREG:
3962 *result = cfg->cmdreg;
3963 break;
3964 case PCI_IVAR_CACHELNSZ:
3965 *result = cfg->cachelnsz;
3966 break;
3967 case PCI_IVAR_MINGNT:
3968 *result = cfg->mingnt;
3969 break;
3970 case PCI_IVAR_MAXLAT:
3971 *result = cfg->maxlat;
3972 break;
3973 case PCI_IVAR_LATTIMER:
3974 *result = cfg->lattimer;
3975 break;
3976 default:
3977 return (ENOENT);
3978 }
3979 return (0);
3980 }
3981
3982 int
3983 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3984 {
3985 struct pci_devinfo *dinfo;
3986
3987 dinfo = device_get_ivars(child);
3988
3989 switch (which) {
3990 case PCI_IVAR_INTPIN:
3991 dinfo->cfg.intpin = value;
3992 return (0);
3993 case PCI_IVAR_ETHADDR:
3994 case PCI_IVAR_SUBVENDOR:
3995 case PCI_IVAR_SUBDEVICE:
3996 case PCI_IVAR_VENDOR:
3997 case PCI_IVAR_DEVICE:
3998 case PCI_IVAR_DEVID:
3999 case PCI_IVAR_CLASS:
4000 case PCI_IVAR_SUBCLASS:
4001 case PCI_IVAR_PROGIF:
4002 case PCI_IVAR_REVID:
4003 case PCI_IVAR_IRQ:
4004 case PCI_IVAR_DOMAIN:
4005 case PCI_IVAR_BUS:
4006 case PCI_IVAR_SLOT:
4007 case PCI_IVAR_FUNCTION:
4008 return (EINVAL); /* disallow for now */
4009
4010 default:
4011 return (ENOENT);
4012 }
4013 }
4014
4015 #include "opt_ddb.h"
4016 #ifdef DDB
4017 #include <ddb/ddb.h>
4018 #include <sys/cons.h>
4019
4020 /*
4021 * List resources based on pci map registers, used for within ddb
4022 */
4023
4024 DB_SHOW_COMMAND(pciregs, db_pci_dump)
4025 {
4026 struct pci_devinfo *dinfo;
4027 struct devlist *devlist_head;
4028 struct pci_conf *p;
4029 const char *name;
4030 int i, error, none_count;
4031
4032 none_count = 0;
4033 /* get the head of the device queue */
4034 devlist_head = &pci_devq;
4035
4036 /*
4037 * Go through the list of devices and print out devices
4038 */
4039 for (error = 0, i = 0,
4040 dinfo = STAILQ_FIRST(devlist_head);
4041 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4042 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4043
4044 /* Populate pd_name and pd_unit */
4045 name = NULL;
4046 if (dinfo->cfg.dev)
4047 name = device_get_name(dinfo->cfg.dev);
4048
4049 p = &dinfo->conf;
4050 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4051 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4052 (name && *name) ? name : "none",
4053 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4054 none_count++,
4055 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4056 p->pc_sel.pc_func, (p->pc_class << 16) |
4057 (p->pc_subclass << 8) | p->pc_progif,
4058 (p->pc_subdevice << 16) | p->pc_subvendor,
4059 (p->pc_device << 16) | p->pc_vendor,
4060 p->pc_revid, p->pc_hdr);
4061 }
4062 }
4063 #endif /* DDB */
4064
4065 static struct resource *
4066 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4067 u_long start, u_long end, u_long count, u_int flags)
4068 {
4069 struct pci_devinfo *dinfo = device_get_ivars(child);
4070 struct resource_list *rl = &dinfo->resources;
4071 struct resource_list_entry *rle;
4072 struct resource *res;
4073 struct pci_map *pm;
4074 pci_addr_t map, testval;
4075 int mapsize;
4076
4077 res = NULL;
4078 pm = pci_find_bar(child, *rid);
4079 if (pm != NULL) {
4080 /* This is a BAR that we failed to allocate earlier. */
4081 mapsize = pm->pm_size;
4082 map = pm->pm_value;
4083 } else {
4084 /*
4085 * Weed out the bogons, and figure out how large the
4086 * BAR/map is. BARs that read back 0 here are bogus
4087 * and unimplemented. Note: atapci in legacy mode are
4088 * special and handled elsewhere in the code. If you
4089 * have a atapci device in legacy mode and it fails
4090 * here, that other code is broken.
4091 */
4092 pci_read_bar(child, *rid, &map, &testval);
4093
4094 /*
4095 * Determine the size of the BAR and ignore BARs with a size
4096 * of 0. Device ROM BARs use a different mask value.
4097 */
4098 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4099 mapsize = pci_romsize(testval);
4100 else
4101 mapsize = pci_mapsize(testval);
4102 if (mapsize == 0)
4103 goto out;
4104 pm = pci_add_bar(child, *rid, map, mapsize);
4105 }
4106
4107 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4108 if (type != SYS_RES_MEMORY) {
4109 if (bootverbose)
4110 device_printf(dev,
4111 "child %s requested type %d for rid %#x,"
4112 " but the BAR says it is an memio\n",
4113 device_get_nameunit(child), type, *rid);
4114 goto out;
4115 }
4116 } else {
4117 if (type != SYS_RES_IOPORT) {
4118 if (bootverbose)
4119 device_printf(dev,
4120 "child %s requested type %d for rid %#x,"
4121 " but the BAR says it is an ioport\n",
4122 device_get_nameunit(child), type, *rid);
4123 goto out;
4124 }
4125 }
4126
4127 /*
4128 * For real BARs, we need to override the size that
4129 * the driver requests, because that's what the BAR
4130 * actually uses and we would otherwise have a
4131 * situation where we might allocate the excess to
4132 * another driver, which won't work.
4133 */
4134 count = (pci_addr_t)1 << mapsize;
4135 if (RF_ALIGNMENT(flags) < mapsize)
4136 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4137 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4138 flags |= RF_PREFETCHABLE;
4139
4140 /*
4141 * Allocate enough resource, and then write back the
4142 * appropriate BAR for that resource.
4143 */
4144 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
4145 start, end, count, flags & ~RF_ACTIVE);
4146 if (res == NULL) {
4147 device_printf(child,
4148 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4149 count, *rid, type, start, end);
4150 goto out;
4151 }
4152 resource_list_add(rl, type, *rid, start, end, count);
4153 rle = resource_list_find(rl, type, *rid);
4154 if (rle == NULL)
4155 panic("pci_reserve_map: unexpectedly can't find resource.");
4156 rle->res = res;
4157 rle->start = rman_get_start(res);
4158 rle->end = rman_get_end(res);
4159 rle->count = count;
4160 rle->flags = RLE_RESERVED;
4161 if (bootverbose)
4162 device_printf(child,
4163 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4164 count, *rid, type, rman_get_start(res));
4165 map = rman_get_start(res);
4166 pci_write_bar(child, pm, map);
4167 out:
4168 return (res);
4169 }
4170
4171 struct resource *
4172 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4173 u_long start, u_long end, u_long count, u_int flags)
4174 {
4175 struct pci_devinfo *dinfo = device_get_ivars(child);
4176 struct resource_list *rl = &dinfo->resources;
4177 struct resource_list_entry *rle;
4178 struct resource *res;
4179 pcicfgregs *cfg = &dinfo->cfg;
4180
4181 if (device_get_parent(child) != dev)
4182 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4183 type, rid, start, end, count, flags));
4184
4185 /*
4186 * Perform lazy resource allocation
4187 */
4188 switch (type) {
4189 case SYS_RES_IRQ:
4190 /*
4191 * Can't alloc legacy interrupt once MSI messages have
4192 * been allocated.
4193 */
4194 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4195 cfg->msix.msix_alloc > 0))
4196 return (NULL);
4197
4198 /*
4199 * If the child device doesn't have an interrupt
4200 * routed and is deserving of an interrupt, try to
4201 * assign it one.
4202 */
4203 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4204 (cfg->intpin != 0))
4205 pci_assign_interrupt(dev, child, 0);
4206 break;
4207 case SYS_RES_IOPORT:
4208 case SYS_RES_MEMORY:
4209 #ifdef NEW_PCIB
4210 /*
4211 * PCI-PCI bridge I/O window resources are not BARs.
4212 * For those allocations just pass the request up the
4213 * tree.
4214 */
4215 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4216 switch (*rid) {
4217 case PCIR_IOBASEL_1:
4218 case PCIR_MEMBASE_1:
4219 case PCIR_PMBASEL_1:
4220 /*
4221 * XXX: Should we bother creating a resource
4222 * list entry?
4223 */
4224 return (bus_generic_alloc_resource(dev, child,
4225 type, rid, start, end, count, flags));
4226 }
4227 }
4228 #endif
4229 /* Reserve resources for this BAR if needed. */
4230 rle = resource_list_find(rl, type, *rid);
4231 if (rle == NULL) {
4232 res = pci_reserve_map(dev, child, type, rid, start, end,
4233 count, flags);
4234 if (res == NULL)
4235 return (NULL);
4236 }
4237 }
4238 return (resource_list_alloc(rl, dev, child, type, rid,
4239 start, end, count, flags));
4240 }
4241
4242 int
4243 pci_activate_resource(device_t dev, device_t child, int type, int rid,
4244 struct resource *r)
4245 {
4246 struct pci_devinfo *dinfo;
4247 int error;
4248
4249 error = bus_generic_activate_resource(dev, child, type, rid, r);
4250 if (error)
4251 return (error);
4252
4253 /* Enable decoding in the command register when activating BARs. */
4254 if (device_get_parent(child) == dev) {
4255 /* Device ROMs need their decoding explicitly enabled. */
4256 dinfo = device_get_ivars(child);
4257 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4258 pci_write_bar(child, pci_find_bar(child, rid),
4259 rman_get_start(r) | PCIM_BIOS_ENABLE);
4260 switch (type) {
4261 case SYS_RES_IOPORT:
4262 case SYS_RES_MEMORY:
4263 error = PCI_ENABLE_IO(dev, child, type);
4264 break;
4265 }
4266 }
4267 return (error);
4268 }
4269
4270 int
4271 pci_deactivate_resource(device_t dev, device_t child, int type,
4272 int rid, struct resource *r)
4273 {
4274 struct pci_devinfo *dinfo;
4275 int error;
4276
4277 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4278 if (error)
4279 return (error);
4280
4281 /* Disable decoding for device ROMs. */
4282 if (device_get_parent(child) == dev) {
4283 dinfo = device_get_ivars(child);
4284 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4285 pci_write_bar(child, pci_find_bar(child, rid),
4286 rman_get_start(r));
4287 }
4288 return (0);
4289 }
4290
4291 void
4292 pci_delete_child(device_t dev, device_t child)
4293 {
4294 struct resource_list_entry *rle;
4295 struct resource_list *rl;
4296 struct pci_devinfo *dinfo;
4297
4298 dinfo = device_get_ivars(child);
4299 rl = &dinfo->resources;
4300
4301 if (device_is_attached(child))
4302 device_detach(child);
4303
4304 /* Turn off access to resources we're about to free */
4305 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4306 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4307
4308 /* Free all allocated resources */
4309 STAILQ_FOREACH(rle, rl, link) {
4310 if (rle->res) {
4311 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4312 resource_list_busy(rl, rle->type, rle->rid)) {
4313 pci_printf(&dinfo->cfg,
4314 "Resource still owned, oops. "
4315 "(type=%d, rid=%d, addr=%lx)\n",
4316 rle->type, rle->rid,
4317 rman_get_start(rle->res));
4318 bus_release_resource(child, rle->type, rle->rid,
4319 rle->res);
4320 }
4321 resource_list_unreserve(rl, dev, child, rle->type,
4322 rle->rid);
4323 }
4324 }
4325 resource_list_free(rl);
4326
4327 device_delete_child(dev, child);
4328 pci_freecfg(dinfo);
4329 }
4330
4331 void
4332 pci_delete_resource(device_t dev, device_t child, int type, int rid)
4333 {
4334 struct pci_devinfo *dinfo;
4335 struct resource_list *rl;
4336 struct resource_list_entry *rle;
4337
4338 if (device_get_parent(child) != dev)
4339 return;
4340
4341 dinfo = device_get_ivars(child);
4342 rl = &dinfo->resources;
4343 rle = resource_list_find(rl, type, rid);
4344 if (rle == NULL)
4345 return;
4346
4347 if (rle->res) {
4348 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4349 resource_list_busy(rl, type, rid)) {
4350 device_printf(dev, "delete_resource: "
4351 "Resource still owned by child, oops. "
4352 "(type=%d, rid=%d, addr=%lx)\n",
4353 type, rid, rman_get_start(rle->res));
4354 return;
4355 }
4356 resource_list_unreserve(rl, dev, child, type, rid);
4357 }
4358 resource_list_delete(rl, type, rid);
4359 }
4360
4361 struct resource_list *
4362 pci_get_resource_list (device_t dev, device_t child)
4363 {
4364 struct pci_devinfo *dinfo = device_get_ivars(child);
4365
4366 return (&dinfo->resources);
4367 }
4368
4369 bus_dma_tag_t
4370 pci_get_dma_tag(device_t bus, device_t dev)
4371 {
4372 struct pci_softc *sc = device_get_softc(bus);
4373
4374 return (sc->sc_dma_tag);
4375 }
4376
4377 uint32_t
4378 pci_read_config_method(device_t dev, device_t child, int reg, int width)
4379 {
4380 struct pci_devinfo *dinfo = device_get_ivars(child);
4381 pcicfgregs *cfg = &dinfo->cfg;
4382
4383 return (PCIB_READ_CONFIG(device_get_parent(dev),
4384 cfg->bus, cfg->slot, cfg->func, reg, width));
4385 }
4386
4387 void
4388 pci_write_config_method(device_t dev, device_t child, int reg,
4389 uint32_t val, int width)
4390 {
4391 struct pci_devinfo *dinfo = device_get_ivars(child);
4392 pcicfgregs *cfg = &dinfo->cfg;
4393
4394 PCIB_WRITE_CONFIG(device_get_parent(dev),
4395 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4396 }
4397
4398 int
4399 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4400 size_t buflen)
4401 {
4402
4403 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4404 pci_get_function(child));
4405 return (0);
4406 }
4407
4408 int
4409 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4410 size_t buflen)
4411 {
4412 struct pci_devinfo *dinfo;
4413 pcicfgregs *cfg;
4414
4415 dinfo = device_get_ivars(child);
4416 cfg = &dinfo->cfg;
4417 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4418 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4419 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4420 cfg->progif);
4421 return (0);
4422 }
4423
4424 int
4425 pci_assign_interrupt_method(device_t dev, device_t child)
4426 {
4427 struct pci_devinfo *dinfo = device_get_ivars(child);
4428 pcicfgregs *cfg = &dinfo->cfg;
4429
4430 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4431 cfg->intpin));
4432 }
4433
4434 static int
4435 pci_modevent(module_t mod, int what, void *arg)
4436 {
4437 static struct cdev *pci_cdev;
4438
4439 switch (what) {
4440 case MOD_LOAD:
4441 STAILQ_INIT(&pci_devq);
4442 pci_generation = 0;
4443 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4444 "pci");
4445 pci_load_vendor_data();
4446 break;
4447
4448 case MOD_UNLOAD:
4449 destroy_dev(pci_cdev);
4450 break;
4451 }
4452
4453 return (0);
4454 }
4455
4456 void
4457 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4458 {
4459
4460 /*
4461 * Only do header type 0 devices. Type 1 devices are bridges,
4462 * which we know need special treatment. Type 2 devices are
4463 * cardbus bridges which also require special treatment.
4464 * Other types are unknown, and we err on the side of safety
4465 * by ignoring them.
4466 */
4467 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4468 return;
4469
4470 /*
4471 * Restore the device to full power mode. We must do this
4472 * before we restore the registers because moving from D3 to
4473 * D0 will cause the chip's BARs and some other registers to
4474 * be reset to some unknown power on reset values. Cut down
4475 * the noise on boot by doing nothing if we are already in
4476 * state D0.
4477 */
4478 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4479 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4480 pci_restore_bars(dev);
4481 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4482 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4483 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4484 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4485 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4486 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4487 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4488 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4489 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4490
4491 /* Restore MSI and MSI-X configurations if they are present. */
4492 if (dinfo->cfg.msi.msi_location != 0)
4493 pci_resume_msi(dev);
4494 if (dinfo->cfg.msix.msix_location != 0)
4495 pci_resume_msix(dev);
4496 }
4497
4498 void
4499 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4500 {
4501 uint32_t cls;
4502 int ps;
4503
4504 /*
4505 * Only do header type 0 devices. Type 1 devices are bridges, which
4506 * we know need special treatment. Type 2 devices are cardbus bridges
4507 * which also require special treatment. Other types are unknown, and
4508 * we err on the side of safety by ignoring them. Powering down
4509 * bridges should not be undertaken lightly.
4510 */
4511 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4512 return;
4513
4514 /*
4515 * Some drivers apparently write to these registers w/o updating our
4516 * cached copy. No harm happens if we update the copy, so do so here
4517 * so we can restore them. The COMMAND register is modified by the
4518 * bus w/o updating the cache. This should represent the normally
4519 * writable portion of the 'defined' part of type 0 headers. In
4520 * theory we also need to save/restore the PCI capability structures
4521 * we know about, but apart from power we don't know any that are
4522 * writable.
4523 */
4524 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4525 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4526 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4527 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4528 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4529 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4530 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4531 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4532 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4533 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4534 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4535 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4536 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4537 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4538 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4539
4540 /*
4541 * don't set the state for display devices, base peripherals and
4542 * memory devices since bad things happen when they are powered down.
4543 * We should (a) have drivers that can easily detach and (b) use
4544 * generic drivers for these devices so that some device actually
4545 * attaches. We need to make sure that when we implement (a) we don't
4546 * power the device down on a reattach.
4547 */
4548 cls = pci_get_class(dev);
4549 if (!setstate)
4550 return;
4551 switch (pci_do_power_nodriver)
4552 {
4553 case 0: /* NO powerdown at all */
4554 return;
4555 case 1: /* Conservative about what to power down */
4556 if (cls == PCIC_STORAGE)
4557 return;
4558 /*FALLTHROUGH*/
4559 case 2: /* Agressive about what to power down */
4560 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4561 cls == PCIC_BASEPERIPH)
4562 return;
4563 /*FALLTHROUGH*/
4564 case 3: /* Power down everything */
4565 break;
4566 }
4567 /*
4568 * PCI spec says we can only go into D3 state from D0 state.
4569 * Transition from D[12] into D0 before going to D3 state.
4570 */
4571 ps = pci_get_powerstate(dev);
4572 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4573 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4574 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4575 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4576 }
4577
4578 /* Wrapper APIs suitable for device driver use. */
4579 void
4580 pci_save_state(device_t dev)
4581 {
4582 struct pci_devinfo *dinfo;
4583
4584 dinfo = device_get_ivars(dev);
4585 pci_cfg_save(dev, dinfo, 0);
4586 }
4587
4588 void
4589 pci_restore_state(device_t dev)
4590 {
4591 struct pci_devinfo *dinfo;
4592
4593 dinfo = device_get_ivars(dev);
4594 pci_cfg_restore(dev, dinfo);
4595 }
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