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sys/dev/pci/pci.c
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1 /* $NetBSD: pci.c,v 1.165 2022/08/24 11:19:25 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.165 2022/08/24 11:19:25 riastradh Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <dev/pci/pci_calls.h> 57 58 #include <net/if.h> 59 60 #include "locators.h" 61 62 static void pci_child_register(device_t); 63 64 #ifdef PCI_CONFIG_DUMP 65 int pci_config_dump = 1; 66 #else 67 int pci_config_dump = 0; 68 #endif 69 70 int pciprint(void *, const char *); 71 72 #ifdef PCI_MACHDEP_ENUMERATE_BUS 73 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 74 #endif 75 76 /* 77 * Important note about PCI-ISA bridges: 78 * 79 * Callbacks are used to configure these devices so that ISA/EISA bridges 80 * can attach their child busses after PCI configuration is done. 81 * 82 * This works because: 83 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 84 * (2) any ISA/EISA bridges must be attached to primary PCI 85 * busses (i.e. bus zero). 86 * 87 * That boils down to: there can only be one of these outstanding 88 * at a time, it is cleared when configuring PCI bus 0 before any 89 * subdevices have been found, and it is run after all subdevices 90 * of PCI bus 0 have been found. 91 * 92 * This is needed because there are some (legacy) PCI devices which 93 * can show up as ISA/EISA devices as well (the prime example of which 94 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 95 * and the bridge is seen before the video board is, the board can show 96 * up as an ISA device, and that can (bogusly) complicate the PCI device's 97 * attach code, or make the PCI device not be properly attached at all. 98 * 99 * We use the generic config_defer() facility to achieve this. 100 */ 101 102 int 103 pcirescan(device_t self, const char *ifattr, const int *locators) 104 { 105 struct pci_softc *sc = device_private(self); 106 107 KASSERT(ifattr && !strcmp(ifattr, "pci")); 108 KASSERT(locators); 109 110 pci_enumerate_bus(sc, locators, NULL, NULL); 111 112 return 0; 113 } 114 115 int 116 pcimatch(device_t parent, cfdata_t cf, void *aux) 117 { 118 struct pcibus_attach_args *pba = aux; 119 120 /* Check the locators */ 121 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 122 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 123 return 0; 124 125 /* sanity */ 126 if (pba->pba_bus < 0 || pba->pba_bus > 255) 127 return 0; 128 129 /* 130 * XXX check other (hardware?) indicators 131 */ 132 133 return 1; 134 } 135 136 void 137 pciattach(device_t parent, device_t self, void *aux) 138 { 139 struct pcibus_attach_args *pba = aux; 140 struct pci_softc *sc = device_private(self); 141 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 142 const char *sep = ""; 143 static const int wildcard[PCICF_NLOCS] = { 144 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 145 }; 146 147 sc->sc_dev = self; 148 149 pci_attach_hook(parent, self, pba); 150 151 aprint_naive("\n"); 152 aprint_normal("\n"); 153 154 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 155 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 156 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 157 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 158 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 159 160 if (io_enabled == 0 && mem_enabled == 0) { 161 aprint_error_dev(self, "no spaces enabled!\n"); 162 goto fail; 163 } 164 165 #define PRINT(str) \ 166 do { \ 167 aprint_verbose("%s%s", sep, str); \ 168 sep = ", "; \ 169 } while (/*CONSTCOND*/0) 170 171 aprint_verbose_dev(self, ""); 172 173 if (io_enabled) 174 PRINT("i/o space"); 175 if (mem_enabled) 176 PRINT("memory space"); 177 aprint_verbose(" enabled"); 178 179 if (mrl_enabled || mrm_enabled || mwi_enabled) { 180 if (mrl_enabled) 181 PRINT("rd/line"); 182 if (mrm_enabled) 183 PRINT("rd/mult"); 184 if (mwi_enabled) 185 PRINT("wr/inv"); 186 aprint_verbose(" ok"); 187 } 188 189 aprint_verbose("\n"); 190 191 #undef PRINT 192 193 sc->sc_iot = pba->pba_iot; 194 sc->sc_memt = pba->pba_memt; 195 sc->sc_dmat = pba->pba_dmat; 196 sc->sc_dmat64 = pba->pba_dmat64; 197 sc->sc_pc = pba->pba_pc; 198 sc->sc_bus = pba->pba_bus; 199 sc->sc_bridgetag = pba->pba_bridgetag; 200 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 201 sc->sc_intrswiz = pba->pba_intrswiz; 202 sc->sc_intrtag = pba->pba_intrtag; 203 sc->sc_flags = pba->pba_flags; 204 205 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 206 207 pcirescan(sc->sc_dev, "pci", wildcard); 208 209 fail: 210 if (!pmf_device_register(self, NULL, NULL)) 211 aprint_error_dev(self, "couldn't establish power handler\n"); 212 } 213 214 int 215 pcidetach(device_t self, int flags) 216 { 217 int rc; 218 219 if ((rc = config_detach_children(self, flags)) != 0) 220 return rc; 221 pmf_device_deregister(self); 222 return 0; 223 } 224 225 int 226 pciprint(void *aux, const char *pnp) 227 { 228 struct pci_attach_args *pa = aux; 229 char devinfo[256]; 230 const struct pci_quirkdata *qd; 231 232 if (pnp) { 233 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 234 aprint_normal("%s at %s", devinfo, pnp); 235 } 236 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 237 if (pci_config_dump) { 238 printf(": "); 239 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 240 if (!pnp) 241 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 242 printf("%s at %s", devinfo, pnp ? pnp : "?"); 243 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 244 #ifdef __i386__ 245 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 246 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #else 249 printf("intrswiz %#lx, intrpin %#lx", 250 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 251 #endif 252 printf(", i/o %s, mem %s,", 253 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 254 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 255 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 256 PCI_PRODUCT(pa->pa_id)); 257 if (qd == NULL) { 258 printf(" no quirks"); 259 } else { 260 snprintb(devinfo, sizeof (devinfo), 261 "\002\001multifn\002singlefn\003skipfunc0" 262 "\004skipfunc1\005skipfunc2\006skipfunc3" 263 "\007skipfunc4\010skipfunc5\011skipfunc6" 264 "\012skipfunc7", qd->quirks); 265 printf(" quirks %s", devinfo); 266 } 267 printf(")"); 268 } 269 return UNCONF; 270 } 271 272 static devhandle_t 273 pci_bus_get_child_devhandle(struct pci_softc *sc, pcitag_t tag) 274 { 275 struct pci_bus_get_child_devhandle_args args = { 276 .pc = sc->sc_pc, 277 .tag = tag, 278 }; 279 280 if (device_call(sc->sc_dev, PCI_BUS_GET_CHILD_DEVHANDLE(&args)) != 0) { 281 /* 282 * The call is either not supported or the requested 283 * device was not found in the platform device tree. 284 * Return an invalid handle. 285 */ 286 return devhandle_invalid(); 287 } 288 289 return args.devhandle; 290 } 291 292 int 293 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 294 int (*match)(const struct pci_attach_args *), 295 struct pci_attach_args *pap) 296 { 297 pci_chipset_tag_t pc = sc->sc_pc; 298 struct pci_attach_args pa; 299 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 300 #ifdef __HAVE_PCI_MSI_MSIX 301 pcireg_t cap; 302 int off; 303 #endif 304 int ret, pin, bus, device, function, i, width; 305 int locs[PCICF_NLOCS]; 306 307 pci_decompose_tag(pc, tag, &bus, &device, &function); 308 309 /* a driver already attached? */ 310 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 311 return 0; 312 313 id = pci_conf_read(pc, tag, PCI_ID_REG); 314 315 /* Invalid vendor ID value? */ 316 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 317 return 0; 318 /* XXX Not invalid, but we've done this ~forever. */ 319 if (PCI_VENDOR(id) == 0) 320 return 0; 321 322 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 323 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 324 return 0; 325 326 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 327 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 328 329 /* Collect memory range info */ 330 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 331 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 332 i = 0; 333 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 334 case PCI_HDRTYPE_PPB: 335 endbar = PCI_MAPREG_PPB_END; 336 break; 337 case PCI_HDRTYPE_PCB: 338 endbar = PCI_MAPREG_PCB_END; 339 break; 340 default: 341 endbar = PCI_MAPREG_END; 342 break; 343 } 344 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 345 struct pci_range *r; 346 pcireg_t type; 347 348 width = 4; 349 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 350 continue; 351 352 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 353 if (PCI_MAPREG_MEM_TYPE(type) == 354 PCI_MAPREG_MEM_TYPE_64BIT) 355 width = 8; 356 357 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 358 if (pci_mapreg_info(pc, tag, bar, type, 359 &r->r_offset, &r->r_size, &r->r_flags) != 0) 360 break; 361 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 362 && (r->r_size == 0x1000000)) { 363 struct pci_range *nr; 364 /* 365 * this has to be a mach64 366 * split things up so each half-aperture can 367 * be mapped PREFETCHABLE except the last page 368 * which may contain registers 369 */ 370 r->r_size = 0x7ff000; 371 r->r_flags = BUS_SPACE_MAP_LINEAR | 372 BUS_SPACE_MAP_PREFETCHABLE; 373 nr = &sc->PCI_SC_DEVICESC(device, 374 function).c_range[i++]; 375 nr->r_offset = r->r_offset + 0x800000; 376 nr->r_size = 0x7ff000; 377 nr->r_flags = BUS_SPACE_MAP_LINEAR | 378 BUS_SPACE_MAP_PREFETCHABLE; 379 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 380 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 381 (bar == 0x10)) { 382 r->r_flags = BUS_SPACE_MAP_LINEAR | 383 BUS_SPACE_MAP_PREFETCHABLE; 384 } 385 } 386 } 387 388 pa.pa_iot = sc->sc_iot; 389 pa.pa_memt = sc->sc_memt; 390 pa.pa_dmat = sc->sc_dmat; 391 pa.pa_dmat64 = sc->sc_dmat64; 392 pa.pa_pc = pc; 393 pa.pa_bus = bus; 394 pa.pa_device = device; 395 pa.pa_function = function; 396 pa.pa_tag = tag; 397 pa.pa_id = id; 398 pa.pa_class = pciclass; 399 400 /* 401 * Set up memory, I/O enable, and PCI command flags 402 * as appropriate. 403 */ 404 pa.pa_flags = sc->sc_flags; 405 406 /* 407 * If the cache line size is not configured, then 408 * clear the MRL/MRM/MWI command-ok flags. 409 */ 410 if (PCI_CACHELINE(bhlcr) == 0) { 411 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 412 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 413 } 414 415 if (sc->sc_bridgetag == NULL) { 416 pa.pa_intrswiz = 0; 417 pa.pa_intrtag = tag; 418 } else { 419 pa.pa_intrswiz = sc->sc_intrswiz + device; 420 pa.pa_intrtag = sc->sc_intrtag; 421 } 422 423 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 424 425 pin = PCI_INTERRUPT_PIN(intr); 426 pa.pa_rawintrpin = pin; 427 if (pin == PCI_INTERRUPT_PIN_NONE) { 428 /* no interrupt */ 429 pa.pa_intrpin = 0; 430 } else { 431 /* 432 * swizzle it based on the number of busses we're 433 * behind and our device number. 434 */ 435 pa.pa_intrpin = /* XXX */ 436 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 437 } 438 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 439 440 devhandle_t devhandle = pci_bus_get_child_devhandle(sc, pa.pa_tag); 441 442 #ifdef __HAVE_PCI_MSI_MSIX 443 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 444 /* 445 * XXX Should we enable MSI mapping ourselves on 446 * systems that have it disabled? 447 */ 448 if (cap & PCI_HT_MSI_ENABLED) { 449 uint64_t addr; 450 if ((cap & PCI_HT_MSI_FIXED) == 0) { 451 addr = pci_conf_read(pc, tag, 452 off + PCI_HT_MSI_ADDR_LO); 453 addr |= (uint64_t)pci_conf_read(pc, tag, 454 off + PCI_HT_MSI_ADDR_HI) << 32; 455 } else 456 addr = PCI_HT_MSI_FIXED_ADDR; 457 458 /* 459 * XXX This will fail to enable MSI on systems 460 * that don't use the canonical address. 461 */ 462 if (addr == PCI_HT_MSI_FIXED_ADDR) { 463 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 464 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 465 } else 466 aprint_verbose_dev(sc->sc_dev, 467 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 468 } 469 } 470 #endif 471 472 if (match != NULL) { 473 ret = (*match)(&pa); 474 if (ret != 0 && pap != NULL) 475 *pap = pa; 476 } else { 477 struct pci_child *c; 478 locs[PCICF_DEV] = device; 479 locs[PCICF_FUNCTION] = function; 480 481 c = &sc->PCI_SC_DEVICESC(device, function); 482 pci_conf_capture(pc, tag, &c->c_conf); 483 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 484 c->c_psok = true; 485 else 486 c->c_psok = false; 487 488 c->c_dev = config_found(sc->sc_dev, &pa, pciprint, 489 CFARGS(.submatch = config_stdsubmatch, 490 .locators = locs, 491 .devhandle = devhandle)); 492 493 ret = (c->c_dev != NULL); 494 } 495 496 return ret; 497 } 498 499 void 500 pcidevdetached(device_t self, device_t child) 501 { 502 struct pci_softc *sc = device_private(self); 503 int d, f; 504 pcitag_t tag; 505 struct pci_child *c; 506 507 d = device_locator(child, PCICF_DEV); 508 f = device_locator(child, PCICF_FUNCTION); 509 510 c = &sc->PCI_SC_DEVICESC(d, f); 511 512 KASSERT(c->c_dev == child); 513 514 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 515 if (c->c_psok) 516 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 517 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 518 c->c_dev = NULL; 519 } 520 521 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 522 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 523 DVF_DETACH_SHUTDOWN); 524 525 int 526 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 527 int *offset, pcireg_t *value) 528 { 529 pcireg_t reg; 530 unsigned int ofs; 531 532 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 533 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 534 return 0; 535 536 /* Determine the Capability List Pointer register to start with. */ 537 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 538 switch (PCI_HDRTYPE_TYPE(reg)) { 539 case 0: /* standard device header */ 540 case 1: /* PCI-PCI bridge header */ 541 ofs = PCI_CAPLISTPTR_REG; 542 break; 543 case 2: /* PCI-CardBus Bridge header */ 544 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 545 break; 546 default: 547 return 0; 548 } 549 550 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 551 while (ofs != 0) { 552 if ((ofs & 3) || (ofs < 0x40)) { 553 int bus, device, function; 554 555 pci_decompose_tag(pc, tag, &bus, &device, &function); 556 557 printf("Skipping broken PCI header on %d:%d:%d\n", 558 bus, device, function); 559 break; 560 } 561 reg = pci_conf_read(pc, tag, ofs); 562 if (PCI_CAPLIST_CAP(reg) == capid) { 563 if (offset) 564 *offset = ofs; 565 if (value) 566 *value = reg; 567 return 1; 568 } 569 ofs = PCI_CAPLIST_NEXT(reg); 570 } 571 572 return 0; 573 } 574 575 int 576 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 577 int *offset, pcireg_t *value) 578 { 579 pcireg_t reg; 580 unsigned int ofs; 581 582 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 583 return 0; 584 585 while (ofs != 0) { 586 #ifdef DIAGNOSTIC 587 if ((ofs & 3) || (ofs < 0x40)) 588 panic("pci_get_ht_capability"); 589 #endif 590 reg = pci_conf_read(pc, tag, ofs); 591 if (PCI_HT_CAP(reg) == capid) { 592 if (offset) 593 *offset = ofs; 594 if (value) 595 *value = reg; 596 return 1; 597 } 598 ofs = PCI_CAPLIST_NEXT(reg); 599 } 600 601 return 0; 602 } 603 604 /* 605 * return number of the devices's MSI vectors 606 * return 0 if the device does not support MSI 607 */ 608 int 609 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 610 { 611 pcireg_t reg; 612 uint32_t mmc; 613 int count, offset; 614 615 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 616 return 0; 617 618 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 619 mmc = PCI_MSI_CTL_MMC(reg); 620 count = 1 << mmc; 621 if (count > PCI_MSI_MAX_VECTORS) { 622 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 623 return 0; 624 } 625 626 return count; 627 } 628 629 /* 630 * return number of the devices's MSI-X vectors 631 * return 0 if the device does not support MSI-X 632 */ 633 int 634 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 635 { 636 pcireg_t reg; 637 int offset; 638 639 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 640 return 0; 641 642 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 643 644 return PCI_MSIX_CTL_TBLSIZE(reg); 645 } 646 647 int 648 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 649 int *offset, pcireg_t *value) 650 { 651 pcireg_t reg; 652 unsigned int ofs; 653 654 /* Only supported for PCI-express devices */ 655 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 656 return 0; 657 658 ofs = PCI_EXTCAPLIST_BASE; 659 reg = pci_conf_read(pc, tag, ofs); 660 if (reg == 0xffffffff || reg == 0) 661 return 0; 662 663 for (;;) { 664 #ifdef DIAGNOSTIC 665 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 666 panic("%s: invalid offset %u", __func__, ofs); 667 #endif 668 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 669 if (offset != NULL) 670 *offset = ofs; 671 if (value != NULL) 672 *value = reg; 673 return 1; 674 } 675 ofs = PCI_EXTCAPLIST_NEXT(reg); 676 if (ofs == 0) 677 break; 678 reg = pci_conf_read(pc, tag, ofs); 679 } 680 681 return 0; 682 } 683 684 int 685 pci_find_device(struct pci_attach_args *pa, 686 int (*match)(const struct pci_attach_args *)) 687 { 688 extern struct cfdriver pci_cd; 689 device_t pcidev; 690 int i; 691 static const int wildcard[2] = { 692 PCICF_DEV_DEFAULT, 693 PCICF_FUNCTION_DEFAULT 694 }; 695 696 for (i = 0; i < pci_cd.cd_ndevs; i++) { 697 pcidev = device_lookup(&pci_cd, i); 698 if (pcidev != NULL && 699 pci_enumerate_bus(device_private(pcidev), wildcard, 700 match, pa) != 0) 701 return 1; 702 } 703 return 0; 704 } 705 706 #ifndef PCI_MACHDEP_ENUMERATE_BUS 707 /* 708 * Generic PCI bus enumeration routine. Used unless machine-dependent 709 * code needs to provide something else. 710 */ 711 int 712 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 713 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 714 { 715 pci_chipset_tag_t pc = sc->sc_pc; 716 int device, function, nfunctions, ret; 717 const struct pci_quirkdata *qd; 718 pcireg_t id, bhlcr; 719 pcitag_t tag; 720 uint8_t devs[32]; 721 int i, n; 722 723 device_t bridgedev; 724 bool arien = false; 725 bool downstream_port = false; 726 727 /* Check PCIe ARI and port type */ 728 bridgedev = device_parent(sc->sc_dev); 729 if (device_is_a(bridgedev, "ppb")) { 730 struct ppb_softc *ppbsc = device_private(bridgedev); 731 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 732 pcitag_t ppbtag = ppbsc->sc_tag; 733 pcireg_t pciecap, capreg, reg; 734 735 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 736 &pciecap, &capreg) != 0) { 737 switch (PCIE_XCAP_TYPE(capreg)) { 738 case PCIE_XCAP_TYPE_RP: 739 case PCIE_XCAP_TYPE_DOWN: 740 case PCIE_XCAP_TYPE_PCI2PCIE: 741 downstream_port = true; 742 break; 743 } 744 745 reg = pci_conf_read(ppbpc, ppbtag, pciecap 746 + PCIE_DCSR2); 747 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 748 arien = true; 749 } 750 } 751 752 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 753 if (downstream_port) { 754 /* PCIe downstream ports only have a single child device */ 755 n = 1; 756 } 757 758 for (i = 0; i < n; i++) { 759 device = devs[i]; 760 761 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 762 (locators[PCICF_DEV] != device)) 763 continue; 764 765 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 766 767 id = pci_conf_read(pc, tag, PCI_ID_REG); 768 769 /* Invalid vendor ID value? */ 770 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 771 continue; 772 /* XXX Not invalid, but we've done this ~forever. */ 773 if (PCI_VENDOR(id) == 0) 774 continue; 775 776 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 777 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 778 continue; 779 780 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 781 782 if (qd != NULL && 783 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 784 nfunctions = 8; 785 else if (qd != NULL && 786 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 787 nfunctions = 1; 788 else if (arien) 789 nfunctions = 8; /* Scan all if ARI is enabled */ 790 else 791 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 792 793 #ifdef __PCI_DEV_FUNCORDER 794 char funcs[8]; 795 int j; 796 for (j = 0; j < nfunctions; j++) { 797 funcs[j] = j; 798 } 799 if (j < __arraycount(funcs)) 800 funcs[j] = -1; 801 if (nfunctions > 1) { 802 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 803 nfunctions, funcs); 804 } 805 for (j = 0; 806 j < 8 && (function = funcs[j]) < 8 && function >= 0; 807 j++) { 808 #else 809 for (function = 0; function < nfunctions; function++) { 810 #endif 811 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 812 && (locators[PCICF_FUNCTION] != function)) 813 continue; 814 815 if (qd != NULL && 816 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 817 continue; 818 tag = pci_make_tag(pc, sc->sc_bus, device, function); 819 ret = pci_probe_device(sc, tag, match, pap); 820 if (match != NULL && ret != 0) 821 return ret; 822 } 823 } 824 return 0; 825 } 826 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 827 828 829 /* 830 * Vital Product Data (PCI 2.2) 831 */ 832 833 int 834 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 835 pcireg_t *data) 836 { 837 uint32_t reg; 838 int ofs, i, j; 839 840 KASSERT(data != NULL); 841 KASSERT((offset + count) < 0x7fff); 842 843 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 844 return 1; 845 846 for (i = 0; i < count; offset += sizeof(*data), i++) { 847 reg &= 0x0000ffff; 848 reg &= ~PCI_VPD_OPFLAG; 849 reg |= PCI_VPD_ADDRESS(offset); 850 pci_conf_write(pc, tag, ofs, reg); 851 852 /* 853 * PCI 2.2 does not specify how long we should poll 854 * for completion nor whether the operation can fail. 855 */ 856 j = 0; 857 do { 858 if (j++ == 20) 859 return 1; 860 delay(4); 861 reg = pci_conf_read(pc, tag, ofs); 862 } while ((reg & PCI_VPD_OPFLAG) == 0); 863 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 864 } 865 866 return 0; 867 } 868 869 int 870 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 871 pcireg_t *data) 872 { 873 pcireg_t reg; 874 int ofs, i, j; 875 876 KASSERT(data != NULL); 877 KASSERT((offset + count) < 0x7fff); 878 879 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 880 return 1; 881 882 for (i = 0; i < count; offset += sizeof(*data), i++) { 883 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 884 885 reg &= 0x0000ffff; 886 reg |= PCI_VPD_OPFLAG; 887 reg |= PCI_VPD_ADDRESS(offset); 888 pci_conf_write(pc, tag, ofs, reg); 889 890 /* 891 * PCI 2.2 does not specify how long we should poll 892 * for completion nor whether the operation can fail. 893 */ 894 j = 0; 895 do { 896 if (j++ == 20) 897 return 1; 898 delay(1); 899 reg = pci_conf_read(pc, tag, ofs); 900 } while (reg & PCI_VPD_OPFLAG); 901 } 902 903 return 0; 904 } 905 906 int 907 pci_dma64_available(const struct pci_attach_args *pa) 908 { 909 #ifdef _PCI_HAVE_DMA64 910 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 911 return 1; 912 #endif 913 return 0; 914 } 915 916 void 917 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 918 struct pci_conf_state *pcs) 919 { 920 int off; 921 922 for (off = 0; off < 16; off++) 923 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 924 925 /* For PCI-X */ 926 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 927 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 928 929 /* For PCIe */ 930 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 931 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 932 unsigned int devtype; 933 934 devtype = PCIE_XCAP_TYPE(xcap); 935 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 936 937 if (PCIE_HAS_LINKREGS(devtype)) 938 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 939 off + PCIE_LCSR); 940 941 if ((xcap & PCIE_XCAP_SI) != 0) 942 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 943 off + PCIE_SLCSR); 944 945 if (PCIE_HAS_ROOTREGS(devtype)) 946 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 947 off + PCIE_RCR); 948 949 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 950 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 951 off + PCIE_DCSR2); 952 953 if (PCIE_HAS_LINKREGS(devtype)) 954 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 955 off + PCIE_LCSR2); 956 957 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 958 } 959 } 960 961 /* For MSI */ 962 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 963 bool bit64, pvmask; 964 965 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 966 967 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 968 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 969 970 /* Address */ 971 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 972 if (bit64) 973 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 974 off + PCI_MSI_MADDR64_HI); 975 976 /* Data */ 977 pcs->msi_mdata = pci_conf_read(pc, tag, 978 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 979 980 /* Per-vector masking */ 981 if (pvmask) 982 pcs->msi_mask = pci_conf_read(pc, tag, 983 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 984 } 985 986 /* For MSI-X */ 987 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 988 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 989 } 990 991 void 992 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 993 struct pci_conf_state *pcs) 994 { 995 int off; 996 pcireg_t val; 997 998 for (off = 15; off >= 0; off--) { 999 val = pci_conf_read(pc, tag, (off * 4)); 1000 if (val != pcs->reg[off]) 1001 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 1002 } 1003 1004 /* For PCI-X */ 1005 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 1006 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 1007 1008 /* For PCIe */ 1009 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 1010 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 1011 unsigned int devtype; 1012 1013 devtype = PCIE_XCAP_TYPE(xcap); 1014 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 1015 1016 /* 1017 * PCIe capability is variable sized. To not to write the next 1018 * area, check the existence of each register. 1019 */ 1020 if (PCIE_HAS_LINKREGS(devtype)) 1021 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 1022 1023 if ((xcap & PCIE_XCAP_SI) != 0) 1024 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 1025 1026 if (PCIE_HAS_ROOTREGS(devtype)) 1027 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1028 1029 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1030 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1031 1032 if (PCIE_HAS_LINKREGS(devtype)) 1033 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1034 pcs->e_lcr2); 1035 1036 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1037 } 1038 } 1039 1040 /* For MSI */ 1041 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1042 pcireg_t reg; 1043 bool bit64, pvmask; 1044 1045 /* First, drop Enable bit in case it's already set. */ 1046 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1047 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1048 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1049 1050 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1051 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1052 1053 /* Address */ 1054 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1055 1056 if (bit64) 1057 pci_conf_write(pc, tag, 1058 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1059 1060 /* Data */ 1061 pci_conf_write(pc, tag, 1062 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1063 pcs->msi_mdata); 1064 1065 /* Per-vector masking */ 1066 if (pvmask) 1067 pci_conf_write(pc, tag, 1068 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1069 pcs->msi_mask); 1070 1071 /* Write CTRL register in the end */ 1072 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1073 } 1074 1075 /* For MSI-X */ 1076 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1077 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1078 } 1079 1080 /* 1081 * Power Management Capability (Rev 2.2) 1082 */ 1083 static int 1084 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1085 int offset) 1086 { 1087 pcireg_t value, now; 1088 1089 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1090 now = value & PCI_PMCSR_STATE_MASK; 1091 switch (now) { 1092 case PCI_PMCSR_STATE_D0: 1093 case PCI_PMCSR_STATE_D1: 1094 case PCI_PMCSR_STATE_D2: 1095 case PCI_PMCSR_STATE_D3: 1096 *state = now; 1097 return 0; 1098 default: 1099 return EINVAL; 1100 } 1101 } 1102 1103 int 1104 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1105 { 1106 int offset; 1107 pcireg_t value; 1108 1109 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1110 return EOPNOTSUPP; 1111 1112 return pci_get_powerstate_int(pc, tag, state, offset); 1113 } 1114 1115 static int 1116 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1117 int offset, pcireg_t cap_reg) 1118 { 1119 pcireg_t value, cap, now; 1120 1121 cap = cap_reg >> PCI_PMCR_SHIFT; 1122 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1123 now = value & PCI_PMCSR_STATE_MASK; 1124 value &= ~PCI_PMCSR_STATE_MASK; 1125 1126 if (now == state) 1127 return 0; 1128 switch (state) { 1129 case PCI_PMCSR_STATE_D0: 1130 break; 1131 case PCI_PMCSR_STATE_D1: 1132 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1133 printf("invalid transition from %d to D1\n", (int)now); 1134 return EINVAL; 1135 } 1136 if (!(cap & PCI_PMCR_D1SUPP)) { 1137 printf("D1 not supported\n"); 1138 return EOPNOTSUPP; 1139 } 1140 break; 1141 case PCI_PMCSR_STATE_D2: 1142 if (now == PCI_PMCSR_STATE_D3) { 1143 printf("invalid transition from %d to D2\n", (int)now); 1144 return EINVAL; 1145 } 1146 if (!(cap & PCI_PMCR_D2SUPP)) { 1147 printf("D2 not supported\n"); 1148 return EOPNOTSUPP; 1149 } 1150 break; 1151 case PCI_PMCSR_STATE_D3: 1152 break; 1153 default: 1154 return EINVAL; 1155 } 1156 value |= state; 1157 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1158 /* delay according to pcipm1.2, ch. 5.6.1 */ 1159 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1160 DELAY(10000); 1161 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1162 DELAY(200); 1163 1164 return 0; 1165 } 1166 1167 int 1168 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1169 { 1170 int offset; 1171 pcireg_t value; 1172 1173 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1174 printf("pci_set_powerstate not supported\n"); 1175 return EOPNOTSUPP; 1176 } 1177 1178 return pci_set_powerstate_int(pc, tag, state, offset, value); 1179 } 1180 1181 int 1182 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1183 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1184 { 1185 pcireg_t pmode; 1186 int error; 1187 1188 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1189 return error; 1190 1191 switch (pmode) { 1192 case PCI_PMCSR_STATE_D0: 1193 break; 1194 case PCI_PMCSR_STATE_D3: 1195 if (wakefun == NULL) { 1196 /* 1197 * The card has lost all configuration data in 1198 * this state, so punt. 1199 */ 1200 aprint_error_dev(dev, 1201 "unable to wake up from power state D3\n"); 1202 return EOPNOTSUPP; 1203 } 1204 /*FALLTHROUGH*/ 1205 default: 1206 if (wakefun) { 1207 error = (*wakefun)(pc, tag, dev, pmode); 1208 if (error) 1209 return error; 1210 } 1211 aprint_normal_dev(dev, "waking up from power state D%d\n", 1212 pmode); 1213 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1214 return error; 1215 } 1216 return 0; 1217 } 1218 1219 int 1220 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1221 device_t dev, pcireg_t state) 1222 { 1223 return 0; 1224 } 1225 1226 struct pci_child_power { 1227 struct pci_conf_state p_pciconf; 1228 pci_chipset_tag_t p_pc; 1229 pcitag_t p_tag; 1230 bool p_has_pm; 1231 int p_pm_offset; 1232 pcireg_t p_pm_cap; 1233 pcireg_t p_class; 1234 pcireg_t p_csr; 1235 }; 1236 1237 static bool 1238 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1239 { 1240 struct pci_child_power *priv = device_pmf_bus_private(dv); 1241 pcireg_t ocsr, csr; 1242 1243 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1244 1245 if (!priv->p_has_pm) 1246 return true; /* ??? hopefully handled by ACPI */ 1247 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1248 return true; /* XXX */ 1249 1250 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1251 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1252 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1253 | PCI_COMMAND_MASTER_ENABLE); 1254 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1255 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1256 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1257 pci_conf_write(priv->p_pc, priv->p_tag, 1258 PCI_COMMAND_STATUS_REG, ocsr); 1259 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1260 return false; 1261 } 1262 return true; 1263 } 1264 1265 static void 1266 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1267 int off) 1268 { 1269 pcireg_t pmcsr; 1270 1271 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1272 1273 if (pmcsr & PCI_PMCSR_PME_STS) { 1274 /* Clear W1C bit */ 1275 pmcsr |= PCI_PMCSR_PME_STS; 1276 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1277 aprint_verbose_dev(dv, "Clear PME# now\n"); 1278 } 1279 } 1280 1281 static bool 1282 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1283 { 1284 struct pci_child_power *priv = device_pmf_bus_private(dv); 1285 1286 if (priv->p_has_pm) { 1287 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1288 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1289 aprint_error_dev(dv, 1290 "unsupported state, continuing.\n"); 1291 return false; 1292 } 1293 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1294 priv->p_pm_offset); 1295 } 1296 1297 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1298 1299 return true; 1300 } 1301 1302 static bool 1303 pci_child_shutdown(device_t dv, int how) 1304 { 1305 struct pci_child_power *priv = device_pmf_bus_private(dv); 1306 pcireg_t csr; 1307 1308 /* restore original bus-mastering state */ 1309 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1310 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1311 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1312 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1313 return true; 1314 } 1315 1316 static void 1317 pci_child_deregister(device_t dv) 1318 { 1319 struct pci_child_power *priv = device_pmf_bus_private(dv); 1320 1321 free(priv, M_DEVBUF); 1322 } 1323 1324 static void 1325 pci_child_register(device_t child) 1326 { 1327 device_t self = device_parent(child); 1328 struct pci_softc *sc = device_private(self); 1329 struct pci_child_power *priv; 1330 int device, function, off; 1331 pcireg_t reg; 1332 1333 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1334 1335 device = device_locator(child, PCICF_DEV); 1336 function = device_locator(child, PCICF_FUNCTION); 1337 1338 priv->p_pc = sc->sc_pc; 1339 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1340 function); 1341 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1342 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1343 PCI_COMMAND_STATUS_REG); 1344 1345 if (pci_get_capability(priv->p_pc, priv->p_tag, 1346 PCI_CAP_PWRMGMT, &off, ®)) { 1347 priv->p_has_pm = true; 1348 priv->p_pm_offset = off; 1349 priv->p_pm_cap = reg; 1350 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1351 } else { 1352 priv->p_has_pm = false; 1353 priv->p_pm_offset = -1; 1354 } 1355 1356 device_pmf_bus_register(child, priv, pci_child_suspend, 1357 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1358 } 1359 1360 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1361 1362 static int 1363 pci_modcmd(modcmd_t cmd, void *priv) 1364 { 1365 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1366 return 0; 1367 return ENOTTY; 1368 }
Cache object: 49349c81f18f7fa52ef37e1d310ff515
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