Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci_host_generic_acpi.c
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1 /*- 2 * Copyright (C) 2018 Cavium Inc. 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Semihalf under 8 * the sponsorship of the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* Generic ECAM PCIe driver */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/rman.h> 44 #include <sys/module.h> 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/cpuset.h> 48 #include <sys/rwlock.h> 49 50 #include <contrib/dev/acpica/include/acpi.h> 51 #include <contrib/dev/acpica/include/accommon.h> 52 53 #include <dev/acpica/acpivar.h> 54 #include <dev/acpica/acpi_pcibvar.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcib_private.h> 59 #include <dev/pci/pci_host_generic.h> 60 #include <dev/pci/pci_host_generic_acpi.h> 61 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 #include "acpi_bus_if.h" 68 69 /* Assembling ECAM Configuration Address */ 70 #define PCIE_BUS_SHIFT 20 71 #define PCIE_SLOT_SHIFT 15 72 #define PCIE_FUNC_SHIFT 12 73 #define PCIE_BUS_MASK 0xFF 74 #define PCIE_SLOT_MASK 0x1F 75 #define PCIE_FUNC_MASK 0x07 76 #define PCIE_REG_MASK 0xFFF 77 78 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 79 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 80 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 81 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 82 ((reg) & PCIE_REG_MASK)) 83 84 #define PCI_IO_WINDOW_OFFSET 0x1000 85 86 #define SPACE_CODE_SHIFT 24 87 #define SPACE_CODE_MASK 0x3 88 #define SPACE_CODE_IO_SPACE 0x1 89 #define PROPS_CELL_SIZE 1 90 #define PCI_ADDR_CELL_SIZE 2 91 92 static struct { 93 char oem_id[ACPI_OEM_ID_SIZE + 1]; 94 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 95 uint32_t quirks; 96 } pci_acpi_quirks[] = { 97 { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 98 { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK }, 99 { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK }, 100 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK }, 101 { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 102 { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 103 { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 104 { 0 }, 105 }; 106 107 /* Forward prototypes */ 108 109 static int generic_pcie_acpi_probe(device_t dev); 110 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *); 111 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *); 112 113 /* 114 * generic_pcie_acpi_probe - look for root bridge flag 115 */ 116 static int 117 generic_pcie_acpi_probe(device_t dev) 118 { 119 ACPI_DEVICE_INFO *devinfo; 120 ACPI_HANDLE h; 121 int root; 122 123 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || 124 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) 125 return (ENXIO); 126 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; 127 AcpiOsFree(devinfo); 128 if (!root) 129 return (ENXIO); 130 131 device_set_desc(dev, "Generic PCI host controller"); 132 return (BUS_PROBE_GENERIC); 133 } 134 135 /* 136 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces 137 * 'produced' by this bridge 138 */ 139 static ACPI_STATUS 140 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg) 141 { 142 device_t dev = (device_t)arg; 143 struct generic_pcie_acpi_softc *sc; 144 rman_res_t min, max, off; 145 int r, restype; 146 147 sc = device_get_softc(dev); 148 r = sc->base.nranges; 149 switch (res->Type) { 150 case ACPI_RESOURCE_TYPE_ADDRESS16: 151 restype = res->Data.Address16.ResourceType; 152 min = res->Data.Address16.Address.Minimum; 153 max = res->Data.Address16.Address.Maximum; 154 break; 155 case ACPI_RESOURCE_TYPE_ADDRESS32: 156 restype = res->Data.Address32.ResourceType; 157 min = res->Data.Address32.Address.Minimum; 158 max = res->Data.Address32.Address.Maximum; 159 off = res->Data.Address32.Address.TranslationOffset; 160 break; 161 case ACPI_RESOURCE_TYPE_ADDRESS64: 162 restype = res->Data.Address64.ResourceType; 163 min = res->Data.Address64.Address.Minimum; 164 max = res->Data.Address64.Address.Maximum; 165 off = res->Data.Address64.Address.TranslationOffset; 166 break; 167 case ACPI_RESOURCE_TYPE_FIXED_MEMORY32: 168 /* 169 * The Microsoft Dev Kit 2023 uses a fixed memory region 170 * for some PCI controllers. For this memory the 171 * ResourceType is ACPI_IO_RANGE meaning we create an IO 172 * resource. As drivers expect it to be a memory resource 173 * force the type here. 174 */ 175 restype = ACPI_MEMORY_RANGE; 176 min = res->Data.FixedMemory32.Address; 177 max = res->Data.FixedMemory32.Address + 178 res->Data.FixedMemory32.AddressLength - 1; 179 off = 0; 180 break; 181 default: 182 return (AE_OK); 183 } 184 185 /* Save detected ranges */ 186 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE || 187 res->Data.Address.ResourceType == ACPI_IO_RANGE) { 188 sc->base.ranges[r].pci_base = min; 189 sc->base.ranges[r].phys_base = min + off; 190 sc->base.ranges[r].size = max - min + 1; 191 if (restype == ACPI_MEMORY_RANGE) 192 sc->base.ranges[r].flags |= FLAG_TYPE_MEM; 193 else if (restype == ACPI_IO_RANGE) 194 sc->base.ranges[r].flags |= FLAG_TYPE_IO; 195 sc->base.nranges++; 196 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) { 197 sc->base.bus_start = min; 198 sc->base.bus_end = max; 199 } 200 return (AE_OK); 201 } 202 203 static void 204 pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc, 205 ACPI_TABLE_HEADER *hdr) 206 { 207 int i; 208 209 for (i = 0; pci_acpi_quirks[i].quirks; i++) { 210 if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id, 211 ACPI_OEM_ID_SIZE) != 0) 212 continue; 213 if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id, 214 ACPI_OEM_TABLE_ID_SIZE) != 0) 215 continue; 216 sc->base.quirks |= pci_acpi_quirks[i].quirks; 217 } 218 } 219 220 static int 221 pci_host_acpi_get_ecam_resource(device_t dev) 222 { 223 struct generic_pcie_acpi_softc *sc; 224 struct acpi_device *ad; 225 struct resource_list *rl; 226 ACPI_TABLE_HEADER *hdr; 227 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end; 228 ACPI_HANDLE handle; 229 ACPI_STATUS status; 230 rman_res_t base, start, end; 231 int found, val; 232 233 sc = device_get_softc(dev); 234 handle = acpi_get_handle(dev); 235 236 /* Try MCFG first */ 237 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr); 238 if (ACPI_SUCCESS(status)) { 239 found = FALSE; 240 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length); 241 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1); 242 while (mcfg_entry < mcfg_end && !found) { 243 if (mcfg_entry->PciSegment == sc->base.ecam && 244 mcfg_entry->StartBusNumber <= sc->base.bus_start && 245 mcfg_entry->EndBusNumber >= sc->base.bus_start) 246 found = TRUE; 247 else 248 mcfg_entry++; 249 } 250 if (found) { 251 if (mcfg_entry->EndBusNumber < sc->base.bus_end) 252 sc->base.bus_end = mcfg_entry->EndBusNumber; 253 base = mcfg_entry->Address; 254 } else { 255 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n", 256 sc->base.bus_start, sc->base.bus_end); 257 return (ENXIO); 258 } 259 pci_host_acpi_get_oem_quirks(sc, hdr); 260 if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK) 261 device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); 262 } else { 263 status = acpi_GetInteger(handle, "_CBA", &val); 264 if (ACPI_SUCCESS(status)) 265 base = val; 266 else 267 return (ENXIO); 268 } 269 270 /* add as MEM rid 0 */ 271 ad = device_get_ivars(dev); 272 rl = &ad->ad_rl; 273 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT); 274 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1; 275 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1); 276 if (bootverbose) 277 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n", 278 sc->base.bus_start, sc->base.bus_end, start, end); 279 return (0); 280 } 281 282 int 283 pci_host_generic_acpi_init(device_t dev) 284 { 285 struct generic_pcie_acpi_softc *sc; 286 ACPI_HANDLE handle; 287 ACPI_STATUS status; 288 int error; 289 290 sc = device_get_softc(dev); 291 handle = acpi_get_handle(dev); 292 293 /* Get Start bus number for the PCI host bus is from _BBN method */ 294 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start); 295 if (ACPI_FAILURE(status)) { 296 device_printf(dev, "No _BBN, using start bus 0\n"); 297 sc->base.bus_start = 0; 298 } 299 sc->base.bus_end = 255; 300 301 /* Get PCI Segment (domain) needed for MCFG lookup */ 302 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam); 303 if (ACPI_FAILURE(status)) { 304 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n"); 305 sc->base.ecam = 0; 306 } 307 308 /* Bus decode ranges */ 309 status = AcpiWalkResources(handle, "_CRS", 310 pci_host_generic_acpi_parse_resource, (void *)dev); 311 if (ACPI_FAILURE(status)) 312 return (ENXIO); 313 314 /* Coherency attribute */ 315 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent))) 316 sc->base.coherent = 0; 317 if (bootverbose) 318 device_printf(dev, "Bus is%s cache-coherent\n", 319 sc->base.coherent ? "" : " not"); 320 321 /* add config space resource */ 322 pci_host_acpi_get_ecam_resource(dev); 323 acpi_pcib_fetch_prt(dev, &sc->ap_prt); 324 325 error = pci_host_generic_core_attach(dev); 326 if (error != 0) 327 return (error); 328 329 return (0); 330 } 331 332 static int 333 pci_host_generic_acpi_attach(device_t dev) 334 { 335 int error; 336 337 error = pci_host_generic_acpi_init(dev); 338 if (error != 0) 339 return (error); 340 341 device_add_child(dev, "pci", -1); 342 return (bus_generic_attach(dev)); 343 } 344 345 static int 346 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index, 347 uintptr_t *result) 348 { 349 struct generic_pcie_acpi_softc *sc; 350 351 sc = device_get_softc(dev); 352 353 if (index == PCIB_IVAR_BUS) { 354 *result = sc->base.bus_start; 355 return (0); 356 } 357 358 if (index == PCIB_IVAR_DOMAIN) { 359 *result = sc->base.ecam; 360 return (0); 361 } 362 363 if (bootverbose) 364 device_printf(dev, "ERROR: Unknown index %d.\n", index); 365 return (ENOENT); 366 } 367 368 static int 369 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin) 370 { 371 struct generic_pcie_acpi_softc *sc; 372 373 sc = device_get_softc(bus); 374 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt)); 375 } 376 377 static u_int 378 generic_pcie_get_xref(device_t pci, device_t child) 379 { 380 struct generic_pcie_acpi_softc *sc; 381 uintptr_t rid; 382 u_int xref, devid; 383 int err; 384 385 sc = device_get_softc(pci); 386 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 387 if (err != 0) 388 return (ACPI_MSI_XREF); 389 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 390 if (err != 0) 391 return (ACPI_MSI_XREF); 392 return (xref); 393 } 394 395 static u_int 396 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id) 397 { 398 struct generic_pcie_acpi_softc *sc; 399 uintptr_t rid; 400 u_int xref, devid; 401 int err; 402 403 sc = device_get_softc(pci); 404 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 405 if (err != 0) 406 return (err); 407 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 408 if (err == 0) 409 *id = devid; 410 else 411 *id = rid; /* RID not in IORT, likely FW bug, ignore */ 412 return (0); 413 } 414 415 static int 416 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count, 417 int maxcount, int *irqs) 418 { 419 420 #if defined(INTRNG) 421 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child), 422 count, maxcount, irqs)); 423 #else 424 return (ENXIO); 425 #endif 426 } 427 428 static int 429 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count, 430 int *irqs) 431 { 432 433 #if defined(INTRNG) 434 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child), 435 count, irqs)); 436 #else 437 return (ENXIO); 438 #endif 439 } 440 441 static int 442 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 443 uint32_t *data) 444 { 445 446 #if defined(INTRNG) 447 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq, 448 addr, data)); 449 #else 450 return (ENXIO); 451 #endif 452 } 453 454 static int 455 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq) 456 { 457 458 #if defined(INTRNG) 459 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child), 460 irq)); 461 #else 462 return (ENXIO); 463 #endif 464 } 465 466 static int 467 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq) 468 { 469 470 #if defined(INTRNG) 471 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child), 472 irq)); 473 #else 474 return (ENXIO); 475 #endif 476 } 477 478 static int 479 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type, 480 uintptr_t *id) 481 { 482 483 if (type == PCI_ID_MSI) 484 return (generic_pcie_map_id(pci, child, id)); 485 else 486 return (pcib_get_id(pci, child, type, id)); 487 } 488 489 static device_method_t generic_pcie_acpi_methods[] = { 490 DEVMETHOD(device_probe, generic_pcie_acpi_probe), 491 DEVMETHOD(device_attach, pci_host_generic_acpi_attach), 492 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar), 493 494 /* pcib interface */ 495 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt), 496 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi), 497 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi), 498 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix), 499 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix), 500 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi), 501 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id), 502 503 DEVMETHOD_END 504 }; 505 506 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods, 507 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver); 508 509 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, 0, 0);
Cache object: 8c9d262679b6aa8f72cc9ce8a2cd3afd
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