Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci_host_generic_fdt.c
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1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/rman.h> 48 49 #if defined(INTRNG) 50 #include <machine/intr.h> 51 #endif 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 #include <dev/pci/pci_host_generic.h> 62 #include <dev/pci/pci_host_generic_fdt.h> 63 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 68 #define SPACE_CODE_SHIFT 24 69 #define SPACE_CODE_MASK 0x3 70 #define SPACE_CODE_IO_SPACE 0x1 71 #define PROPS_CELL_SIZE 1 72 #define PCI_ADDR_CELL_SIZE 2 73 74 struct pci_ofw_devinfo { 75 STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link; 76 struct ofw_bus_devinfo di_dinfo; 77 uint8_t slot; 78 uint8_t func; 79 uint8_t bus; 80 }; 81 82 /* Forward prototypes */ 83 84 static int generic_pcie_fdt_probe(device_t dev); 85 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 86 static int generic_pcie_ofw_bus_attach(device_t); 87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 88 device_t); 89 90 static int 91 generic_pcie_fdt_probe(device_t dev) 92 { 93 94 if (!ofw_bus_status_okay(dev)) 95 return (ENXIO); 96 97 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 98 device_set_desc(dev, "Generic PCI host controller"); 99 return (BUS_PROBE_GENERIC); 100 } 101 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 102 device_set_desc(dev, "GEM5 PCIe host controller"); 103 return (BUS_PROBE_DEFAULT); 104 } 105 106 return (ENXIO); 107 } 108 109 int 110 pci_host_generic_setup_fdt(device_t dev) 111 { 112 struct generic_pcie_fdt_softc *sc; 113 phandle_t node; 114 int error; 115 116 sc = device_get_softc(dev); 117 118 STAILQ_INIT(&sc->pci_ofw_devlist); 119 120 /* Retrieve 'ranges' property from FDT */ 121 if (bootverbose) 122 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 123 if (parse_pci_mem_ranges(dev, &sc->base)) 124 return (ENXIO); 125 126 /* Attach OFW bus */ 127 if (generic_pcie_ofw_bus_attach(dev) != 0) 128 return (ENXIO); 129 130 node = ofw_bus_get_node(dev); 131 if (sc->base.coherent == 0) { 132 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 133 } 134 if (bootverbose) 135 device_printf(dev, "Bus is%s cache-coherent\n", 136 sc->base.coherent ? "" : " not"); 137 138 /* TODO parse FDT bus ranges */ 139 sc->base.bus_start = 0; 140 sc->base.bus_end = 0xFF; 141 142 /* 143 * ofw_pcib uses device unit as PCI domain number. 144 * Do the same. Some boards have multiple RCs handled 145 * by different drivers, this ensures that there are 146 * no collisions. 147 */ 148 sc->base.ecam = device_get_unit(dev); 149 150 error = pci_host_generic_core_attach(dev); 151 if (error != 0) 152 return (error); 153 154 if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") || 155 ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") || 156 ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) { 157 device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); 158 sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK; 159 } 160 161 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 162 163 return (0); 164 } 165 166 int 167 pci_host_generic_fdt_attach(device_t dev) 168 { 169 int error; 170 171 error = pci_host_generic_setup_fdt(dev); 172 if (error != 0) 173 return (error); 174 175 device_add_child(dev, "pci", -1); 176 return (bus_generic_attach(dev)); 177 } 178 179 static int 180 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 181 { 182 pcell_t pci_addr_cells, parent_addr_cells; 183 pcell_t attributes, size_cells; 184 cell_t *base_ranges; 185 int nbase_ranges; 186 phandle_t node; 187 int i, j, k; 188 int tuple; 189 190 node = ofw_bus_get_node(dev); 191 192 OF_getencprop(node, "#address-cells", &pci_addr_cells, 193 sizeof(pci_addr_cells)); 194 OF_getencprop(node, "#size-cells", &size_cells, 195 sizeof(size_cells)); 196 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 197 sizeof(parent_addr_cells)); 198 199 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 200 device_printf(dev, 201 "Unexpected number of address or size cells in FDT\n"); 202 return (ENXIO); 203 } 204 205 nbase_ranges = OF_getproplen(node, "ranges"); 206 sc->nranges = nbase_ranges / sizeof(cell_t) / 207 (parent_addr_cells + pci_addr_cells + size_cells); 208 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 209 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 210 211 for (i = 0, j = 0; i < sc->nranges; i++) { 212 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 213 SPACE_CODE_MASK; 214 if (attributes == SPACE_CODE_IO_SPACE) { 215 sc->ranges[i].flags |= FLAG_TYPE_IO; 216 } else { 217 sc->ranges[i].flags |= FLAG_TYPE_MEM; 218 } 219 220 sc->ranges[i].pci_base = 0; 221 for (k = 0; k < (pci_addr_cells - 1); k++) { 222 sc->ranges[i].pci_base <<= 32; 223 sc->ranges[i].pci_base |= base_ranges[j++]; 224 } 225 sc->ranges[i].phys_base = 0; 226 for (k = 0; k < parent_addr_cells; k++) { 227 sc->ranges[i].phys_base <<= 32; 228 sc->ranges[i].phys_base |= base_ranges[j++]; 229 } 230 sc->ranges[i].size = 0; 231 for (k = 0; k < size_cells; k++) { 232 sc->ranges[i].size <<= 32; 233 sc->ranges[i].size |= base_ranges[j++]; 234 } 235 } 236 237 for (; i < MAX_RANGES_TUPLES; i++) { 238 /* zero-fill remaining tuples to mark empty elements in array */ 239 sc->ranges[i].pci_base = 0; 240 sc->ranges[i].phys_base = 0; 241 sc->ranges[i].size = 0; 242 } 243 244 if (bootverbose) { 245 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 246 device_printf(dev, 247 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 248 sc->ranges[tuple].pci_base, 249 sc->ranges[tuple].phys_base, 250 sc->ranges[tuple].size); 251 } 252 } 253 254 free(base_ranges, M_DEVBUF); 255 return (0); 256 } 257 258 static int 259 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 260 { 261 struct generic_pcie_fdt_softc *sc; 262 struct ofw_pci_register reg; 263 uint32_t pintr, mintr[4]; 264 phandle_t iparent; 265 int intrcells; 266 267 sc = device_get_softc(bus); 268 pintr = pin; 269 270 bzero(®, sizeof(reg)); 271 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 272 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 273 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 274 275 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 276 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 277 mintr, sizeof(mintr), &iparent); 278 if (intrcells) { 279 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 280 return (pintr); 281 } 282 283 device_printf(bus, "could not route pin %d for device %d.%d\n", 284 pin, pci_get_slot(dev), pci_get_function(dev)); 285 return (PCI_INVALID_IRQ); 286 } 287 288 static int 289 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 290 int maxcount, int *irqs) 291 { 292 #if defined(INTRNG) 293 phandle_t msi_parent; 294 int err; 295 296 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 297 &msi_parent, NULL); 298 if (err != 0) 299 return (err); 300 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 301 irqs)); 302 #else 303 return (ENXIO); 304 #endif 305 } 306 307 static int 308 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 309 { 310 #if defined(INTRNG) 311 phandle_t msi_parent; 312 int err; 313 314 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 315 &msi_parent, NULL); 316 if (err != 0) 317 return (err); 318 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 319 #else 320 return (ENXIO); 321 #endif 322 } 323 324 static int 325 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 326 uint32_t *data) 327 { 328 #if defined(INTRNG) 329 phandle_t msi_parent; 330 int err; 331 332 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 333 &msi_parent, NULL); 334 if (err != 0) 335 return (err); 336 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 337 #else 338 return (ENXIO); 339 #endif 340 } 341 342 static int 343 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 344 { 345 #if defined(INTRNG) 346 phandle_t msi_parent; 347 int err; 348 349 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 350 &msi_parent, NULL); 351 if (err != 0) 352 return (err); 353 return (intr_alloc_msix(pci, child, msi_parent, irq)); 354 #else 355 return (ENXIO); 356 #endif 357 } 358 359 static int 360 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 361 { 362 #if defined(INTRNG) 363 phandle_t msi_parent; 364 int err; 365 366 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 367 &msi_parent, NULL); 368 if (err != 0) 369 return (err); 370 return (intr_release_msix(pci, child, msi_parent, irq)); 371 #else 372 return (ENXIO); 373 #endif 374 } 375 376 static int 377 generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id) 378 { 379 struct pci_id_ofw_iommu *iommu; 380 uint32_t iommu_rid; 381 uint32_t iommu_xref; 382 uint16_t pci_rid; 383 phandle_t node; 384 int err; 385 386 node = ofw_bus_get_node(pci); 387 pci_rid = pci_get_rid(child); 388 389 iommu = (struct pci_id_ofw_iommu *)id; 390 391 err = ofw_bus_iommu_map(node, pci_rid, &iommu_xref, &iommu_rid); 392 if (err == 0) { 393 iommu->id = iommu_rid; 394 iommu->xref = iommu_xref; 395 } 396 397 return (err); 398 } 399 400 int 401 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 402 uintptr_t *id) 403 { 404 phandle_t node; 405 int err; 406 uint32_t rid; 407 uint16_t pci_rid; 408 409 if (type == PCI_ID_OFW_IOMMU) 410 return (generic_pcie_get_iommu(pci, child, id)); 411 412 if (type != PCI_ID_MSI) 413 return (pcib_get_id(pci, child, type, id)); 414 415 node = ofw_bus_get_node(pci); 416 pci_rid = pci_get_rid(child); 417 418 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 419 if (err != 0) 420 return (err); 421 *id = rid; 422 423 return (0); 424 } 425 426 static const struct ofw_bus_devinfo * 427 generic_pcie_ofw_get_devinfo(device_t bus, device_t child) 428 { 429 struct generic_pcie_fdt_softc *sc; 430 struct pci_ofw_devinfo *di; 431 uint8_t slot, func, busno; 432 433 sc = device_get_softc(bus); 434 slot = pci_get_slot(child); 435 func = pci_get_function(child); 436 busno = pci_get_bus(child); 437 438 STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link) 439 if (slot == di->slot && func == di->func && busno == di->bus) 440 return (&di->di_dinfo); 441 442 return (NULL); 443 } 444 445 /* Helper functions */ 446 447 static int 448 generic_pcie_ofw_bus_attach(device_t dev) 449 { 450 struct generic_pcie_fdt_softc *sc; 451 struct pci_ofw_devinfo *di; 452 phandle_t parent, node; 453 pcell_t reg[5]; 454 ssize_t len; 455 456 sc = device_get_softc(dev); 457 parent = ofw_bus_get_node(dev); 458 if (parent == 0) 459 return (0); 460 461 /* Iterate through all bus subordinates */ 462 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 463 len = OF_getencprop(node, "reg", reg, sizeof(reg)); 464 if (len != 5 * sizeof(pcell_t)) 465 continue; 466 467 /* Allocate and populate devinfo. */ 468 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 469 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 470 free(di, M_DEVBUF); 471 continue; 472 } 473 di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]); 474 di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]); 475 di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]); 476 STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link); 477 } 478 479 return (0); 480 } 481 482 static device_method_t generic_pcie_fdt_methods[] = { 483 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 484 DEVMETHOD(device_attach, pci_host_generic_fdt_attach), 485 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 486 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 487 488 /* pcib interface */ 489 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 490 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 491 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 492 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 493 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 494 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 495 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 496 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 497 498 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 499 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 500 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 501 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 502 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 503 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 504 505 DEVMETHOD_END 506 }; 507 508 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 509 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 510 511 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 0, 0); 512 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, 0, 0);
Cache object: 26484423454fccc7f3065b960571ea12
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