Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/pci/pci_pci.c
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1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/9.0/sys/dev/pci/pci_pci.c 224069 2011-07-15 21:08:58Z jhb $"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pci_private.h> 50 #include <dev/pci/pcib_private.h> 51 52 #include "pcib_if.h" 53 54 static int pcib_probe(device_t dev); 55 static int pcib_suspend(device_t dev); 56 static int pcib_resume(device_t dev); 57 static int pcib_power_for_sleep(device_t pcib, device_t dev, 58 int *pstate); 59 60 static device_method_t pcib_methods[] = { 61 /* Device interface */ 62 DEVMETHOD(device_probe, pcib_probe), 63 DEVMETHOD(device_attach, pcib_attach), 64 DEVMETHOD(device_detach, bus_generic_detach), 65 DEVMETHOD(device_shutdown, bus_generic_shutdown), 66 DEVMETHOD(device_suspend, pcib_suspend), 67 DEVMETHOD(device_resume, pcib_resume), 68 69 /* Bus interface */ 70 DEVMETHOD(bus_print_child, bus_generic_print_child), 71 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 72 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 73 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 74 #ifdef NEW_PCIB 75 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 76 DEVMETHOD(bus_release_resource, pcib_release_resource), 77 #else 78 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 79 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 80 #endif 81 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 82 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 83 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 84 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 85 86 /* pcib interface */ 87 DEVMETHOD(pcib_maxslots, pcib_maxslots), 88 DEVMETHOD(pcib_read_config, pcib_read_config), 89 DEVMETHOD(pcib_write_config, pcib_write_config), 90 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 91 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 92 DEVMETHOD(pcib_release_msi, pcib_release_msi), 93 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 94 DEVMETHOD(pcib_release_msix, pcib_release_msix), 95 DEVMETHOD(pcib_map_msi, pcib_map_msi), 96 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 97 98 { 0, 0 } 99 }; 100 101 static devclass_t pcib_devclass; 102 103 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 104 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 105 106 #ifdef NEW_PCIB 107 /* 108 * XXX Todo: 109 * - properly handle the ISA enable bit. If it is set, we should change 110 * the behavior of the I/O window resource and rman to not allocate the 111 * blocked ranges (upper 768 bytes of each 1K in the first 64k of the 112 * I/O port address space). 113 */ 114 115 /* 116 * Is a resource from a child device sub-allocated from one of our 117 * resource managers? 118 */ 119 static int 120 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 121 { 122 123 switch (type) { 124 case SYS_RES_IOPORT: 125 return (rman_is_region_manager(r, &sc->io.rman)); 126 case SYS_RES_MEMORY: 127 /* Prefetchable resources may live in either memory rman. */ 128 if (rman_get_flags(r) & RF_PREFETCHABLE && 129 rman_is_region_manager(r, &sc->pmem.rman)) 130 return (1); 131 return (rman_is_region_manager(r, &sc->mem.rman)); 132 } 133 return (0); 134 } 135 136 static int 137 pcib_is_window_open(struct pcib_window *pw) 138 { 139 140 return (pw->valid && pw->base < pw->limit); 141 } 142 143 /* 144 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 145 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 146 * when allocating the resource windows and rely on the PCI bus driver 147 * to do this for us. 148 */ 149 static void 150 pcib_activate_window(struct pcib_softc *sc, int type) 151 { 152 153 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 154 } 155 156 static void 157 pcib_write_windows(struct pcib_softc *sc, int mask) 158 { 159 device_t dev; 160 uint32_t val; 161 162 dev = sc->dev; 163 if (sc->io.valid && mask & WIN_IO) { 164 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 165 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 166 pci_write_config(dev, PCIR_IOBASEH_1, 167 sc->io.base >> 16, 2); 168 pci_write_config(dev, PCIR_IOLIMITH_1, 169 sc->io.limit >> 16, 2); 170 } 171 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 172 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 173 } 174 175 if (mask & WIN_MEM) { 176 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 177 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 178 } 179 180 if (sc->pmem.valid && mask & WIN_PMEM) { 181 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 182 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 183 pci_write_config(dev, PCIR_PMBASEH_1, 184 sc->pmem.base >> 32, 4); 185 pci_write_config(dev, PCIR_PMLIMITH_1, 186 sc->pmem.limit >> 32, 4); 187 } 188 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 189 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 190 } 191 } 192 193 static void 194 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 195 int flags, pci_addr_t max_address) 196 { 197 char buf[64]; 198 int error, rid; 199 200 if (max_address != (u_long)max_address) 201 max_address = ~0ul; 202 w->rman.rm_start = 0; 203 w->rman.rm_end = max_address; 204 w->rman.rm_type = RMAN_ARRAY; 205 snprintf(buf, sizeof(buf), "%s %s window", 206 device_get_nameunit(sc->dev), w->name); 207 w->rman.rm_descr = strdup(buf, M_DEVBUF); 208 error = rman_init(&w->rman); 209 if (error) 210 panic("Failed to initialize %s %s rman", 211 device_get_nameunit(sc->dev), w->name); 212 213 if (!pcib_is_window_open(w)) 214 return; 215 216 if (w->base > max_address || w->limit > max_address) { 217 device_printf(sc->dev, 218 "initial %s window has too many bits, ignoring\n", w->name); 219 return; 220 } 221 rid = w->reg; 222 w->res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 223 w->limit - w->base + 1, flags); 224 if (w->res == NULL) { 225 device_printf(sc->dev, 226 "failed to allocate initial %s window: %#jx-%#jx\n", 227 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 228 w->base = max_address; 229 w->limit = 0; 230 pcib_write_windows(sc, w->mask); 231 return; 232 } 233 pcib_activate_window(sc, type); 234 235 error = rman_manage_region(&w->rman, rman_get_start(w->res), 236 rman_get_end(w->res)); 237 if (error) 238 panic("Failed to initialize rman with resource"); 239 } 240 241 /* 242 * Initialize I/O windows. 243 */ 244 static void 245 pcib_probe_windows(struct pcib_softc *sc) 246 { 247 pci_addr_t max; 248 device_t dev; 249 uint32_t val; 250 251 dev = sc->dev; 252 253 /* Determine if the I/O port window is implemented. */ 254 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 255 if (val == 0) { 256 /* 257 * If 'val' is zero, then only 16-bits of I/O space 258 * are supported. 259 */ 260 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 261 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 262 sc->io.valid = 1; 263 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 264 } 265 } else 266 sc->io.valid = 1; 267 268 /* Read the existing I/O port window. */ 269 if (sc->io.valid) { 270 sc->io.reg = PCIR_IOBASEL_1; 271 sc->io.step = 12; 272 sc->io.mask = WIN_IO; 273 sc->io.name = "I/O port"; 274 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 275 sc->io.base = PCI_PPBIOBASE( 276 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 277 sc->io.limit = PCI_PPBIOLIMIT( 278 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 279 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 280 max = 0xffffffff; 281 } else { 282 sc->io.base = PCI_PPBIOBASE(0, val); 283 sc->io.limit = PCI_PPBIOLIMIT(0, 284 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 285 max = 0xffff; 286 } 287 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 288 } 289 290 /* Read the existing memory window. */ 291 sc->mem.valid = 1; 292 sc->mem.reg = PCIR_MEMBASE_1; 293 sc->mem.step = 20; 294 sc->mem.mask = WIN_MEM; 295 sc->mem.name = "memory"; 296 sc->mem.base = PCI_PPBMEMBASE(0, 297 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 298 sc->mem.limit = PCI_PPBMEMLIMIT(0, 299 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 300 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 301 302 /* Determine if the prefetchable memory window is implemented. */ 303 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 304 if (val == 0) { 305 /* 306 * If 'val' is zero, then only 32-bits of memory space 307 * are supported. 308 */ 309 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 310 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 311 sc->pmem.valid = 1; 312 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 313 } 314 } else 315 sc->pmem.valid = 1; 316 317 /* Read the existing prefetchable memory window. */ 318 if (sc->pmem.valid) { 319 sc->pmem.reg = PCIR_PMBASEL_1; 320 sc->pmem.step = 20; 321 sc->pmem.mask = WIN_PMEM; 322 sc->pmem.name = "prefetch"; 323 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 324 sc->pmem.base = PCI_PPBMEMBASE( 325 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 326 sc->pmem.limit = PCI_PPBMEMLIMIT( 327 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 328 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 329 max = 0xffffffffffffffff; 330 } else { 331 sc->pmem.base = PCI_PPBMEMBASE(0, val); 332 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 333 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 334 max = 0xffffffff; 335 } 336 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 337 RF_PREFETCHABLE, max); 338 } 339 } 340 341 #else 342 343 /* 344 * Is the prefetch window open (eg, can we allocate memory in it?) 345 */ 346 static int 347 pcib_is_prefetch_open(struct pcib_softc *sc) 348 { 349 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 350 } 351 352 /* 353 * Is the nonprefetch window open (eg, can we allocate memory in it?) 354 */ 355 static int 356 pcib_is_nonprefetch_open(struct pcib_softc *sc) 357 { 358 return (sc->membase > 0 && sc->membase < sc->memlimit); 359 } 360 361 /* 362 * Is the io window open (eg, can we allocate ports in it?) 363 */ 364 static int 365 pcib_is_io_open(struct pcib_softc *sc) 366 { 367 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 368 } 369 370 /* 371 * Get current I/O decode. 372 */ 373 static void 374 pcib_get_io_decode(struct pcib_softc *sc) 375 { 376 device_t dev; 377 uint32_t iolow; 378 379 dev = sc->dev; 380 381 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 382 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 383 sc->iobase = PCI_PPBIOBASE( 384 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 385 else 386 sc->iobase = PCI_PPBIOBASE(0, iolow); 387 388 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 389 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 390 sc->iolimit = PCI_PPBIOLIMIT( 391 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 392 else 393 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 394 } 395 396 /* 397 * Get current memory decode. 398 */ 399 static void 400 pcib_get_mem_decode(struct pcib_softc *sc) 401 { 402 device_t dev; 403 pci_addr_t pmemlow; 404 405 dev = sc->dev; 406 407 sc->membase = PCI_PPBMEMBASE(0, 408 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 409 sc->memlimit = PCI_PPBMEMLIMIT(0, 410 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 411 412 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 413 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 414 sc->pmembase = PCI_PPBMEMBASE( 415 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 416 else 417 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 418 419 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 420 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 421 sc->pmemlimit = PCI_PPBMEMLIMIT( 422 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 423 else 424 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 425 } 426 427 /* 428 * Restore previous I/O decode. 429 */ 430 static void 431 pcib_set_io_decode(struct pcib_softc *sc) 432 { 433 device_t dev; 434 uint32_t iohi; 435 436 dev = sc->dev; 437 438 iohi = sc->iobase >> 16; 439 if (iohi > 0) 440 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 441 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 442 443 iohi = sc->iolimit >> 16; 444 if (iohi > 0) 445 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 446 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 447 } 448 449 /* 450 * Restore previous memory decode. 451 */ 452 static void 453 pcib_set_mem_decode(struct pcib_softc *sc) 454 { 455 device_t dev; 456 pci_addr_t pmemhi; 457 458 dev = sc->dev; 459 460 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 461 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 462 463 pmemhi = sc->pmembase >> 32; 464 if (pmemhi > 0) 465 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 466 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 467 468 pmemhi = sc->pmemlimit >> 32; 469 if (pmemhi > 0) 470 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 471 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 472 } 473 #endif 474 475 /* 476 * Get current bridge configuration. 477 */ 478 static void 479 pcib_cfg_save(struct pcib_softc *sc) 480 { 481 device_t dev; 482 483 dev = sc->dev; 484 485 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 486 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 487 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 488 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 489 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 490 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 491 #ifndef NEW_PCIB 492 if (sc->command & PCIM_CMD_PORTEN) 493 pcib_get_io_decode(sc); 494 if (sc->command & PCIM_CMD_MEMEN) 495 pcib_get_mem_decode(sc); 496 #endif 497 } 498 499 /* 500 * Restore previous bridge configuration. 501 */ 502 static void 503 pcib_cfg_restore(struct pcib_softc *sc) 504 { 505 device_t dev; 506 507 dev = sc->dev; 508 509 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 510 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 511 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 512 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 513 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 514 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 515 #ifdef NEW_PCIB 516 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 517 #else 518 if (sc->command & PCIM_CMD_PORTEN) 519 pcib_set_io_decode(sc); 520 if (sc->command & PCIM_CMD_MEMEN) 521 pcib_set_mem_decode(sc); 522 #endif 523 } 524 525 /* 526 * Generic device interface 527 */ 528 static int 529 pcib_probe(device_t dev) 530 { 531 if ((pci_get_class(dev) == PCIC_BRIDGE) && 532 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 533 device_set_desc(dev, "PCI-PCI bridge"); 534 return(-10000); 535 } 536 return(ENXIO); 537 } 538 539 void 540 pcib_attach_common(device_t dev) 541 { 542 struct pcib_softc *sc; 543 struct sysctl_ctx_list *sctx; 544 struct sysctl_oid *soid; 545 546 sc = device_get_softc(dev); 547 sc->dev = dev; 548 549 /* 550 * Get current bridge configuration. 551 */ 552 sc->domain = pci_get_domain(dev); 553 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 554 pcib_cfg_save(sc); 555 556 /* 557 * Setup sysctl reporting nodes 558 */ 559 sctx = device_get_sysctl_ctx(dev); 560 soid = device_get_sysctl_tree(dev); 561 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 562 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 563 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 564 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 565 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 566 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 567 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 568 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 569 570 /* 571 * Quirk handling. 572 */ 573 switch (pci_get_devid(dev)) { 574 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 575 { 576 uint8_t supbus; 577 578 supbus = pci_read_config(dev, 0x41, 1); 579 if (supbus != 0xff) { 580 sc->secbus = supbus + 1; 581 sc->subbus = supbus + 1; 582 } 583 break; 584 } 585 586 /* 587 * The i82380FB mobile docking controller is a PCI-PCI bridge, 588 * and it is a subtractive bridge. However, the ProgIf is wrong 589 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 590 * happen. There's also a Toshiba bridge that behaves this 591 * way. 592 */ 593 case 0x124b8086: /* Intel 82380FB Mobile */ 594 case 0x060513d7: /* Toshiba ???? */ 595 sc->flags |= PCIB_SUBTRACTIVE; 596 break; 597 598 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 599 case 0x00dd10de: 600 { 601 char *cp; 602 603 if ((cp = getenv("smbios.planar.maker")) == NULL) 604 break; 605 if (strncmp(cp, "Compal", 6) != 0) { 606 freeenv(cp); 607 break; 608 } 609 freeenv(cp); 610 if ((cp = getenv("smbios.planar.product")) == NULL) 611 break; 612 if (strncmp(cp, "08A0", 4) != 0) { 613 freeenv(cp); 614 break; 615 } 616 freeenv(cp); 617 if (sc->subbus < 0xa) { 618 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 619 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 620 } 621 break; 622 } 623 } 624 625 if (pci_msi_device_blacklisted(dev)) 626 sc->flags |= PCIB_DISABLE_MSI; 627 628 /* 629 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 630 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 631 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 632 * This means they act as if they were subtractively decoding 633 * bridges and pass all transactions. Mark them and real ProgIf 1 634 * parts as subtractive. 635 */ 636 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 637 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 638 sc->flags |= PCIB_SUBTRACTIVE; 639 640 #ifdef NEW_PCIB 641 pcib_probe_windows(sc); 642 #endif 643 if (bootverbose) { 644 device_printf(dev, " domain %d\n", sc->domain); 645 device_printf(dev, " secondary bus %d\n", sc->secbus); 646 device_printf(dev, " subordinate bus %d\n", sc->subbus); 647 #ifdef NEW_PCIB 648 if (pcib_is_window_open(&sc->io)) 649 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 650 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 651 if (pcib_is_window_open(&sc->mem)) 652 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 653 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 654 if (pcib_is_window_open(&sc->pmem)) 655 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 656 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 657 #else 658 if (pcib_is_io_open(sc)) 659 device_printf(dev, " I/O decode 0x%x-0x%x\n", 660 sc->iobase, sc->iolimit); 661 if (pcib_is_nonprefetch_open(sc)) 662 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 663 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 664 if (pcib_is_prefetch_open(sc)) 665 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 666 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 667 #endif 668 else 669 device_printf(dev, " no prefetched decode\n"); 670 if (sc->flags & PCIB_SUBTRACTIVE) 671 device_printf(dev, " Subtractively decoded bridge.\n"); 672 } 673 674 /* 675 * XXX If the secondary bus number is zero, we should assign a bus number 676 * since the BIOS hasn't, then initialise the bridge. A simple 677 * bus_alloc_resource with the a couple of busses seems like the right 678 * approach, but we don't know what busses the BIOS might have already 679 * assigned to other bridges on this bus that probe later than we do. 680 * 681 * If the subordinate bus number is less than the secondary bus number, 682 * we should pick a better value. One sensible alternative would be to 683 * pick 255; the only tradeoff here is that configuration transactions 684 * would be more widely routed than absolutely necessary. We could 685 * then do a walk of the tree later and fix it. 686 */ 687 } 688 689 int 690 pcib_attach(device_t dev) 691 { 692 struct pcib_softc *sc; 693 device_t child; 694 695 pcib_attach_common(dev); 696 sc = device_get_softc(dev); 697 if (sc->secbus != 0) { 698 child = device_add_child(dev, "pci", sc->secbus); 699 if (child != NULL) 700 return(bus_generic_attach(dev)); 701 } 702 703 /* no secondary bus; we should have fixed this */ 704 return(0); 705 } 706 707 int 708 pcib_suspend(device_t dev) 709 { 710 device_t pcib; 711 int dstate, error; 712 713 pcib_cfg_save(device_get_softc(dev)); 714 error = bus_generic_suspend(dev); 715 if (error == 0 && pci_do_power_suspend) { 716 dstate = PCI_POWERSTATE_D3; 717 pcib = device_get_parent(device_get_parent(dev)); 718 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 719 pci_set_powerstate(dev, dstate); 720 } 721 return (error); 722 } 723 724 int 725 pcib_resume(device_t dev) 726 { 727 device_t pcib; 728 729 if (pci_do_power_resume) { 730 pcib = device_get_parent(device_get_parent(dev)); 731 if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0) 732 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 733 } 734 pcib_cfg_restore(device_get_softc(dev)); 735 return (bus_generic_resume(dev)); 736 } 737 738 int 739 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 740 { 741 struct pcib_softc *sc = device_get_softc(dev); 742 743 switch (which) { 744 case PCIB_IVAR_DOMAIN: 745 *result = sc->domain; 746 return(0); 747 case PCIB_IVAR_BUS: 748 *result = sc->secbus; 749 return(0); 750 } 751 return(ENOENT); 752 } 753 754 int 755 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 756 { 757 struct pcib_softc *sc = device_get_softc(dev); 758 759 switch (which) { 760 case PCIB_IVAR_DOMAIN: 761 return(EINVAL); 762 case PCIB_IVAR_BUS: 763 sc->secbus = value; 764 return(0); 765 } 766 return(ENOENT); 767 } 768 769 #ifdef NEW_PCIB 770 /* 771 * Attempt to allocate a resource from the existing resources assigned 772 * to a window. 773 */ 774 static struct resource * 775 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 776 device_t child, int type, int *rid, u_long start, u_long end, u_long count, 777 u_int flags) 778 { 779 struct resource *res; 780 781 if (!pcib_is_window_open(w)) 782 return (NULL); 783 784 res = rman_reserve_resource(&w->rman, start, end, count, 785 flags & ~RF_ACTIVE, child); 786 if (res == NULL) 787 return (NULL); 788 789 if (bootverbose) 790 device_printf(sc->dev, 791 "allocated %s range (%#lx-%#lx) for rid %x of %s\n", 792 w->name, rman_get_start(res), rman_get_end(res), *rid, 793 pcib_child_name(child)); 794 rman_set_rid(res, *rid); 795 796 /* 797 * If the resource should be active, pass that request up the 798 * tree. This assumes the parent drivers can handle 799 * activating sub-allocated resources. 800 */ 801 if (flags & RF_ACTIVE) { 802 if (bus_activate_resource(child, type, *rid, res) != 0) { 803 rman_release_resource(res); 804 return (NULL); 805 } 806 } 807 808 return (res); 809 } 810 811 /* 812 * Attempt to grow a window to make room for a given resource request. 813 * The 'step' parameter is log_2 of the desired I/O window's alignment. 814 */ 815 static int 816 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 817 u_long start, u_long end, u_long count, u_int flags) 818 { 819 u_long align, start_free, end_free, front, back; 820 int error, rid; 821 822 /* 823 * Clamp the desired resource range to the maximum address 824 * this window supports. Reject impossible requests. 825 */ 826 if (!w->valid) 827 return (EINVAL); 828 if (end > w->rman.rm_end) 829 end = w->rman.rm_end; 830 if (start + count - 1 > end || start + count < start) 831 return (EINVAL); 832 833 /* 834 * If there is no resource at all, just try to allocate enough 835 * aligned space for this resource. 836 */ 837 if (w->res == NULL) { 838 if (RF_ALIGNMENT(flags) < w->step) { 839 flags &= ~RF_ALIGNMENT_MASK; 840 flags |= RF_ALIGNMENT_LOG2(w->step); 841 } 842 start &= ~((1ul << w->step) - 1); 843 end |= ((1ul << w->step) - 1); 844 count = roundup2(count, 1ul << w->step); 845 rid = w->reg; 846 w->res = bus_alloc_resource(sc->dev, type, &rid, start, end, 847 count, flags & ~RF_ACTIVE); 848 if (w->res == NULL) { 849 if (bootverbose) 850 device_printf(sc->dev, 851 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n", 852 w->name, start, end, count); 853 return (ENXIO); 854 } 855 if (bootverbose) 856 device_printf(sc->dev, 857 "allocated initial %s window of %#lx-%#lx\n", 858 w->name, rman_get_start(w->res), 859 rman_get_end(w->res)); 860 error = rman_manage_region(&w->rman, rman_get_start(w->res), 861 rman_get_end(w->res)); 862 if (error) { 863 if (bootverbose) 864 device_printf(sc->dev, 865 "failed to add initial %s window to rman\n", 866 w->name); 867 bus_release_resource(sc->dev, type, w->reg, w->res); 868 w->res = NULL; 869 return (error); 870 } 871 pcib_activate_window(sc, type); 872 goto updatewin; 873 } 874 875 /* 876 * See if growing the window would help. Compute the minimum 877 * amount of address space needed on both the front and back 878 * ends of the existing window to satisfy the allocation. 879 * 880 * For each end, build a candidate region adjusting for the 881 * required alignment, etc. If there is a free region at the 882 * edge of the window, grow from the inner edge of the free 883 * region. Otherwise grow from the window boundary. 884 * 885 * XXX: Special case: if w->res is completely empty and the 886 * request size is larger than w->res, we should find the 887 * optimal aligned buffer containing w->res and allocate that. 888 */ 889 if (bootverbose) 890 device_printf(sc->dev, 891 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n", 892 w->name, start, end, count); 893 align = 1ul << RF_ALIGNMENT(flags); 894 if (start < rman_get_start(w->res)) { 895 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 896 0 || start_free != rman_get_start(w->res)) 897 end_free = rman_get_start(w->res) - 1; 898 if (end_free > end) 899 end_free = end; 900 901 /* Move end_free down until it is properly aligned. */ 902 end_free &= ~(align - 1); 903 end_free--; 904 front = end_free - (count - 1); 905 906 /* 907 * The resource would now be allocated at (front, 908 * end_free). Ensure that fits in the (start, end) 909 * bounds. end_free is checked above. If 'front' is 910 * ok, ensure it is properly aligned for this window. 911 * Also check for underflow. 912 */ 913 if (front >= start && front <= end_free) { 914 if (bootverbose) 915 printf("\tfront candidate range: %#lx-%#lx\n", 916 front, end_free); 917 front &= (1ul << w->step) - 1; 918 front = rman_get_start(w->res) - front; 919 } else 920 front = 0; 921 } else 922 front = 0; 923 if (end > rman_get_end(w->res)) { 924 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 925 0 || end_free != rman_get_end(w->res)) 926 start_free = rman_get_end(w->res) + 1; 927 if (start_free < start) 928 start_free = start; 929 930 /* Move start_free up until it is properly aligned. */ 931 start_free = roundup2(start_free, align); 932 back = start_free + count - 1; 933 934 /* 935 * The resource would now be allocated at (start_free, 936 * back). Ensure that fits in the (start, end) 937 * bounds. start_free is checked above. If 'back' is 938 * ok, ensure it is properly aligned for this window. 939 * Also check for overflow. 940 */ 941 if (back <= end && start_free <= back) { 942 if (bootverbose) 943 printf("\tback candidate range: %#lx-%#lx\n", 944 start_free, back); 945 back = roundup2(back + 1, 1ul << w->step) - 1; 946 back -= rman_get_end(w->res); 947 } else 948 back = 0; 949 } else 950 back = 0; 951 952 /* 953 * Try to allocate the smallest needed region first. 954 * If that fails, fall back to the other region. 955 */ 956 error = ENOSPC; 957 while (front != 0 || back != 0) { 958 if (front != 0 && (front <= back || back == 0)) { 959 error = bus_adjust_resource(sc->dev, type, w->res, 960 rman_get_start(w->res) - front, 961 rman_get_end(w->res)); 962 if (error == 0) 963 break; 964 front = 0; 965 } else { 966 error = bus_adjust_resource(sc->dev, type, w->res, 967 rman_get_start(w->res), 968 rman_get_end(w->res) + back); 969 if (error == 0) 970 break; 971 back = 0; 972 } 973 } 974 975 if (error) 976 return (error); 977 if (bootverbose) 978 device_printf(sc->dev, "grew %s window to %#lx-%#lx\n", 979 w->name, rman_get_start(w->res), rman_get_end(w->res)); 980 981 /* Add the newly allocated region to the resource manager. */ 982 if (w->base != rman_get_start(w->res)) { 983 KASSERT(w->limit == rman_get_end(w->res), ("both ends moved")); 984 error = rman_manage_region(&w->rman, rman_get_start(w->res), 985 w->base - 1); 986 } else { 987 KASSERT(w->limit != rman_get_end(w->res), 988 ("neither end moved")); 989 error = rman_manage_region(&w->rman, w->limit + 1, 990 rman_get_end(w->res)); 991 } 992 if (error) { 993 if (bootverbose) 994 device_printf(sc->dev, 995 "failed to expand %s resource manager\n", w->name); 996 bus_adjust_resource(sc->dev, type, w->res, w->base, w->limit); 997 return (error); 998 } 999 1000 updatewin: 1001 /* Save the new window. */ 1002 w->base = rman_get_start(w->res); 1003 w->limit = rman_get_end(w->res); 1004 KASSERT((w->base & ((1ul << w->step) - 1)) == 0, 1005 ("start address is not aligned")); 1006 KASSERT((w->limit & ((1ul << w->step) - 1)) == (1ul << w->step) - 1, 1007 ("end address is not aligned")); 1008 pcib_write_windows(sc, w->mask); 1009 return (0); 1010 } 1011 1012 /* 1013 * We have to trap resource allocation requests and ensure that the bridge 1014 * is set up to, or capable of handling them. 1015 */ 1016 struct resource * 1017 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1018 u_long start, u_long end, u_long count, u_int flags) 1019 { 1020 struct pcib_softc *sc; 1021 struct resource *r; 1022 1023 sc = device_get_softc(dev); 1024 1025 /* 1026 * VGA resources are decoded iff the VGA enable bit is set in 1027 * the bridge control register. VGA resources do not fall into 1028 * the resource windows and are passed up to the parent. 1029 */ 1030 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 1031 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 1032 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 1033 return (bus_generic_alloc_resource(dev, child, type, 1034 rid, start, end, count, flags)); 1035 else 1036 return (NULL); 1037 } 1038 1039 switch (type) { 1040 case SYS_RES_IOPORT: 1041 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 1042 end, count, flags); 1043 if (r != NULL) 1044 break; 1045 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 1046 flags) == 0) 1047 r = pcib_suballoc_resource(sc, &sc->io, child, type, 1048 rid, start, end, count, flags); 1049 break; 1050 case SYS_RES_MEMORY: 1051 /* 1052 * For prefetchable resources, prefer the prefetchable 1053 * memory window, but fall back to the regular memory 1054 * window if that fails. Try both windows before 1055 * attempting to grow a window in case the firmware 1056 * has used a range in the regular memory window to 1057 * map a prefetchable BAR. 1058 */ 1059 if (flags & RF_PREFETCHABLE) { 1060 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 1061 rid, start, end, count, flags); 1062 if (r != NULL) 1063 break; 1064 } 1065 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 1066 start, end, count, flags); 1067 if (r != NULL) 1068 break; 1069 if (flags & RF_PREFETCHABLE) { 1070 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 1071 count, flags) == 0) { 1072 r = pcib_suballoc_resource(sc, &sc->pmem, child, 1073 type, rid, start, end, count, flags); 1074 if (r != NULL) 1075 break; 1076 } 1077 } 1078 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 1079 flags & ~RF_PREFETCHABLE) == 0) 1080 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 1081 rid, start, end, count, flags); 1082 break; 1083 default: 1084 return (bus_generic_alloc_resource(dev, child, type, rid, 1085 start, end, count, flags)); 1086 } 1087 1088 /* 1089 * If attempts to suballocate from the window fail but this is a 1090 * subtractive bridge, pass the request up the tree. 1091 */ 1092 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 1093 return (bus_generic_alloc_resource(dev, child, type, rid, 1094 start, end, count, flags)); 1095 return (r); 1096 } 1097 1098 int 1099 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 1100 u_long start, u_long end) 1101 { 1102 struct pcib_softc *sc; 1103 1104 sc = device_get_softc(bus); 1105 if (pcib_is_resource_managed(sc, type, r)) 1106 return (rman_adjust_resource(r, start, end)); 1107 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 1108 } 1109 1110 int 1111 pcib_release_resource(device_t dev, device_t child, int type, int rid, 1112 struct resource *r) 1113 { 1114 struct pcib_softc *sc; 1115 int error; 1116 1117 sc = device_get_softc(dev); 1118 if (pcib_is_resource_managed(sc, type, r)) { 1119 if (rman_get_flags(r) & RF_ACTIVE) { 1120 error = bus_deactivate_resource(child, type, rid, r); 1121 if (error) 1122 return (error); 1123 } 1124 return (rman_release_resource(r)); 1125 } 1126 return (bus_generic_release_resource(dev, child, type, rid, r)); 1127 } 1128 #else 1129 /* 1130 * We have to trap resource allocation requests and ensure that the bridge 1131 * is set up to, or capable of handling them. 1132 */ 1133 struct resource * 1134 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1135 u_long start, u_long end, u_long count, u_int flags) 1136 { 1137 struct pcib_softc *sc = device_get_softc(dev); 1138 const char *name, *suffix; 1139 int ok; 1140 1141 /* 1142 * Fail the allocation for this range if it's not supported. 1143 */ 1144 name = device_get_nameunit(child); 1145 if (name == NULL) { 1146 name = ""; 1147 suffix = ""; 1148 } else 1149 suffix = " "; 1150 switch (type) { 1151 case SYS_RES_IOPORT: 1152 ok = 0; 1153 if (!pcib_is_io_open(sc)) 1154 break; 1155 ok = (start >= sc->iobase && end <= sc->iolimit); 1156 1157 /* 1158 * Make sure we allow access to VGA I/O addresses when the 1159 * bridge has the "VGA Enable" bit set. 1160 */ 1161 if (!ok && pci_is_vga_ioport_range(start, end)) 1162 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1163 1164 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1165 if (!ok) { 1166 if (start < sc->iobase) 1167 start = sc->iobase; 1168 if (end > sc->iolimit) 1169 end = sc->iolimit; 1170 if (start < end) 1171 ok = 1; 1172 } 1173 } else { 1174 ok = 1; 1175 #if 0 1176 /* 1177 * If we overlap with the subtractive range, then 1178 * pick the upper range to use. 1179 */ 1180 if (start < sc->iolimit && end > sc->iobase) 1181 start = sc->iolimit + 1; 1182 #endif 1183 } 1184 if (end < start) { 1185 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 1186 end, start); 1187 start = 0; 1188 end = 0; 1189 ok = 0; 1190 } 1191 if (!ok) { 1192 device_printf(dev, "%s%srequested unsupported I/O " 1193 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 1194 name, suffix, start, end, sc->iobase, sc->iolimit); 1195 return (NULL); 1196 } 1197 if (bootverbose) 1198 device_printf(dev, 1199 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 1200 name, suffix, start, end); 1201 break; 1202 1203 case SYS_RES_MEMORY: 1204 ok = 0; 1205 if (pcib_is_nonprefetch_open(sc)) 1206 ok = ok || (start >= sc->membase && end <= sc->memlimit); 1207 if (pcib_is_prefetch_open(sc)) 1208 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 1209 1210 /* 1211 * Make sure we allow access to VGA memory addresses when the 1212 * bridge has the "VGA Enable" bit set. 1213 */ 1214 if (!ok && pci_is_vga_memory_range(start, end)) 1215 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1216 1217 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1218 if (!ok) { 1219 ok = 1; 1220 if (flags & RF_PREFETCHABLE) { 1221 if (pcib_is_prefetch_open(sc)) { 1222 if (start < sc->pmembase) 1223 start = sc->pmembase; 1224 if (end > sc->pmemlimit) 1225 end = sc->pmemlimit; 1226 } else { 1227 ok = 0; 1228 } 1229 } else { /* non-prefetchable */ 1230 if (pcib_is_nonprefetch_open(sc)) { 1231 if (start < sc->membase) 1232 start = sc->membase; 1233 if (end > sc->memlimit) 1234 end = sc->memlimit; 1235 } else { 1236 ok = 0; 1237 } 1238 } 1239 } 1240 } else if (!ok) { 1241 ok = 1; /* subtractive bridge: always ok */ 1242 #if 0 1243 if (pcib_is_nonprefetch_open(sc)) { 1244 if (start < sc->memlimit && end > sc->membase) 1245 start = sc->memlimit + 1; 1246 } 1247 if (pcib_is_prefetch_open(sc)) { 1248 if (start < sc->pmemlimit && end > sc->pmembase) 1249 start = sc->pmemlimit + 1; 1250 } 1251 #endif 1252 } 1253 if (end < start) { 1254 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 1255 end, start); 1256 start = 0; 1257 end = 0; 1258 ok = 0; 1259 } 1260 if (!ok && bootverbose) 1261 device_printf(dev, 1262 "%s%srequested unsupported memory range %#lx-%#lx " 1263 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 1264 name, suffix, start, end, 1265 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 1266 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1267 if (!ok) 1268 return (NULL); 1269 if (bootverbose) 1270 device_printf(dev,"%s%srequested memory range " 1271 "0x%lx-0x%lx: good\n", 1272 name, suffix, start, end); 1273 break; 1274 1275 default: 1276 break; 1277 } 1278 /* 1279 * Bridge is OK decoding this resource, so pass it up. 1280 */ 1281 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 1282 count, flags)); 1283 } 1284 #endif 1285 1286 /* 1287 * PCIB interface. 1288 */ 1289 int 1290 pcib_maxslots(device_t dev) 1291 { 1292 return(PCI_SLOTMAX); 1293 } 1294 1295 /* 1296 * Since we are a child of a PCI bus, its parent must support the pcib interface. 1297 */ 1298 uint32_t 1299 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 1300 { 1301 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 1302 } 1303 1304 void 1305 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 1306 { 1307 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 1308 } 1309 1310 /* 1311 * Route an interrupt across a PCI bridge. 1312 */ 1313 int 1314 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 1315 { 1316 device_t bus; 1317 int parent_intpin; 1318 int intnum; 1319 1320 /* 1321 * 1322 * The PCI standard defines a swizzle of the child-side device/intpin to 1323 * the parent-side intpin as follows. 1324 * 1325 * device = device on child bus 1326 * child_intpin = intpin on child bus slot (0-3) 1327 * parent_intpin = intpin on parent bus slot (0-3) 1328 * 1329 * parent_intpin = (device + child_intpin) % 4 1330 */ 1331 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 1332 1333 /* 1334 * Our parent is a PCI bus. Its parent must export the pcib interface 1335 * which includes the ability to route interrupts. 1336 */ 1337 bus = device_get_parent(pcib); 1338 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 1339 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 1340 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 1341 pci_get_slot(dev), 'A' + pin - 1, intnum); 1342 } 1343 return(intnum); 1344 } 1345 1346 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 1347 int 1348 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 1349 { 1350 struct pcib_softc *sc = device_get_softc(pcib); 1351 device_t bus; 1352 1353 if (sc->flags & PCIB_DISABLE_MSI) 1354 return (ENXIO); 1355 bus = device_get_parent(pcib); 1356 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 1357 irqs)); 1358 } 1359 1360 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 1361 int 1362 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 1363 { 1364 device_t bus; 1365 1366 bus = device_get_parent(pcib); 1367 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 1368 } 1369 1370 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 1371 int 1372 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 1373 { 1374 struct pcib_softc *sc = device_get_softc(pcib); 1375 device_t bus; 1376 1377 if (sc->flags & PCIB_DISABLE_MSI) 1378 return (ENXIO); 1379 bus = device_get_parent(pcib); 1380 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 1381 } 1382 1383 /* Pass request to release an MSI-X message up to the parent bridge. */ 1384 int 1385 pcib_release_msix(device_t pcib, device_t dev, int irq) 1386 { 1387 device_t bus; 1388 1389 bus = device_get_parent(pcib); 1390 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 1391 } 1392 1393 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 1394 int 1395 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 1396 uint32_t *data) 1397 { 1398 device_t bus; 1399 int error; 1400 1401 bus = device_get_parent(pcib); 1402 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 1403 if (error) 1404 return (error); 1405 1406 pci_ht_map_msi(pcib, *addr); 1407 return (0); 1408 } 1409 1410 /* Pass request for device power state up to parent bridge. */ 1411 int 1412 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 1413 { 1414 device_t bus; 1415 1416 bus = device_get_parent(pcib); 1417 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 1418 }
Cache object: 209ab5d5a526adfa54fff496ad127a21
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