FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pciconf.c
1 /* $NetBSD: pciconf.c,v 1.23 2004/03/17 20:27:57 scw Exp $ */
2
3 /*
4 * Copyright 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Allen Briggs for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37 /*
38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/).
39 */
40
41 /*
42 * To do:
43 * - Perform all data structure allocation dynamically, don't have
44 * statically-sized arrays ("oops, you lose because you have too
45 * many slots filled!")
46 * - Do this in 2 passes, with an MD hook to control the behavior:
47 * (1) Configure the bus (possibly including expansion
48 * ROMs.
49 * (2) Another pass to disable expansion ROMs if they're
50 * mapped (since you're not supposed to leave them
51 * mapped when you're not using them).
52 * This would facilitate MD code executing the expansion ROMs
53 * if necessary (possibly with an x86 emulator) to configure
54 * devices (e.g. VGA cards).
55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration
56 * information around & be able to reconfigure on the fly
57 * - Deal with segments (See IA64 System Abstraction Layer)
58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode)
59 * - Deal with ISA/VGA/VGA palette snooping
60 * - Deal with device capabilities on bridges
61 * - Worry about changing a bridge to/from transparency
62 * From thorpej (05/25/01)
63 * - Try to handle devices that are already configured (perhaps using that
64 * as a hint to where we put other devices)
65 */
66
67 #include <sys/cdefs.h>
68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.23 2004/03/17 20:27:57 scw Exp $");
69
70 #include "opt_pci.h"
71
72 #include <sys/param.h>
73 #include <sys/extent.h>
74 #include <sys/queue.h>
75 #include <sys/systm.h>
76 #include <sys/malloc.h>
77
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pciconf.h>
80 #include <dev/pci/pcidevs.h>
81 #include <dev/pci/pccbbreg.h>
82
83 int pci_conf_debug = 0;
84
85 #if !defined(MIN)
86 #define MIN(a,b) (((a)<(b))?(a):(b))
87 #define MAX(a,b) (((a)>(b))?(a):(b))
88 #endif
89
90 /* per-bus constants. */
91 #define MAX_CONF_DEV 32 /* Arbitrary */
92 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */
93 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */
94
95 struct _s_pciconf_bus_t; /* Forward declaration */
96
97 typedef struct _s_pciconf_dev_t {
98 int ipin;
99 int iline;
100 int min_gnt;
101 int max_lat;
102 int enable;
103 pcitag_t tag;
104 pci_chipset_tag_t pc;
105 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */
106 } pciconf_dev_t;
107
108 typedef struct _s_pciconf_win_t {
109 pciconf_dev_t *dev;
110 int reg; /* 0 for busses */
111 int align;
112 int prefetch;
113 u_int64_t size;
114 u_int64_t address;
115 } pciconf_win_t;
116
117 typedef struct _s_pciconf_bus_t {
118 int busno;
119 int next_busno;
120 int last_busno;
121 int max_mingnt;
122 int min_maxlat;
123 int cacheline_size;
124 int prefetch;
125 int fast_b2b;
126 int freq_66;
127 int def_ltim;
128 int max_ltim;
129 int bandwidth_used;
130 int swiz;
131 int io_32bit;
132 int pmem_64bit;
133
134 int ndevs;
135 pciconf_dev_t device[MAX_CONF_DEV];
136
137 /* These should be sorted in order of decreasing size */
138 int nmemwin;
139 pciconf_win_t pcimemwin[MAX_CONF_MEM];
140 int niowin;
141 pciconf_win_t pciiowin[MAX_CONF_IO];
142
143 bus_size_t io_total;
144 bus_size_t mem_total;
145 bus_size_t pmem_total;
146
147 struct extent *ioext;
148 struct extent *memext;
149 struct extent *pmemext;
150
151 pci_chipset_tag_t pc;
152 struct _s_pciconf_bus_t *parent_bus;
153 } pciconf_bus_t;
154
155 static int probe_bus(pciconf_bus_t *);
156 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *);
157 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int);
158 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int);
159 static int setup_iowins(pciconf_bus_t *);
160 static int setup_memwins(pciconf_bus_t *);
161 static int configure_bridge(pciconf_dev_t *);
162 static int configure_bus(pciconf_bus_t *);
163 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int);
164 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t);
165 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t);
166 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int);
167
168 static void print_tag(pci_chipset_tag_t, pcitag_t);
169
170 static void
171 print_tag(pci_chipset_tag_t pc, pcitag_t tag)
172 {
173 int bus, dev, func;
174
175 pci_decompose_tag(pc, tag, &bus, &dev, &func);
176 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func);
177 }
178
179 /************************************************************************/
180 /************************************************************************/
181 /*********************** Bus probing routines ***********************/
182 /************************************************************************/
183 /************************************************************************/
184 static pciconf_win_t *
185 get_io_desc(pciconf_bus_t *pb, bus_size_t size)
186 {
187 int i, n;
188
189 n = pb->niowin;
190 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--)
191 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */
192 return &pb->pciiowin[i];
193 }
194
195 static pciconf_win_t *
196 get_mem_desc(pciconf_bus_t *pb, bus_size_t size)
197 {
198 int i, n;
199
200 n = pb->nmemwin;
201 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--)
202 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */
203 return &pb->pcimemwin[i];
204 }
205
206 /*
207 * Set up bus common stuff, then loop over devices & functions.
208 * If we find something, call pci_do_device_query()).
209 */
210 static int
211 probe_bus(pciconf_bus_t *pb)
212 {
213 int device, maxdevs;
214 #ifdef __PCI_BUS_DEVORDER
215 char devs[32];
216 int i;
217 #endif
218
219 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno);
220 pb->ndevs = 0;
221 pb->niowin = 0;
222 pb->nmemwin = 0;
223 pb->freq_66 = 1;
224 #ifdef PCICONF_NO_FAST_B2B
225 pb->fast_b2b = 0;
226 #else
227 pb->fast_b2b = 1;
228 #endif
229 pb->prefetch = 1;
230 pb->max_mingnt = 0; /* we are looking for the maximum */
231 pb->min_maxlat = 0x100; /* we are looking for the minimum */
232 pb->bandwidth_used = 0;
233
234 #ifdef __PCI_BUS_DEVORDER
235 pci_bus_devorder(pb->pc, pb->busno, devs);
236 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) {
237 #else
238 for (device = 0; device < maxdevs; device++) {
239 #endif
240 pcitag_t tag;
241 pcireg_t id, bhlcr;
242 int function, nfunction;
243 int confmode;
244
245 tag = pci_make_tag(pb->pc, pb->busno, device, 0);
246 if (pci_conf_debug) {
247 print_tag(pb->pc, tag);
248 }
249 id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
250
251 if (pci_conf_debug) {
252 printf("id=%x: Vendor=%x, Product=%x\n",
253 id, PCI_VENDOR(id),PCI_PRODUCT(id));
254 }
255 /* Invalid vendor ID value? */
256 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
257 continue;
258
259 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
260 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1;
261 for (function = 0 ; function < nfunction ; function++) {
262 tag = pci_make_tag(pb->pc, pb->busno, device, function);
263 id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
264 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
265 continue;
266 if (pb->ndevs+1 < MAX_CONF_DEV) {
267 if (pci_conf_debug) {
268 print_tag(pb->pc, tag);
269 printf("Found dev 0x%04x 0x%04x -- "
270 "really probing.\n",
271 PCI_VENDOR(id), PCI_PRODUCT(id));
272 }
273 #ifdef __HAVE_PCI_CONF_HOOK
274 confmode = pci_conf_hook(pb->pc, pb->busno,
275 device, function, id);
276 if (confmode == 0)
277 continue;
278 #else
279 /*
280 * Don't enable expansion ROMS -- some cards
281 * share address decoders between the EXPROM
282 * and PCI memory space, and enabling the ROM
283 * when not needed will cause all sorts of
284 * lossage.
285 */
286 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM;
287 #endif
288 if (pci_do_device_query(pb, tag, device,
289 function, confmode))
290 return -1;
291 pb->ndevs++;
292 }
293 }
294 }
295 return 0;
296 }
297
298 static void
299 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb)
300 {
301 pb->busno = parent->next_busno;
302 pb->next_busno = pb->busno + 1;
303 }
304
305 static void
306 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub)
307 {
308 pcireg_t busreg;
309
310 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT;
311 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT;
312 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
313 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg);
314 }
315
316 static pciconf_bus_t *
317 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev)
318 {
319 pciconf_bus_t *pb;
320 pcireg_t io, pmem;
321 pciconf_win_t *pi, *pm;
322
323 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT);
324 if (!pb)
325 panic("Unable to allocate memory for PCI configuration.");
326
327 pb->cacheline_size = parent->cacheline_size;
328 pb->parent_bus = parent;
329 alloc_busno(parent, pb);
330
331 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff);
332
333 pb->swiz = parent->swiz + dev;
334
335 pb->ioext = NULL;
336 pb->memext = NULL;
337 pb->pmemext = NULL;
338 pb->pc = parent->pc;
339 pb->io_total = pb->mem_total = pb->pmem_total = 0;
340
341 pb->io_32bit = 0;
342 if (parent->io_32bit) {
343 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG);
344 if (PCI_BRIDGE_IO_32BITS(io)) {
345 pb->io_32bit = 1;
346 }
347 }
348
349 pb->pmem_64bit = 0;
350 if (parent->pmem_64bit) {
351 pmem = pci_conf_read(parent->pc, pd->tag,
352 PCI_BRIDGE_PREFETCHMEM_REG);
353 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) {
354 pb->pmem_64bit = 1;
355 }
356 }
357
358 if (probe_bus(pb)) {
359 printf("Failed to probe bus %d\n", pb->busno);
360 goto err;
361 }
362
363 /* We have found all subordinate busses now, reprogram busreg. */
364 pb->last_busno = pb->next_busno-1;
365 parent->next_busno = pb->next_busno;
366 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno,
367 pb->last_busno);
368 if (pci_conf_debug)
369 printf("PCI bus bridge (parent %d) covers busses %d-%d\n",
370 parent->busno, pb->busno, pb->last_busno);
371
372 if (pb->io_total > 0) {
373 if (parent->niowin >= MAX_CONF_IO) {
374 printf("pciconf: too many I/O windows\n");
375 goto err;
376 }
377 pb->io_total |= 0xfff; /* Round up */
378 pi = get_io_desc(parent, pb->io_total);
379 pi->dev = pd;
380 pi->reg = 0;
381 pi->size = pb->io_total;
382 pi->align = 0x1000; /* 4K alignment */
383 pi->prefetch = 0;
384 parent->niowin++;
385 parent->io_total += pb->io_total;
386 }
387
388 if (pb->mem_total > 0) {
389 if (parent->nmemwin >= MAX_CONF_MEM) {
390 printf("pciconf: too many MEM windows\n");
391 goto err;
392 }
393 pb->mem_total |= 0xfffff; /* Round up */
394 pm = get_mem_desc(parent, pb->mem_total);
395 pm->dev = pd;
396 pm->reg = 0;
397 pm->size = pb->mem_total;
398 pm->align = 0x100000; /* 1M alignment */
399 pm->prefetch = 0;
400 parent->nmemwin++;
401 parent->mem_total += pb->mem_total;
402 }
403
404 if (pb->pmem_total > 0) {
405 if (parent->nmemwin >= MAX_CONF_MEM) {
406 printf("pciconf: too many MEM windows\n");
407 goto err;
408 }
409 pb->pmem_total |= 0xfffff; /* Round up */
410 pm = get_mem_desc(parent, pb->pmem_total);
411 pm->dev = pd;
412 pm->reg = 0;
413 pm->size = pb->pmem_total;
414 pm->align = 0x100000; /* 1M alignment */
415 pm->prefetch = 1;
416 parent->nmemwin++;
417 parent->pmem_total += pb->pmem_total;
418 }
419
420 return pb;
421 err:
422 free(pb, M_DEVBUF);
423 return NULL;
424 }
425
426 static int
427 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode)
428 {
429 pciconf_dev_t *pd;
430 pciconf_win_t *pi, *pm;
431 pcireg_t class, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg;
432 u_int64_t size;
433 int br, width, reg_start, reg_end;
434
435 pd = &pb->device[pb->ndevs];
436 pd->pc = pb->pc;
437 pd->tag = tag;
438 pd->ppb = NULL;
439 pd->enable = mode;
440
441 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG);
442
443 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG);
444
445 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) {
446 cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
447 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
448 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd);
449 } else if (pci_conf_debug) {
450 print_tag(pb->pc, tag);
451 printf("device is a bridge; not clearing enables\n");
452 }
453
454 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0)
455 pb->fast_b2b = 0;
456
457 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0)
458 pb->freq_66 = 0;
459
460 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
461 switch (PCI_HDRTYPE_TYPE(bhlc)) {
462 case PCI_HDRTYPE_DEVICE:
463 reg_start = PCI_MAPREG_START;
464 reg_end = PCI_MAPREG_END;
465 break;
466 case PCI_HDRTYPE_PPB:
467 pd->ppb = query_bus(pb, pd, dev);
468 if (pd->ppb == NULL)
469 return -1;
470 return 0;
471 case PCI_HDRTYPE_PCB:
472 reg_start = PCI_MAPREG_START;
473 reg_end = PCI_MAPREG_PCB_END;
474
475 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM);
476 busreg = (busreg & 0xff000000) |
477 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT |
478 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT |
479 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
480 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg);
481
482 pb->next_busno ++;
483 break;
484 default:
485 return -1;
486 }
487
488 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG);
489 pd->ipin = PCI_INTERRUPT_PIN(icr);
490 pd->iline = PCI_INTERRUPT_LINE(icr);
491 pd->min_gnt = PCI_MIN_GNT(icr);
492 pd->max_lat = PCI_MAX_LAT(icr);
493 if (pd->iline || pd->ipin) {
494 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz,
495 &pd->iline);
496 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
497 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT);
498 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr);
499 }
500
501 if (pd->min_gnt != 0 || pd->max_lat != 0) {
502 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt)
503 pb->max_mingnt = pd->min_gnt;
504
505 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat)
506 pb->min_maxlat = pd->max_lat;
507
508 pb->bandwidth_used += pd->min_gnt * 4000000 /
509 (pd->min_gnt + pd->max_lat);
510 }
511
512 width = 4;
513 for (br = reg_start; br < reg_end; br += width) {
514 #if 0
515 /* XXX Should only ignore if IDE not in legacy mode? */
516 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE &&
517 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
518 break;
519 }
520 #endif
521 bar = pci_conf_read(pb->pc, tag, br);
522 pci_conf_write(pb->pc, tag, br, 0xffffffff);
523 mask = pci_conf_read(pb->pc, tag, br);
524 pci_conf_write(pb->pc, tag, br, bar);
525 width = 4;
526
527 if ( (mode & PCI_CONF_MAP_IO)
528 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) {
529 /*
530 * Upper 16 bits must be one. Devices may hardwire
531 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203.
532 */
533 mask |= 0xffff0000;
534
535 size = PCI_MAPREG_IO_SIZE(mask);
536 if (size == 0) {
537 if (pci_conf_debug) {
538 print_tag(pb->pc, tag);
539 printf("I/O BAR 0x%x is void\n", br);
540 }
541 continue;
542 }
543
544 if (pb->niowin >= MAX_CONF_IO) {
545 printf("pciconf: too many I/O windows\n");
546 return -1;
547 }
548
549 pi = get_io_desc(pb, size);
550 pi->dev = pd;
551 pi->reg = br;
552 pi->size = (u_int64_t) size;
553 pi->align = 4;
554 pi->prefetch = 0;
555 if (pci_conf_debug) {
556 print_tag(pb->pc, tag);
557 printf("Register 0x%x, I/O size %" PRIu64 "\n",
558 br, pi->size);
559 }
560 pb->niowin++;
561 pb->io_total += size;
562 } else if ((mode & PCI_CONF_MAP_MEM)
563 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) {
564 switch (PCI_MAPREG_MEM_TYPE(mask)) {
565 case PCI_MAPREG_MEM_TYPE_32BIT:
566 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
567 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask);
568 break;
569 case PCI_MAPREG_MEM_TYPE_64BIT:
570 bar64 = pci_conf_read(pb->pc, tag, br + 4);
571 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff);
572 mask64 = pci_conf_read(pb->pc, tag, br + 4);
573 pci_conf_write(pb->pc, tag, br + 4, bar64);
574 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE(
575 (((u_int64_t) mask64) << 32) | mask);
576 width = 8;
577 break;
578 default:
579 print_tag(pb->pc, tag);
580 printf("reserved mapping type 0x%x\n",
581 PCI_MAPREG_MEM_TYPE(mask));
582 continue;
583 }
584
585 if (size == 0) {
586 if (pci_conf_debug) {
587 print_tag(pb->pc, tag);
588 printf("MEM%d BAR 0x%x is void\n",
589 PCI_MAPREG_MEM_TYPE(mask) ==
590 PCI_MAPREG_MEM_TYPE_64BIT ?
591 64 : 32, br);
592 }
593 continue;
594 } else {
595 if (pci_conf_debug) {
596 print_tag(pb->pc, tag);
597 printf("MEM%d BAR 0x%x has size %lx\n",
598 PCI_MAPREG_MEM_TYPE(mask) ==
599 PCI_MAPREG_MEM_TYPE_64BIT ?
600 64 : 32, br, (unsigned long)size);
601 }
602 }
603
604 if (pb->nmemwin >= MAX_CONF_MEM) {
605 printf("pciconf: too many memory windows\n");
606 return -1;
607 }
608
609 pm = get_mem_desc(pb, size);
610 pm->dev = pd;
611 pm->reg = br;
612 pm->size = size;
613 pm->align = 4;
614 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask);
615 if (pci_conf_debug) {
616 print_tag(pb->pc, tag);
617 printf("Register 0x%x, memory size %"
618 PRIu64 "\n", br, pm->size);
619 }
620 pb->nmemwin++;
621 if (pm->prefetch) {
622 pb->pmem_total += size;
623 } else {
624 pb->mem_total += size;
625 }
626 }
627 }
628
629 if (mode & PCI_CONF_MAP_ROM) {
630 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
631 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe);
632 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
633 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar);
634
635 if (mask != 0 && mask != 0xffffffff) {
636 if (pb->nmemwin >= MAX_CONF_MEM) {
637 printf("pciconf: too many memory windows\n");
638 return -1;
639 }
640 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask);
641
642 pm = get_mem_desc(pb, size);
643 pm->dev = pd;
644 pm->reg = PCI_MAPREG_ROM;
645 pm->size = size;
646 pm->align = 4;
647 pm->prefetch = 1;
648 if (pci_conf_debug) {
649 print_tag(pb->pc, tag);
650 printf("Expansion ROM memory size %"
651 PRIu64 "\n", pm->size);
652 }
653 pb->nmemwin++;
654 pb->pmem_total += size;
655 }
656 } else {
657 /* Ensure ROM is disabled */
658 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
659 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe);
660 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
661 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM,
662 bar & ~PCI_MAPREG_ROM_ENABLE);
663 }
664
665 return 0;
666 }
667
668 /************************************************************************/
669 /************************************************************************/
670 /******************** Bus configuration routines ********************/
671 /************************************************************************/
672 /************************************************************************/
673 static u_int64_t
674 pci_allocate_range(struct extent *ex, u_int64_t amt, int align)
675 {
676 int r;
677 u_long addr;
678
679 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr);
680 if (r) {
681 addr = (u_long) -1;
682 printf("extent_alloc(%p, %" PRIu64 ", %d) returned %d\n",
683 ex, amt, align, r);
684 extent_print(ex);
685 }
686 return (pcireg_t) addr;
687 }
688
689 static int
690 setup_iowins(pciconf_bus_t *pb)
691 {
692 pciconf_win_t *pi;
693 pciconf_dev_t *pd;
694
695 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) {
696 if (pi->size == 0)
697 continue;
698
699 pd = pi->dev;
700 pi->address = pci_allocate_range(pb->ioext, pi->size,
701 pi->align);
702 if (pi->address == -1) {
703 print_tag(pd->pc, pd->tag);
704 printf("Failed to allocate PCI I/O space (%"
705 PRIu64 " req)\n", pi->size);
706 return -1;
707 }
708 if (!pb->io_32bit && pi->address > 0xFFFF) {
709 pi->address = 0;
710 pd->enable = 0;
711 }
712 if (pd->ppb && pi->reg == 0) {
713 pd->ppb->ioext = extent_create("pciconf", pi->address,
714 pi->address + pi->size, M_DEVBUF, NULL, 0,
715 EX_NOWAIT);
716 if (pd->ppb->ioext == NULL) {
717 print_tag(pd->pc, pd->tag);
718 printf("Failed to alloc I/O ext. for bus %d\n",
719 pd->ppb->busno);
720 return -1;
721 }
722 continue;
723 }
724 pd->enable |= PCI_CONF_ENABLE_IO;
725 if (pci_conf_debug) {
726 print_tag(pd->pc, pd->tag);
727 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64
728 " (reg %x)\n", pi->size, pi->address, pi->reg);
729 }
730 pci_conf_write(pd->pc, pd->tag, pi->reg,
731 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO);
732 }
733 return 0;
734 }
735
736 static int
737 setup_memwins(pciconf_bus_t *pb)
738 {
739 pciconf_win_t *pm;
740 pciconf_dev_t *pd;
741 pcireg_t base;
742 struct extent *ex;
743
744 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) {
745 if (pm->size == 0)
746 continue;
747
748 pd = pm->dev;
749 ex = (pm->prefetch) ? pb->pmemext : pb->memext;
750 pm->address = pci_allocate_range(ex, pm->size, pm->align);
751 if (pm->address == -1) {
752 print_tag(pd->pc, pd->tag);
753 printf(
754 "Failed to allocate PCI memory space (%" PRIu64
755 " req)\n", pm->size);
756 return -1;
757 }
758 if (pd->ppb && pm->reg == 0) {
759 ex = extent_create("pciconf", pm->address,
760 pm->address + pm->size, M_DEVBUF, NULL, 0,
761 EX_NOWAIT);
762 if (ex == NULL) {
763 print_tag(pd->pc, pd->tag);
764 printf("Failed to alloc MEM ext. for bus %d\n",
765 pd->ppb->busno);
766 return -1;
767 }
768 if (pm->prefetch) {
769 pd->ppb->pmemext = ex;
770 } else {
771 pd->ppb->memext = ex;
772 }
773 continue;
774 }
775 if (pm->prefetch && !pb->pmem_64bit &&
776 pm->address > 0xFFFFFFFFULL) {
777 pm->address = 0;
778 pd->enable = 0;
779 } else {
780 pd->enable |= PCI_CONF_ENABLE_MEM;
781 }
782 if (pm->reg != PCI_MAPREG_ROM) {
783 if (pci_conf_debug) {
784 print_tag(pd->pc, pd->tag);
785 printf(
786 "Putting %" PRIu64 " MEM bytes @ %#"
787 PRIx64 " (reg %x)\n", pm->size,
788 pm->address, pm->reg);
789 }
790 base = pci_conf_read(pd->pc, pd->tag, pm->reg);
791 base = PCI_MAPREG_MEM_ADDR(pm->address) |
792 PCI_MAPREG_MEM_TYPE(base);
793 pci_conf_write(pd->pc, pd->tag, pm->reg, base);
794 if (PCI_MAPREG_MEM_TYPE(base) ==
795 PCI_MAPREG_MEM_TYPE_64BIT) {
796 base = (pcireg_t)
797 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32);
798 pci_conf_write(pd->pc, pd->tag, pm->reg + 4,
799 base);
800 }
801 }
802 }
803 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) {
804 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) {
805 pd = pm->dev;
806 if (pci_conf_debug) {
807 print_tag(pd->pc, pd->tag);
808 printf(
809 "Putting %" PRIu64 " ROM bytes @ %#"
810 PRIx64 " (reg %x)\n", pm->size,
811 pm->address, pm->reg);
812 }
813 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE);
814 pci_conf_write(pd->pc, pd->tag, pm->reg, base);
815 }
816 }
817 return 0;
818 }
819
820 /*
821 * Configure I/O, memory, and prefetcable memory spaces, then make
822 * a call to configure_bus().
823 */
824 static int
825 configure_bridge(pciconf_dev_t *pd)
826 {
827 unsigned long io_base, io_limit, mem_base, mem_limit;
828 pciconf_bus_t *pb;
829 pcireg_t io, iohigh, mem, cmd;
830 int rv;
831
832 pb = pd->ppb;
833 /* Configure I/O base & limit*/
834 if (pb->ioext) {
835 io_base = pb->ioext->ex_start;
836 io_limit = pb->ioext->ex_end;
837 } else {
838 io_base = 0x1000; /* 4K */
839 io_limit = 0x0000;
840 }
841 if (pb->io_32bit) {
842 iohigh =
843 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) |
844 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT);
845 } else {
846 if (io_limit > 0xFFFF) {
847 printf("Bus %d bridge does not support 32-bit I/O. ",
848 pb->busno);
849 printf("Disabling I/O accesses\n");
850 io_base = 0x1000; /* 4K */
851 io_limit = 0x0000;
852 }
853 iohigh = 0;
854 }
855 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) &
856 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT);
857 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK)
858 << PCI_BRIDGE_STATIO_IOBASE_SHIFT);
859 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK)
860 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT);
861 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io);
862 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh);
863
864 /* Configure mem base & limit */
865 if (pb->memext) {
866 mem_base = pb->memext->ex_start;
867 mem_limit = pb->memext->ex_end;
868 } else {
869 mem_base = 0x100000; /* 1M */
870 mem_limit = 0x000000;
871 }
872 #if ULONG_MAX > 0xffffffff
873 if (mem_limit > 0xFFFFFFFFULL) {
874 printf("Bus %d bridge MEM range out of range. ", pb->busno);
875 printf("Disabling MEM accesses\n");
876 mem_base = 0x100000; /* 1M */
877 mem_limit = 0x000000;
878 }
879 #endif
880 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK)
881 << PCI_BRIDGE_MEMORY_BASE_SHIFT);
882 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK)
883 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT);
884 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem);
885
886 /* Configure prefetchable mem base & limit */
887 if (pb->pmemext) {
888 mem_base = pb->pmemext->ex_start;
889 mem_limit = pb->pmemext->ex_end;
890 } else {
891 mem_base = 0x100000; /* 1M */
892 mem_limit = 0x000000;
893 }
894 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG);
895 #if ULONG_MAX > 0xffffffff
896 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) {
897 printf("Bus %d bridge does not support 64-bit PMEM. ",
898 pb->busno);
899 printf("Disabling prefetchable-MEM accesses\n");
900 mem_base = 0x100000; /* 1M */
901 mem_limit = 0x000000;
902 }
903 #endif
904 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK)
905 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT);
906 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK)
907 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT);
908 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem);
909 /*
910 * XXX -- 64-bit systems need a lot more than just this...
911 */
912 if (sizeof(u_long) > 4) {
913 mem_base = (int64_t) mem_base >> 32;
914 mem_limit = (int64_t) mem_limit >> 32;
915 }
916 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG,
917 mem_base & 0xffffffff);
918 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG,
919 mem_limit & 0xffffffff);
920
921 rv = configure_bus(pb);
922
923 if (pb->ioext)
924 extent_destroy(pb->ioext);
925 if (pb->memext)
926 extent_destroy(pb->memext);
927 if (pb->pmemext)
928 extent_destroy(pb->pmemext);
929 if (rv == 0) {
930 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG);
931 cmd &= PCI_BRIDGE_CONTROL_MASK;
932 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR)
933 << PCI_BRIDGE_CONTROL_SHIFT;
934 if (pb->fast_b2b) {
935 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B
936 << PCI_BRIDGE_CONTROL_SHIFT;
937 }
938 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd);
939 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
940 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
941 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd);
942 }
943
944 return rv;
945 }
946
947 /*
948 * Calculate latency values, allocate I/O and MEM segments, then set them
949 * up. If a PCI-PCI bridge is found, configure the bridge separately,
950 * which will cause a recursive call back here.
951 */
952 static int
953 configure_bus(pciconf_bus_t *pb)
954 {
955 pciconf_dev_t *pd;
956 int def_ltim, max_ltim, band, bus_mhz;
957
958 if (pb->ndevs == 0) {
959 if (pci_conf_debug)
960 printf("PCI bus %d - no devices\n", pb->busno);
961 return (1);
962 }
963 bus_mhz = pb->freq_66 ? 66 : 33;
964 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */
965 band = 40000000; /* 0.25us cycles/sec */
966 if (band < pb->bandwidth_used) {
967 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n",
968 pb->busno);
969 def_ltim = -1;
970 } else {
971 def_ltim = (band - pb->bandwidth_used) / pb->ndevs;
972 if (def_ltim > pb->min_maxlat)
973 def_ltim = pb->min_maxlat;
974 def_ltim = def_ltim * bus_mhz / 4;
975 }
976 def_ltim = (def_ltim + 7) & ~7;
977 max_ltim = (max_ltim + 7) & ~7;
978
979 pb->def_ltim = MIN( def_ltim, 255 );
980 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 );
981
982 /*
983 * Now we have what we need to initialize the devices.
984 * It would probably be better if we could allocate all of these
985 * for all busses at once, but "not right now". First, get a list
986 * of free memory ranges from the m.d. system.
987 */
988 if (setup_iowins(pb) || setup_memwins(pb)) {
989 printf("PCI bus configuration failed: ");
990 printf("unable to assign all I/O and memory ranges.");
991 return -1;
992 }
993
994 /*
995 * Configure the latency for the devices, and enable them.
996 */
997 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) {
998 pcireg_t cmd, class, misc;
999 int ltim;
1000
1001 if (pci_conf_debug) {
1002 print_tag(pd->pc, pd->tag);
1003 printf("Configuring device.\n");
1004 }
1005 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
1006 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
1007 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
1008 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE;
1009 if (pb->fast_b2b)
1010 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
1011 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
1012 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) {
1013 if (pd->enable & PCI_CONF_ENABLE_IO)
1014 cmd |= PCI_COMMAND_IO_ENABLE;
1015 if (pd->enable & PCI_CONF_ENABLE_MEM)
1016 cmd |= PCI_COMMAND_MEM_ENABLE;
1017 if (pd->enable & PCI_CONF_ENABLE_BM)
1018 cmd |= PCI_COMMAND_MASTER_ENABLE;
1019 ltim = pd->min_gnt * bus_mhz / 4;
1020 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim);
1021 } else {
1022 cmd |= PCI_COMMAND_MASTER_ENABLE;
1023 ltim = MIN (pb->def_ltim, pb->max_ltim);
1024 }
1025 if (!(pd->enable)) {
1026 print_tag(pd->pc, pd->tag);
1027 printf("Disabled due to lack of resources.\n");
1028 cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
1029 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
1030 }
1031 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd);
1032
1033 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
1034 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
1035 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT;
1036 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) <<
1037 PCI_CACHELINE_SHIFT;
1038 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc);
1039
1040 if (pd->ppb) {
1041 if (configure_bridge(pd) < 0)
1042 return -1;
1043 continue;
1044 }
1045 }
1046
1047 if (pci_conf_debug) {
1048 printf("PCI bus %d configured\n", pb->busno);
1049 }
1050
1051 return 0;
1052 }
1053
1054 /*
1055 * Let's configure the PCI bus.
1056 * This consists of basically scanning for all existing devices,
1057 * identifying their needs, and then making another pass over them
1058 * to set:
1059 * 1. I/O addresses
1060 * 2. Memory addresses (Prefetchable and not)
1061 * 3. PCI command register
1062 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test),
1063 * Header type, Latency timer, Cache line size) register
1064 *
1065 * The command register is set to enable fast back-to-back transactions
1066 * if the host bridge says it can handle it. We also configure
1067 * Master Enable, SERR enable, parity enable, and (if this is not a
1068 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices
1069 * will not report some I/O space.
1070 *
1071 * The latency is computed to be a "fair share" of the bus bandwidth.
1072 * The bus bandwidth variable is initialized to the number of PCI cycles
1073 * in one second. The number of cycles taken for one transaction by each
1074 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth.
1075 * Care is taken to ensure that the latency timer won't be set such that
1076 * it would exceed the critical time for any device.
1077 *
1078 * This is complicated somewhat due to the presence of bridges. PCI-PCI
1079 * bridges are probed and configured recursively.
1080 */
1081 int
1082 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext,
1083 struct extent *memext, struct extent *pmemext, int firstbus,
1084 int cacheline_size)
1085 {
1086 pciconf_bus_t *pb;
1087 int rv;
1088
1089 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT);
1090 pb->busno = firstbus;
1091 pb->next_busno = pb->busno + 1;
1092 pb->last_busno = 255;
1093 pb->cacheline_size = cacheline_size;
1094 pb->parent_bus = NULL;
1095 pb->swiz = 0;
1096 pb->io_32bit = 1;
1097 pb->pmem_64bit = 0;
1098 pb->ioext = ioext;
1099 pb->memext = memext;
1100 if (pmemext == NULL) {
1101 pb->pmemext = memext;
1102 } else {
1103 pb->pmemext = pmemext;
1104 }
1105 pb->pc = pc;
1106 pb->io_total = pb->mem_total = pb->pmem_total = 0;
1107
1108 rv = probe_bus(pb);
1109 pb->last_busno = pb->next_busno-1;
1110 if (rv == 0) {
1111 rv = configure_bus(pb);
1112 }
1113
1114 /*
1115 * All done!
1116 */
1117 free(pb, M_DEVBUF);
1118 return rv;
1119 }
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