1 /* $NetBSD: pciide_cmd_reg.h,v 1.13 2003/10/05 17:48:49 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 1998 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 /*
34 * Registers definitions for CMD Technologies's PCI 064x IDE controllers.
35 * Available from http://www.cmd.com/
36 */
37
38 /* Interesting revision of the 0646 */
39 #define CMD0646U2_REV 0x05
40 #define CMD0646U_REV 0x03
41
42 /* Configuration (RO) */
43 #define CMD_CONF 0x50
44 #define CMD_CONF_REV_MASK 0x03 /* 0640/3/6 only */
45 #define CMD_CONF_DRV0_INTR 0x04
46 #define CMD_CONF_DEVID 0x18 /* 0640/3/6 only */
47 #define CMD_CONF_VESAPRT 0x20 /* 0640/3/6 only */
48 #define CMD_CONF_DSA1 0x40
49 #define CMD_CONF_DSA0 0x80 /* 0640/3/6 only */
50
51 /* Control register (RW) */
52 #define CMD_CTRL 0x51
53 #define CMD_CTRL_HR_FIFO 0x01 /* 0640/3/6 only */
54 #define CMD_CTRL_HW_FIFO 0x02 /* 0640/3/6 only */
55 #define CMD_CTRL_DEVSEL 0x04
56 #define CMD_CTRL_2PORT 0x08
57 #define CMD_CTRL_PAR 0x10 /* 0640/3/6 only */
58 #define CMD_CTRL_HW_HLD 0x20 /* 0640/3/6 only */
59 #define CMD_CTRL_DRV0_RAHEAD 0x40
60 #define CMD_CTRL_DRV1_RAHEAD 0x80
61
62 /*
63 * data read/write timing registers . 0640 uses the same for drive 0 and 1
64 * on the secondary channel
65 */
66 #define CMD_DATA_TIM(chan, drive) \
67 (((chan) == 0) ? \
68 ((drive) == 0) ? 0x54: 0x56 \
69 : \
70 ((drive) == 0) ? 0x58 : 0x5b)
71
72 /* secondary channel status and addr timings */
73 #define CMD_ARTTIM23 0x57
74 #define CMD_ARTTIM23_IRQ 0x10
75 #define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d))
76
77 /* DMA master read mode select */
78 #define CMD_DMA_MODE 0x71
79 #define CMD_DMA_MASK 0x03
80 #define CMD_DMA 0x00
81 #define CMD_DMA_MULTIPLE 0x01
82 #define CMD_DMA_LINE 0x03
83 /* the followings bits are only for 0646U/646U2/648/649 */
84 #define CMD_DMA_IRQ(chan) (0x4 << (chan))
85 #define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan))
86 #define CMD_DMA_RST 0x40
87
88 /* the followings are only for 0646U/646U2/648/649 */
89 /* busmaster control/status register */
90 #define CMD_BICSR 0x79
91 #define CMD_BICSR_80(chan) (0x01 << (chan))
92 /* Ultra/DMA timings reg */
93 #define CMD_UDMATIM(channel) (0x73 + (8 * (channel)))
94 #define CMD_UDMATIM_UDMA(drive) (0x01 << (drive))
95 #define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
96 #define CMD_UDMATIM_TIM_MASK 0x3
97 #define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
98 static const int8_t cmd0646_9_tim_udma[] __attribute__((__unused__)) =
99 {0x03, 0x02, 0x01, 0x02, 0x01, 0x00};
100
101 /*
102 * timings values for the 0643/6/8/9
103 * for all dma_mode we have to have
104 * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
105 */
106 static const int8_t cmd0643_9_data_tim_pio[] __attribute__((__unused__)) =
107 {0xA9, 0x57, 0x44, 0x32, 0x3F};
108 static const int8_t cmd0643_9_data_tim_dma[] __attribute__((__unused__)) =
109 {0x87, 0x32, 0x3F};
Cache object: c0968ac7443b324ff2c7bd757df401d3
|