Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pcireg.h
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1 /* $NetBSD: pcireg.h,v 1.45 2004/02/04 06:58:24 soren Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46 #define PCI_ID_REG 0x00 47 48 typedef u_int16_t pci_vendor_id_t; 49 typedef u_int16_t pci_product_id_t; 50 51 #define PCI_VENDOR_SHIFT 0 52 #define PCI_VENDOR_MASK 0xffff 53 #define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56 #define PCI_PRODUCT_SHIFT 16 57 #define PCI_PRODUCT_MASK 0xffff 58 #define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61 #define PCI_ID_CODE(vid,pid) \ 62 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 63 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 64 65 /* 66 * Command and status register. 67 */ 68 #define PCI_COMMAND_STATUS_REG 0x04 69 #define PCI_COMMAND_SHIFT 0 70 #define PCI_COMMAND_MASK 0xffff 71 #define PCI_STATUS_SHIFT 16 72 #define PCI_STATUS_MASK 0xffff 73 74 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 75 ((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \ 76 (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) \ 77 78 #define PCI_COMMAND_IO_ENABLE 0x00000001 79 #define PCI_COMMAND_MEM_ENABLE 0x00000002 80 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 81 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 82 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 83 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 84 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 85 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 86 #define PCI_COMMAND_SERR_ENABLE 0x00000100 87 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 88 89 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 90 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 91 #define PCI_STATUS_UDF_SUPPORT 0x00400000 92 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 93 #define PCI_STATUS_PARITY_ERROR 0x01000000 94 #define PCI_STATUS_DEVSEL_FAST 0x00000000 95 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 96 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 97 #define PCI_STATUS_DEVSEL_MASK 0x06000000 98 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 99 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 100 #define PCI_STATUS_MASTER_ABORT 0x20000000 101 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 102 #define PCI_STATUS_PARITY_DETECT 0x80000000 103 104 /* 105 * PCI Class and Revision Register; defines type and revision of device. 106 */ 107 #define PCI_CLASS_REG 0x08 108 109 typedef u_int8_t pci_class_t; 110 typedef u_int8_t pci_subclass_t; 111 typedef u_int8_t pci_interface_t; 112 typedef u_int8_t pci_revision_t; 113 114 #define PCI_CLASS_SHIFT 24 115 #define PCI_CLASS_MASK 0xff 116 #define PCI_CLASS(cr) \ 117 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 118 119 #define PCI_SUBCLASS_SHIFT 16 120 #define PCI_SUBCLASS_MASK 0xff 121 #define PCI_SUBCLASS(cr) \ 122 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 123 124 #define PCI_INTERFACE_SHIFT 8 125 #define PCI_INTERFACE_MASK 0xff 126 #define PCI_INTERFACE(cr) \ 127 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 128 129 #define PCI_REVISION_SHIFT 0 130 #define PCI_REVISION_MASK 0xff 131 #define PCI_REVISION(cr) \ 132 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 133 134 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 135 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 136 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 137 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 138 139 /* base classes */ 140 #define PCI_CLASS_PREHISTORIC 0x00 141 #define PCI_CLASS_MASS_STORAGE 0x01 142 #define PCI_CLASS_NETWORK 0x02 143 #define PCI_CLASS_DISPLAY 0x03 144 #define PCI_CLASS_MULTIMEDIA 0x04 145 #define PCI_CLASS_MEMORY 0x05 146 #define PCI_CLASS_BRIDGE 0x06 147 #define PCI_CLASS_COMMUNICATIONS 0x07 148 #define PCI_CLASS_SYSTEM 0x08 149 #define PCI_CLASS_INPUT 0x09 150 #define PCI_CLASS_DOCK 0x0a 151 #define PCI_CLASS_PROCESSOR 0x0b 152 #define PCI_CLASS_SERIALBUS 0x0c 153 #define PCI_CLASS_WIRELESS 0x0d 154 #define PCI_CLASS_I2O 0x0e 155 #define PCI_CLASS_SATCOM 0x0f 156 #define PCI_CLASS_CRYPTO 0x10 157 #define PCI_CLASS_DASP 0x11 158 #define PCI_CLASS_UNDEFINED 0xff 159 160 /* 0x00 prehistoric subclasses */ 161 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 162 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 163 164 /* 0x01 mass storage subclasses */ 165 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 166 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 167 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 168 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 169 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 170 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 171 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 172 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 173 174 /* 0x02 network subclasses */ 175 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 176 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 177 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 178 #define PCI_SUBCLASS_NETWORK_ATM 0x03 179 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 180 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 181 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 182 #define PCI_SUBCLASS_NETWORK_MISC 0x80 183 184 /* 0x03 display subclasses */ 185 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 186 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 187 #define PCI_SUBCLASS_DISPLAY_3D 0x02 188 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 189 190 /* 0x04 multimedia subclasses */ 191 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 192 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 193 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 194 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 195 196 /* 0x05 memory subclasses */ 197 #define PCI_SUBCLASS_MEMORY_RAM 0x00 198 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 199 #define PCI_SUBCLASS_MEMORY_MISC 0x80 200 201 /* 0x06 bridge subclasses */ 202 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 203 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 204 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 205 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 206 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 207 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 208 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 209 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 210 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 211 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 212 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 213 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 214 215 /* 0x07 communications subclasses */ 216 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 217 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 218 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 219 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 220 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 221 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 222 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 223 224 /* 0x08 system subclasses */ 225 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 226 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 227 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 228 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 229 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 230 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 231 232 /* 0x09 input subclasses */ 233 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 234 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 235 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 236 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 237 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 238 #define PCI_SUBCLASS_INPUT_MISC 0x80 239 240 /* 0x0a dock subclasses */ 241 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 242 #define PCI_SUBCLASS_DOCK_MISC 0x80 243 244 /* 0x0b processor subclasses */ 245 #define PCI_SUBCLASS_PROCESSOR_386 0x00 246 #define PCI_SUBCLASS_PROCESSOR_486 0x01 247 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 248 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 249 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 250 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 251 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 252 253 /* 0x0c serial bus subclasses */ 254 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 255 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 256 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 257 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 258 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 259 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 260 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 261 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 262 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 263 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 264 265 /* 0x0d wireless subclasses */ 266 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 267 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 268 #define PCI_SUBCLASS_WIRELESS_RF 0x10 269 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 270 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 271 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 272 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 273 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 274 275 /* 0x0e I2O (Intelligent I/O) subclasses */ 276 #define PCI_SUBCLASS_I2O_STANDARD 0x00 277 278 /* 0x0f satellite communication subclasses */ 279 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 280 #define PCI_SUBCLASS_SATCOM_TV 0x01 281 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 282 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 283 #define PCI_SUBCLASS_SATCOM_DATA 0x04 284 285 /* 0x10 encryption/decryption subclasses */ 286 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 287 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 288 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 289 290 /* 0x11 data acquisition and signal processing subclasses */ 291 #define PCI_SUBCLASS_DASP_DPIO 0x00 292 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 293 #define PCI_SUBCLASS_DASP_SYNC 0x10 294 #define PCI_SUBCLASS_DASP_MGMT 0x20 295 #define PCI_SUBCLASS_DASP_MISC 0x80 296 297 /* 298 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 299 */ 300 #define PCI_BHLC_REG 0x0c 301 302 #define PCI_BIST_SHIFT 24 303 #define PCI_BIST_MASK 0xff 304 #define PCI_BIST(bhlcr) \ 305 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 306 307 #define PCI_HDRTYPE_SHIFT 16 308 #define PCI_HDRTYPE_MASK 0xff 309 #define PCI_HDRTYPE(bhlcr) \ 310 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 311 312 #define PCI_HDRTYPE_TYPE(bhlcr) \ 313 (PCI_HDRTYPE(bhlcr) & 0x7f) 314 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 315 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 316 317 #define PCI_LATTIMER_SHIFT 8 318 #define PCI_LATTIMER_MASK 0xff 319 #define PCI_LATTIMER(bhlcr) \ 320 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 321 322 #define PCI_CACHELINE_SHIFT 0 323 #define PCI_CACHELINE_MASK 0xff 324 #define PCI_CACHELINE(bhlcr) \ 325 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 326 327 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 328 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 329 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 330 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 331 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 332 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 333 334 /* 335 * PCI header type 336 */ 337 #define PCI_HDRTYPE_DEVICE 0 338 #define PCI_HDRTYPE_PPB 1 339 #define PCI_HDRTYPE_PCB 2 340 341 /* 342 * Mapping registers 343 */ 344 #define PCI_MAPREG_START 0x10 345 #define PCI_MAPREG_END 0x28 346 #define PCI_MAPREG_ROM 0x30 347 #define PCI_MAPREG_PPB_END 0x18 348 #define PCI_MAPREG_PCB_END 0x14 349 350 #define PCI_MAPREG_TYPE(mr) \ 351 ((mr) & PCI_MAPREG_TYPE_MASK) 352 #define PCI_MAPREG_TYPE_MASK 0x00000001 353 354 #define PCI_MAPREG_TYPE_MEM 0x00000000 355 #define PCI_MAPREG_TYPE_IO 0x00000001 356 #define PCI_MAPREG_ROM_ENABLE 0x00000001 357 358 #define PCI_MAPREG_MEM_TYPE(mr) \ 359 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 360 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 361 362 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 363 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 364 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 365 366 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 367 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 368 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 369 370 #define PCI_MAPREG_MEM_ADDR(mr) \ 371 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 372 #define PCI_MAPREG_MEM_SIZE(mr) \ 373 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 374 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 375 376 #define PCI_MAPREG_MEM64_ADDR(mr) \ 377 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 378 #define PCI_MAPREG_MEM64_SIZE(mr) \ 379 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 380 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 381 382 #define PCI_MAPREG_IO_ADDR(mr) \ 383 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 384 #define PCI_MAPREG_IO_SIZE(mr) \ 385 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 386 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 387 388 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 389 (-(size)) 390 391 #define PCI_MAPREG_NUM(offset) \ 392 (((unsigned)(offset)-PCI_MAPREG_START)/4) 393 394 395 /* 396 * Cardbus CIS pointer (PCI rev. 2.1) 397 */ 398 #define PCI_CARDBUS_CIS_REG 0x28 399 400 /* 401 * Subsystem identification register; contains a vendor ID and a device ID. 402 * Types/macros for PCI_ID_REG apply. 403 * (PCI rev. 2.1) 404 */ 405 #define PCI_SUBSYS_ID_REG 0x2c 406 407 /* 408 * Capabilities link list (PCI rev. 2.2) 409 */ 410 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 411 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 412 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 413 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 414 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 415 416 #define PCI_CAP_RESERVED0 0x00 417 #define PCI_CAP_PWRMGMT 0x01 418 #define PCI_CAP_AGP 0x02 419 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 420 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 421 #define PCI_CAP_VPD 0x03 422 #define PCI_CAP_SLOTID 0x04 423 #define PCI_CAP_MSI 0x05 424 #define PCI_CAP_CPCI_HOTSWAP 0x06 425 #define PCI_CAP_PCIX 0x07 426 #define PCI_CAP_LDT 0x08 427 #define PCI_CAP_VENDSPEC 0x09 428 #define PCI_CAP_DEBUGPORT 0x0a 429 #define PCI_CAP_CPCI_RSRCCTL 0x0b 430 #define PCI_CAP_HOTPLUG 0x0c 431 #define PCI_CAP_AGP8 0x0e 432 #define PCI_CAP_SECURE 0x0f 433 #define PCI_CAP_PCIEXPRESS 0x10 434 #define PCI_CAP_MSIX 0x11 435 436 /* 437 * Vital Product Data; access via capability pointer (PCI rev 2.2). 438 */ 439 #define PCI_VPD_ADDRESS_MASK 0x7fff 440 #define PCI_VPD_ADDRESS_SHIFT 16 441 #define PCI_VPD_ADDRESS(ofs) \ 442 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 443 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 444 #define PCI_VPD_OPFLAG 0x80000000 445 446 /* 447 * Power Management Capability; access via capability pointer. 448 */ 449 450 /* Power Management Capability Register */ 451 #define PCI_PMCR 0x02 452 #define PCI_PMCR_D1SUPP 0x0200 453 #define PCI_PMCR_D2SUPP 0x0400 454 /* Power Management Control Status Register */ 455 #define PCI_PMCSR 0x04 456 #define PCI_PMCSR_STATE_MASK 0x03 457 #define PCI_PMCSR_STATE_D0 0x00 458 #define PCI_PMCSR_STATE_D1 0x01 459 #define PCI_PMCSR_STATE_D2 0x02 460 #define PCI_PMCSR_STATE_D3 0x03 461 462 /* 463 * PCI-X capability. 464 */ 465 466 /* 467 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 468 * word at the capability; the lower 16 bits are the capability ID and 469 * next capability pointer). 470 * 471 * Since we always read PCI config space in 32-bit words, we define these 472 * as 32-bit values, offset and shifted appropriately. Make sure you perform 473 * the appropriate R/M/W cycles! 474 */ 475 #define PCI_PCIX_CMD 0x00 476 #define PCI_PCIX_CMD_PERR_RECOVER 0x00010000 477 #define PCI_PCIX_CMD_RELAXED_ORDER 0x00020000 478 #define PCI_PCIX_CMD_BYTECNT_MASK 0x000c0000 479 #define PCI_PCIX_CMD_BYTECNT_SHIFT 18 480 #define PCI_PCIX_CMD_BCNT_512 0x00000000 481 #define PCI_PCIX_CMD_BCNT_1024 0x00040000 482 #define PCI_PCIX_CMD_BCNT_2048 0x00080000 483 #define PCI_PCIX_CMD_BCNT_4096 0x000c0000 484 #define PCI_PCIX_CMD_SPLTRANS_MASK 0x00700000 485 #define PCI_PCIX_CMD_SPLTRANS_1 0x00000000 486 #define PCI_PCIX_CMD_SPLTRANS_2 0x00100000 487 #define PCI_PCIX_CMD_SPLTRANS_3 0x00200000 488 #define PCI_PCIX_CMD_SPLTRANS_4 0x00300000 489 #define PCI_PCIX_CMD_SPLTRANS_8 0x00400000 490 #define PCI_PCIX_CMD_SPLTRANS_12 0x00500000 491 #define PCI_PCIX_CMD_SPLTRANS_16 0x00600000 492 #define PCI_PCIX_CMD_SPLTRANS_32 0x00700000 493 494 /* 495 * Status. 32 bits at offset 4. 496 */ 497 #define PCI_PCIX_STATUS 0x04 498 #define PCI_PCIX_STATUS_FN_MASK 0x00000007 499 #define PCI_PCIX_STATUS_DEV_MASK 0x000000f8 500 #define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00 501 #define PCI_PCIX_STATUS_64BIT 0x00010000 502 #define PCI_PCIX_STATUS_133 0x00020000 503 #define PCI_PCIX_STATUS_SPLDISC 0x00040000 504 #define PCI_PCIX_STATUS_SPLUNEX 0x00080000 505 #define PCI_PCIX_STATUS_DEVCPLX 0x00100000 506 #define PCI_PCIX_STATUS_MAXB_MASK 0x00600000 507 #define PCI_PCIX_STATUS_MAXB_SHIFT 21 508 #define PCI_PCIX_STATUS_MAXB_512 0x00000000 509 #define PCI_PCIX_STATUS_MAXB_1024 0x00200000 510 #define PCI_PCIX_STATUS_MAXB_2048 0x00400000 511 #define PCI_PCIX_STATUS_MAXB_4096 0x00600000 512 #define PCI_PCIX_STATUS_MAXST_MASK 0x03800000 513 #define PCI_PCIX_STATUS_MAXST_1 0x00000000 514 #define PCI_PCIX_STATUS_MAXST_2 0x00800000 515 #define PCI_PCIX_STATUS_MAXST_3 0x01000000 516 #define PCI_PCIX_STATUS_MAXST_4 0x01800000 517 #define PCI_PCIX_STATUS_MAXST_8 0x02000000 518 #define PCI_PCIX_STATUS_MAXST_12 0x02800000 519 #define PCI_PCIX_STATUS_MAXST_16 0x03000000 520 #define PCI_PCIX_STATUS_MAXST_32 0x03800000 521 #define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000 522 #define PCI_PCIX_STATUS_MAXRS_1K 0x00000000 523 #define PCI_PCIX_STATUS_MAXRS_2K 0x04000000 524 #define PCI_PCIX_STATUS_MAXRS_4K 0x08000000 525 #define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000 526 #define PCI_PCIX_STATUS_MAXRS_16K 0x10000000 527 #define PCI_PCIX_STATUS_MAXRS_32K 0x14000000 528 #define PCI_PCIX_STATUS_MAXRS_64K 0x18000000 529 #define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000 530 #define PCI_PCIX_STATUS_SCERR 0x20000000 531 532 533 /* 534 * Interrupt Configuration Register; contains interrupt pin and line. 535 */ 536 #define PCI_INTERRUPT_REG 0x3c 537 538 typedef u_int8_t pci_intr_latency_t; 539 typedef u_int8_t pci_intr_grant_t; 540 typedef u_int8_t pci_intr_pin_t; 541 typedef u_int8_t pci_intr_line_t; 542 543 #define PCI_MAX_LAT_SHIFT 24 544 #define PCI_MAX_LAT_MASK 0xff 545 #define PCI_MAX_LAT(icr) \ 546 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 547 548 #define PCI_MIN_GNT_SHIFT 16 549 #define PCI_MIN_GNT_MASK 0xff 550 #define PCI_MIN_GNT(icr) \ 551 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 552 553 #define PCI_INTERRUPT_GRANT_SHIFT 24 554 #define PCI_INTERRUPT_GRANT_MASK 0xff 555 #define PCI_INTERRUPT_GRANT(icr) \ 556 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 557 558 #define PCI_INTERRUPT_LATENCY_SHIFT 16 559 #define PCI_INTERRUPT_LATENCY_MASK 0xff 560 #define PCI_INTERRUPT_LATENCY(icr) \ 561 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 562 563 #define PCI_INTERRUPT_PIN_SHIFT 8 564 #define PCI_INTERRUPT_PIN_MASK 0xff 565 #define PCI_INTERRUPT_PIN(icr) \ 566 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 567 568 #define PCI_INTERRUPT_LINE_SHIFT 0 569 #define PCI_INTERRUPT_LINE_MASK 0xff 570 #define PCI_INTERRUPT_LINE(icr) \ 571 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 572 573 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 574 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 575 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 576 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 577 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 578 579 #define PCI_INTERRUPT_PIN_NONE 0x00 580 #define PCI_INTERRUPT_PIN_A 0x01 581 #define PCI_INTERRUPT_PIN_B 0x02 582 #define PCI_INTERRUPT_PIN_C 0x03 583 #define PCI_INTERRUPT_PIN_D 0x04 584 #define PCI_INTERRUPT_PIN_MAX 0x04 585 586 /* Header Type 1 (Bridge) configuration registers */ 587 #define PCI_BRIDGE_BUS_REG 0x18 588 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 589 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 590 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 591 592 #define PCI_BRIDGE_STATIO_REG 0x1C 593 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 594 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 595 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 596 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 597 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 598 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 599 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 600 601 #define PCI_BRIDGE_MEMORY_REG 0x20 602 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 603 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 604 #define PCI_BRIDGE_MEMORY_BASE_MASK 0xffff 605 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0xffff 606 607 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 608 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 609 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 610 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0xffff 611 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0xffff 612 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 613 614 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 615 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 616 617 #define PCI_BRIDGE_IOHIGH_REG 0x30 618 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 619 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 620 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 621 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 622 623 #define PCI_BRIDGE_CONTROL_REG 0x3C 624 #define PCI_BRIDGE_CONTROL_SHIFT 16 625 #define PCI_BRIDGE_CONTROL_MASK 0xffff 626 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 627 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 628 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 629 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 630 /* Reserved (1 << 4) */ 631 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 632 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 633 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 634 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 635 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 636 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 637 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 638 /* Reserved (1 << 12) - (1 << 15) */ 639 640 /* 641 * Vital Product Data resource tags. 642 */ 643 struct pci_vpd_smallres { 644 uint8_t vpdres_byte0; /* length of data + tag */ 645 /* Actual data. */ 646 } __attribute__((__packed__)); 647 648 struct pci_vpd_largeres { 649 uint8_t vpdres_byte0; 650 uint8_t vpdres_len_lsb; /* length of data only */ 651 uint8_t vpdres_len_msb; 652 /* Actual data. */ 653 } __attribute__((__packed__)); 654 655 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 656 657 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 658 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 659 660 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 661 662 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 663 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 664 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 665 666 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 667 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 668 669 struct pci_vpd { 670 uint8_t vpd_key0; 671 uint8_t vpd_key1; 672 uint8_t vpd_len; /* length of data only */ 673 /* Actual data. */ 674 } __attribute__((__packed__)); 675 676 /* 677 * Recommended VPD fields: 678 * 679 * PN Part number of assembly 680 * FN FRU part number 681 * EC EC level of assembly 682 * MN Manufacture ID 683 * SN Serial Number 684 * 685 * Conditionally recommended VPD fields: 686 * 687 * LI Load ID 688 * RL ROM Level 689 * RM Alterable ROM Level 690 * NA Network Address 691 * DD Device Driver Level 692 * DG Diagnostic Level 693 * LL Loadable Microcode Level 694 * VI Vendor ID/Device ID 695 * FU Function Number 696 * SI Subsystem Vendor ID/Subsystem ID 697 * 698 * Additional VPD fields: 699 * 700 * Z0-ZZ User/Product Specific 701 */ 702 703 /* 704 * Threshold below which 32bit PCI DMA needs bouncing. 705 */ 706 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 707 708 #endif /* _DEV_PCI_PCIREG_H_ */
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