The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pcivar.h

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    1 /*      $NetBSD: pcivar.h,v 1.59 2003/08/15 07:17:21 itojun Exp $       */
    2 
    3 /*
    4  * Copyright (c) 1996, 1997 Christopher G. Demetriou.  All rights reserved.
    5  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Charles M. Hannum.
   18  * 4. The name of the author may not be used to endorse or promote products
   19  *    derived from this software without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #ifndef _DEV_PCI_PCIVAR_H_
   34 #define _DEV_PCI_PCIVAR_H_
   35 
   36 /*
   37  * Definitions for PCI autoconfiguration.
   38  *
   39  * This file describes types and functions which are used for PCI
   40  * configuration.  Some of this information is machine-specific, and is
   41  * provided by pci_machdep.h.
   42  */
   43 
   44 #include <sys/device.h>
   45 #include <machine/bus.h>
   46 #include <dev/pci/pcireg.h>
   47 
   48 /*
   49  * Structures and definitions needed by the machine-dependent header.
   50  */
   51 typedef u_int32_t pcireg_t;             /* configuration space register XXX */
   52 struct pcibus_attach_args;
   53 struct pci_softc;
   54 
   55 #ifdef _KERNEL
   56 /*
   57  * Machine-dependent definitions.
   58  */
   59 #include <machine/pci_machdep.h>
   60 
   61 /*
   62  * PCI bus attach arguments.
   63  */
   64 struct pcibus_attach_args {
   65         char            *pba_busname;   /* XXX should be common */
   66         bus_space_tag_t pba_iot;        /* pci i/o space tag */
   67         bus_space_tag_t pba_memt;       /* pci mem space tag */
   68         bus_dma_tag_t pba_dmat;         /* DMA tag */
   69         bus_dma_tag_t pba_dmat64;       /* DMA tag */
   70         pci_chipset_tag_t pba_pc;
   71         int             pba_flags;      /* flags; see below */
   72 
   73         int             pba_bus;        /* PCI bus number */
   74 
   75         /*
   76          * Pointer to the pcitag of our parent bridge.  If there is no
   77          * parent bridge, then we assume we are a root bus.
   78          */
   79         pcitag_t        *pba_bridgetag;
   80 
   81         /*
   82          * Interrupt swizzling information.  These fields
   83          * are only used by secondary busses.
   84          */
   85         u_int           pba_intrswiz;   /* how to swizzle pins */
   86         pcitag_t        pba_intrtag;    /* intr. appears to come from here */
   87 };
   88 
   89 /*
   90  * PCI device attach arguments.
   91  */
   92 struct pci_attach_args {
   93         bus_space_tag_t pa_iot;         /* pci i/o space tag */
   94         bus_space_tag_t pa_memt;        /* pci mem space tag */
   95         bus_dma_tag_t pa_dmat;          /* DMA tag */
   96         bus_dma_tag_t pa_dmat64;        /* DMA tag */
   97         pci_chipset_tag_t pa_pc;
   98         int             pa_flags;       /* flags; see below */
   99 
  100         u_int           pa_bus;
  101         u_int           pa_device;
  102         u_int           pa_function;
  103         pcitag_t        pa_tag;
  104         pcireg_t        pa_id, pa_class;
  105 
  106         /*
  107          * Interrupt information.
  108          *
  109          * "Intrline" is used on systems whose firmware puts
  110          * the right routing data into the line register in
  111          * configuration space.  The rest are used on systems
  112          * that do not.
  113          */
  114         u_int           pa_intrswiz;    /* how to swizzle pins if ppb */
  115         pcitag_t        pa_intrtag;     /* intr. appears to come from here */
  116         pci_intr_pin_t  pa_intrpin;     /* intr. appears on this pin */
  117         pci_intr_line_t pa_intrline;    /* intr. routing information */
  118         pci_intr_pin_t  pa_rawintrpin;  /* unswizzled pin */
  119 };
  120 
  121 /*
  122  * Flags given in the bus and device attachment args.
  123  */
  124 #define PCI_FLAGS_IO_ENABLED    0x01            /* I/O space is enabled */
  125 #define PCI_FLAGS_MEM_ENABLED   0x02            /* memory space is enabled */
  126 #define PCI_FLAGS_MRL_OKAY      0x04            /* Memory Read Line okay */
  127 #define PCI_FLAGS_MRM_OKAY      0x08            /* Memory Read Multiple okay */
  128 #define PCI_FLAGS_MWI_OKAY      0x10            /* Memory Write and Invalidate
  129                                                    okay */
  130 
  131 /*
  132  * PCI device 'quirks'.
  133  *
  134  * In general strange behaviour which can be handled by a driver (e.g.
  135  * a bridge's inability to pass a type of access correctly) should be.
  136  * The quirks table should only contain information which impacts
  137  * the operation of the MI PCI code and which can't be pushed lower
  138  * (e.g. because it's unacceptable to require a driver to be present
  139  * for the information to be known).
  140  */
  141 struct pci_quirkdata {
  142         pci_vendor_id_t         vendor;         /* Vendor ID */
  143         pci_product_id_t        product;        /* Product ID */
  144         int                     quirks;         /* quirks; see below */
  145 };
  146 #define PCI_QUIRK_MULTIFUNCTION         1
  147 #define PCI_QUIRK_MONOFUNCTION          2
  148 #define PCI_QUIRK_SKIP_FUNC(n)          (4 << n)
  149 #define PCI_QUIRK_SKIP_FUNC0            PCI_QUIRK_SKIP_FUNC(0)
  150 #define PCI_QUIRK_SKIP_FUNC1            PCI_QUIRK_SKIP_FUNC(1)
  151 #define PCI_QUIRK_SKIP_FUNC2            PCI_QUIRK_SKIP_FUNC(2)
  152 #define PCI_QUIRK_SKIP_FUNC3            PCI_QUIRK_SKIP_FUNC(3)
  153 #define PCI_QUIRK_SKIP_FUNC4            PCI_QUIRK_SKIP_FUNC(4)
  154 #define PCI_QUIRK_SKIP_FUNC5            PCI_QUIRK_SKIP_FUNC(5)
  155 #define PCI_QUIRK_SKIP_FUNC6            PCI_QUIRK_SKIP_FUNC(6)
  156 #define PCI_QUIRK_SKIP_FUNC7            PCI_QUIRK_SKIP_FUNC(7)
  157 
  158 struct pci_softc {
  159         struct device sc_dev;
  160         bus_space_tag_t sc_iot, sc_memt;
  161         bus_dma_tag_t sc_dmat;
  162         bus_dma_tag_t sc_dmat64;
  163         pci_chipset_tag_t sc_pc;
  164         int sc_bus, sc_maxndevs;
  165         pcitag_t *sc_bridgetag;
  166         u_int sc_intrswiz;
  167         pcitag_t sc_intrtag;
  168         int sc_flags;
  169 };
  170 
  171 extern struct cfdriver pci_cd;
  172 
  173 /*
  174  * Locators devices that attach to 'pcibus', as specified to config.
  175  */
  176 #define pcibuscf_bus            cf_loc[PCIBUSCF_BUS]
  177 #define PCIBUS_UNK_BUS          PCIBUSCF_BUS_DEFAULT    /* wildcarded 'bus' */
  178 
  179 /*
  180  * Locators for PCI devices, as specified to config.
  181  */
  182 #define pcicf_dev               cf_loc[PCICF_DEV]
  183 #define PCI_UNK_DEV             PCICF_DEV_DEFAULT       /* wildcarded 'dev' */
  184 
  185 #define pcicf_function          cf_loc[PCICF_FUNCTION]
  186 #define PCI_UNK_FUNCTION        PCICF_FUNCTION_DEFAULT /* wildcarded 'function' */
  187 
  188 /*
  189  * Configuration space access and utility functions.  (Note that most,
  190  * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.)
  191  */
  192 int     pci_mapreg_probe __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t *));
  193 pcireg_t pci_mapreg_type __P((pci_chipset_tag_t, pcitag_t, int));
  194 int     pci_mapreg_info __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t,
  195             bus_addr_t *, bus_size_t *, int *));
  196 int     pci_mapreg_map __P((struct pci_attach_args *, int, pcireg_t, int,
  197             bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *,
  198             bus_size_t *));
  199 
  200 int pci_get_capability __P((pci_chipset_tag_t, pcitag_t, int,
  201                             int *, pcireg_t *));
  202 
  203 /*
  204  * Helper functions for autoconfiguration.
  205  */
  206 int     pci_enumerate_bus_generic(struct pci_softc *,
  207             int (*)(struct pci_attach_args *), struct pci_attach_args *);
  208 int     pci_probe_device(struct pci_softc *, pcitag_t tag,
  209             int (*)(struct pci_attach_args *), struct pci_attach_args *);
  210 void    pci_devinfo __P((pcireg_t, pcireg_t, int, char *));
  211 void    pci_conf_print __P((pci_chipset_tag_t, pcitag_t,
  212             void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)));
  213 const struct pci_quirkdata *
  214         pci_lookup_quirkdata __P((pci_vendor_id_t, pci_product_id_t));
  215 
  216 /*
  217  * Helper functions for user access to the PCI bus.
  218  */
  219 struct proc;
  220 int     pci_devioctl __P((pci_chipset_tag_t, pcitag_t, u_long, caddr_t,
  221             int flag, struct proc *));
  222 
  223 /*
  224  * Power Management (PCI 2.2)
  225  */
  226 
  227 #define PCI_PWR_D0      0
  228 #define PCI_PWR_D1      1
  229 #define PCI_PWR_D2      2
  230 #define PCI_PWR_D3      3
  231 int     pci_set_powerstate __P((pci_chipset_tag_t, pcitag_t, int));
  232 int     pci_get_powerstate __P((pci_chipset_tag_t, pcitag_t));
  233 
  234 /*
  235  * Vital Product Data (PCI 2.2)
  236  */
  237 int     pci_vpd_read __P((pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *));
  238 int     pci_vpd_write __P((pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *));
  239 
  240 /*
  241  * Misc.
  242  */
  243 char   *pci_findvendor __P((pcireg_t));
  244 int     pci_find_device(struct pci_attach_args *pa,
  245                         int (*match)(struct pci_attach_args *));
  246 int     pci_dma64_available(struct pci_attach_args *);
  247 
  248 
  249 #endif /* _KERNEL */
  250 
  251 #endif /* _DEV_PCI_PCIVAR_H_ */

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