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sys/dev/pci/pdcide.c
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1 /* $NetBSD: pdcide.c,v 1.11 2004/01/03 22:56:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_pdc202xx_reg.h> 40 41 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void pdc202xx_setup_channel(struct wdc_channel *); 43 static void pdc20268_setup_channel(struct wdc_channel *); 44 static int pdc202xx_pci_intr(void *); 45 static int pdc20265_pci_intr(void *); 46 static void pdc20262_dma_start(void *, int, int); 47 static int pdc20262_dma_finish(void *, int, int, int); 48 49 static int pdcide_match(struct device *, struct cfdata *, void *); 50 static void pdcide_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(pdcide, sizeof(struct pciide_softc), 53 pdcide_match, pdcide_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_promise_products[] = { 56 { PCI_PRODUCT_PROMISE_PDC20246, 57 0, 58 "Promise Ultra33/ATA Bus Master IDE Accelerator", 59 pdc202xx_chip_map, 60 }, 61 { PCI_PRODUCT_PROMISE_PDC20262, 62 0, 63 "Promise Ultra66/ATA Bus Master IDE Accelerator", 64 pdc202xx_chip_map, 65 }, 66 { PCI_PRODUCT_PROMISE_PDC20267, 67 0, 68 "Promise Ultra100/ATA Bus Master IDE Accelerator", 69 pdc202xx_chip_map, 70 }, 71 { PCI_PRODUCT_PROMISE_PDC20265, 72 0, 73 "Promise Ultra100/ATA Bus Master IDE Accelerator", 74 pdc202xx_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_PDC20268, 77 0, 78 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 79 pdc202xx_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20270, 82 0, 83 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 84 pdc202xx_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20269, 87 0, 88 "Promise Ultra133/ATA Bus Master IDE Accelerator", 89 pdc202xx_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20276, 92 0, 93 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 94 pdc202xx_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20275, 97 0, 98 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 99 pdc202xx_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20271, 102 0, 103 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 104 pdc202xx_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20277, 107 0, 108 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 109 pdc202xx_chip_map, 110 }, 111 { 0, 112 0, 113 NULL, 114 NULL 115 } 116 }; 117 118 static int 119 pdcide_match(struct device *parent, struct cfdata *match, void *aux) 120 { 121 struct pci_attach_args *pa = aux; 122 123 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 124 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 125 return (2); 126 } 127 return (0); 128 } 129 130 static void 131 pdcide_attach(struct device *parent, struct device *self, void *aux) 132 { 133 struct pci_attach_args *pa = aux; 134 struct pciide_softc *sc = (struct pciide_softc *)self; 135 136 pciide_common_attach(sc, pa, 137 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 138 139 } 140 141 /* Macros to test product */ 142 #define PDC_IS_262(sc) \ 143 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 144 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 145 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 146 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 147 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 148 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 153 #define PDC_IS_265(sc) \ 154 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 163 #define PDC_IS_268(sc) \ 164 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 171 #define PDC_IS_276(sc) \ 172 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 176 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 177 178 static void 179 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 180 { 181 struct pciide_channel *cp; 182 int channel; 183 pcireg_t interface, st, mode; 184 bus_size_t cmdsize, ctlsize; 185 186 if (!PDC_IS_268(sc)) { 187 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 188 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 189 st), DEBUG_PROBE); 190 /* turn off RAID mode */ 191 if (st & PDC2xx_STATE_IDERAID) { 192 WDCDEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE); 193 st &= ~PDC2xx_STATE_IDERAID; 194 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 195 } 196 } else 197 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1); 198 199 if (pciide_chipen(sc, pa) == 0) 200 return; 201 202 /* 203 * can't rely on the PCI_CLASS_REG content if the chip was in raid 204 * mode. We have to fake interface 205 */ 206 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 207 if (st & PDC2xx_STATE_NATIVE) 208 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 209 210 aprint_normal("%s: bus-master DMA support present", 211 sc->sc_wdcdev.sc_dev.dv_xname); 212 pciide_mapreg_dma(sc, pa); 213 aprint_normal("\n"); 214 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 215 WDC_CAPABILITY_MODE; 216 if (sc->sc_dma_ok) { 217 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 219 sc->sc_wdcdev.irqack = pciide_irqack; 220 } 221 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 222 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 223 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 224 sc->sc_wdcdev.PIO_cap = 4; 225 sc->sc_wdcdev.DMA_cap = 2; 226 if (PDC_IS_276(sc)) 227 sc->sc_wdcdev.UDMA_cap = 6; 228 else if (PDC_IS_265(sc)) 229 sc->sc_wdcdev.UDMA_cap = 5; 230 else if (PDC_IS_262(sc)) 231 sc->sc_wdcdev.UDMA_cap = 4; 232 else 233 sc->sc_wdcdev.UDMA_cap = 2; 234 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 235 pdc20268_setup_channel : pdc202xx_setup_channel; 236 sc->sc_wdcdev.channels = sc->wdc_chanarray; 237 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 238 239 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || 240 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || 241 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265) { 242 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 243 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 244 } 245 246 if (!PDC_IS_268(sc)) { 247 /* setup failsafe defaults */ 248 mode = 0; 249 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 250 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 251 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 252 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 253 for (channel = 0; 254 channel < sc->sc_wdcdev.nchannels; 255 channel++) { 256 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 257 "drive 0 initial timings 0x%x, now 0x%x\n", 258 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 259 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 260 DEBUG_PROBE); 261 pci_conf_write(sc->sc_pc, sc->sc_tag, 262 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 263 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 264 "drive 1 initial timings 0x%x, now 0x%x\n", 265 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 266 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 267 pci_conf_write(sc->sc_pc, sc->sc_tag, 268 PDC2xx_TIM(channel, 1), mode); 269 } 270 271 mode = PDC2xx_SCR_DMA; 272 if (PDC_IS_265(sc)) { 273 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 274 } else if (PDC_IS_262(sc)) { 275 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 276 } else { 277 /* the BIOS set it up this way */ 278 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 279 } 280 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 281 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 282 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 283 "now 0x%x\n", 284 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 285 PDC2xx_SCR), 286 mode), DEBUG_PROBE); 287 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 288 PDC2xx_SCR, mode); 289 290 /* controller initial state register is OK even without BIOS */ 291 /* Set DMA mode to IDE DMA compatibility */ 292 mode = 293 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 294 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 295 DEBUG_PROBE); 296 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 297 mode | 0x1); 298 mode = 299 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 300 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 301 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 302 mode | 0x1); 303 } 304 305 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 306 cp = &sc->pciide_channels[channel]; 307 if (pciide_chansetup(sc, channel, interface) == 0) 308 continue; 309 if ((st & (PDC_IS_262(sc) ? 310 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 311 aprint_normal("%s: %s channel ignored (disabled)\n", 312 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 313 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 314 continue; 315 } 316 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 317 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 318 /* clear interrupt, in case there is one pending */ 319 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 320 IDEDMA_CTL_INTR); 321 } 322 return; 323 } 324 325 static void 326 pdc202xx_setup_channel(struct wdc_channel *chp) 327 { 328 struct ata_drive_datas *drvp; 329 int drive; 330 pcireg_t mode, st; 331 u_int32_t idedma_ctl, scr, atapi; 332 struct pciide_channel *cp = (struct pciide_channel*)chp; 333 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 334 int channel = chp->ch_channel; 335 336 /* setup DMA if needed */ 337 pciide_channel_dma_setup(cp); 338 339 idedma_ctl = 0; 340 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 341 sc->sc_wdcdev.sc_dev.dv_xname, 342 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 343 DEBUG_PROBE); 344 345 /* Per channel settings */ 346 if (PDC_IS_262(sc)) { 347 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 348 PDC262_U66); 349 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 350 /* Trim UDMA mode */ 351 if ((st & PDC262_STATE_80P(channel)) != 0 || 352 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 353 chp->ch_drive[0].UDMA_mode <= 2) || 354 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 355 chp->ch_drive[1].UDMA_mode <= 2)) { 356 if (chp->ch_drive[0].UDMA_mode > 2) 357 chp->ch_drive[0].UDMA_mode = 2; 358 if (chp->ch_drive[1].UDMA_mode > 2) 359 chp->ch_drive[1].UDMA_mode = 2; 360 } 361 /* Set U66 if needed */ 362 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 363 chp->ch_drive[0].UDMA_mode > 2) || 364 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 365 chp->ch_drive[1].UDMA_mode > 2)) 366 scr |= PDC262_U66_EN(channel); 367 else 368 scr &= ~PDC262_U66_EN(channel); 369 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 370 PDC262_U66, scr); 371 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 372 sc->sc_wdcdev.sc_dev.dv_xname, channel, 373 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 374 PDC262_ATAPI(channel))), DEBUG_PROBE); 375 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 376 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 377 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 378 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 379 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 380 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 381 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 382 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 383 atapi = 0; 384 else 385 atapi = PDC262_ATAPI_UDMA; 386 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 387 PDC262_ATAPI(channel), atapi); 388 } 389 } 390 for (drive = 0; drive < 2; drive++) { 391 drvp = &chp->ch_drive[drive]; 392 /* If no drive, skip */ 393 if ((drvp->drive_flags & DRIVE) == 0) 394 continue; 395 mode = 0; 396 if (drvp->drive_flags & DRIVE_UDMA) { 397 /* use Ultra/DMA */ 398 drvp->drive_flags &= ~DRIVE_DMA; 399 mode = PDC2xx_TIM_SET_MB(mode, 400 pdc2xx_udma_mb[drvp->UDMA_mode]); 401 mode = PDC2xx_TIM_SET_MC(mode, 402 pdc2xx_udma_mc[drvp->UDMA_mode]); 403 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 404 } else if (drvp->drive_flags & DRIVE_DMA) { 405 mode = PDC2xx_TIM_SET_MB(mode, 406 pdc2xx_dma_mb[drvp->DMA_mode]); 407 mode = PDC2xx_TIM_SET_MC(mode, 408 pdc2xx_dma_mc[drvp->DMA_mode]); 409 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 410 } else { 411 mode = PDC2xx_TIM_SET_MB(mode, 412 pdc2xx_dma_mb[0]); 413 mode = PDC2xx_TIM_SET_MC(mode, 414 pdc2xx_dma_mc[0]); 415 } 416 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 417 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 418 if (drvp->drive_flags & DRIVE_ATA) 419 mode |= PDC2xx_TIM_PRE; 420 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 421 if (drvp->PIO_mode >= 3) { 422 mode |= PDC2xx_TIM_IORDY; 423 if (drive == 0) 424 mode |= PDC2xx_TIM_IORDYp; 425 } 426 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 427 "timings 0x%x\n", 428 sc->sc_wdcdev.sc_dev.dv_xname, 429 chp->ch_channel, drive, mode), DEBUG_PROBE); 430 pci_conf_write(sc->sc_pc, sc->sc_tag, 431 PDC2xx_TIM(chp->ch_channel, drive), mode); 432 } 433 if (idedma_ctl != 0) { 434 /* Add software bits in status register */ 435 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 436 0, idedma_ctl); 437 } 438 } 439 440 static void 441 pdc20268_setup_channel(struct wdc_channel *chp) 442 { 443 struct ata_drive_datas *drvp; 444 int drive; 445 u_int32_t idedma_ctl; 446 struct pciide_channel *cp = (struct pciide_channel*)chp; 447 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 448 int u100; 449 450 /* setup DMA if needed */ 451 pciide_channel_dma_setup(cp); 452 453 idedma_ctl = 0; 454 455 /* I don't know what this is for, FreeBSD does it ... */ 456 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 457 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->ch_channel, 0x0b); 458 459 /* 460 * cable type detect, from FreeBSD 461 */ 462 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 463 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->ch_channel) & 0x04) ? 464 0 : 1; 465 466 for (drive = 0; drive < 2; drive++) { 467 drvp = &chp->ch_drive[drive]; 468 /* If no drive, skip */ 469 if ((drvp->drive_flags & DRIVE) == 0) 470 continue; 471 if (drvp->drive_flags & DRIVE_UDMA) { 472 /* use Ultra/DMA */ 473 drvp->drive_flags &= ~DRIVE_DMA; 474 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 475 if (drvp->UDMA_mode > 2 && u100 == 0) 476 drvp->UDMA_mode = 2; 477 } else if (drvp->drive_flags & DRIVE_DMA) { 478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 479 } 480 } 481 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 482 if (idedma_ctl != 0) { 483 /* Add software bits in status register */ 484 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 485 0, idedma_ctl); 486 } 487 } 488 489 static int 490 pdc202xx_pci_intr(void *arg) 491 { 492 struct pciide_softc *sc = arg; 493 struct pciide_channel *cp; 494 struct wdc_channel *wdc_cp; 495 int i, rv, crv; 496 u_int32_t scr; 497 498 rv = 0; 499 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 500 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 501 cp = &sc->pciide_channels[i]; 502 wdc_cp = &cp->wdc_channel; 503 /* If a compat channel skip. */ 504 if (cp->compat) 505 continue; 506 if (scr & PDC2xx_SCR_INT(i)) { 507 crv = wdcintr(wdc_cp); 508 if (crv == 0) 509 printf("%s:%d: bogus intr (reg 0x%x)\n", 510 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 511 else 512 rv = 1; 513 } 514 } 515 return rv; 516 } 517 518 static int 519 pdc20265_pci_intr(void *arg) 520 { 521 struct pciide_softc *sc = arg; 522 struct pciide_channel *cp; 523 struct wdc_channel *wdc_cp; 524 int i, rv, crv; 525 u_int32_t dmastat; 526 527 rv = 0; 528 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 529 cp = &sc->pciide_channels[i]; 530 wdc_cp = &cp->wdc_channel; 531 /* If a compat channel skip. */ 532 if (cp->compat) 533 continue; 534 #if 0 535 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 536 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 537 continue; 538 #endif 539 /* 540 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 541 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 542 * So use it instead (requires 2 reg reads instead of 1, 543 * but we can't do it another way). 544 */ 545 dmastat = bus_space_read_1(sc->sc_dma_iot, 546 cp->dma_iohs[IDEDMA_CTL], 0); 547 if((dmastat & IDEDMA_CTL_INTR) == 0) 548 continue; 549 crv = wdcintr(wdc_cp); 550 if (crv == 0) 551 printf("%s:%d: bogus intr\n", 552 sc->sc_wdcdev.sc_dev.dv_xname, i); 553 else 554 rv = 1; 555 } 556 return rv; 557 } 558 559 static void 560 pdc20262_dma_start(void *v, int channel, int drive) 561 { 562 struct pciide_softc *sc = v; 563 struct pciide_dma_maps *dma_maps = 564 &sc->pciide_channels[channel].dma_maps[drive]; 565 int atapi; 566 567 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 568 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 569 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 570 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 571 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 572 PDC262_ATAPI(channel), atapi); 573 } 574 575 pciide_dma_start(v, channel, drive); 576 } 577 578 static int 579 pdc20262_dma_finish(void *v, int channel, int drive, int force) 580 { 581 struct pciide_softc *sc = v; 582 struct pciide_dma_maps *dma_maps = 583 &sc->pciide_channels[channel].dma_maps[drive]; 584 struct wdc_channel *chp; 585 int atapi, error; 586 587 error = pciide_dma_finish(v, channel, drive, force); 588 589 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 590 chp = sc->wdc_chanarray[channel]; 591 atapi = 0; 592 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 593 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 594 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 595 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 596 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 597 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 598 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 599 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 600 atapi = PDC262_ATAPI_UDMA; 601 } 602 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 603 PDC262_ATAPI(channel), atapi); 604 } 605 606 return error; 607 }
Cache object: d213ec24d4e7dd9576aceabded3fefa5
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