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sys/dev/pci/piixide.c
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1 /* $NetBSD: piixide.c,v 1.8.2.1 2004/07/28 11:21:02 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct wdc_channel *); 43 static void piix3_4_setup_channel(struct wdc_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 0, 135 "Intel 6300ESB IDE Controller (ICH5)", 136 piix_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 0, 140 "Intel 6300ESB Serial ATA Controller", 141 piixsata_chip_map, 142 }, 143 { 0, 144 0, 145 NULL, 146 NULL 147 } 148 }; 149 150 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 151 piixide_match, piixide_attach, NULL, NULL); 152 153 static int 154 piixide_match(struct device *parent, struct cfdata *match, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 159 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 160 return (2); 161 } 162 return (0); 163 } 164 165 static void 166 piixide_attach(struct device *parent, struct device *self, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 struct pciide_softc *sc = (struct pciide_softc *)self; 170 171 pciide_common_attach(sc, pa, 172 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 173 174 } 175 176 static void 177 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 178 { 179 struct pciide_channel *cp; 180 int channel; 181 u_int32_t idetim; 182 bus_size_t cmdsize, ctlsize; 183 184 if (pciide_chipen(sc, pa) == 0) 185 return; 186 187 aprint_normal("%s: bus-master DMA support present", 188 sc->sc_wdcdev.sc_dev.dv_xname); 189 pciide_mapreg_dma(sc, pa); 190 aprint_normal("\n"); 191 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 192 WDC_CAPABILITY_MODE; 193 if (sc->sc_dma_ok) { 194 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 195 sc->sc_wdcdev.irqack = pciide_irqack; 196 switch(sc->sc_pp->ide_product) { 197 case PCI_PRODUCT_INTEL_82371AB_IDE: 198 case PCI_PRODUCT_INTEL_82440MX_IDE: 199 case PCI_PRODUCT_INTEL_82801AA_IDE: 200 case PCI_PRODUCT_INTEL_82801AB_IDE: 201 case PCI_PRODUCT_INTEL_82801BA_IDE: 202 case PCI_PRODUCT_INTEL_82801BAM_IDE: 203 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 204 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 205 case PCI_PRODUCT_INTEL_82801DB_IDE: 206 case PCI_PRODUCT_INTEL_82801DBM_IDE: 207 case PCI_PRODUCT_INTEL_82801EB_IDE: 208 case PCI_PRODUCT_INTEL_6300ESB_IDE: 209 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 210 } 211 } 212 sc->sc_wdcdev.PIO_cap = 4; 213 sc->sc_wdcdev.DMA_cap = 2; 214 switch(sc->sc_pp->ide_product) { 215 case PCI_PRODUCT_INTEL_82801AA_IDE: 216 sc->sc_wdcdev.UDMA_cap = 4; 217 break; 218 case PCI_PRODUCT_INTEL_82801BA_IDE: 219 case PCI_PRODUCT_INTEL_82801BAM_IDE: 220 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 221 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 222 case PCI_PRODUCT_INTEL_82801DB_IDE: 223 case PCI_PRODUCT_INTEL_82801DBM_IDE: 224 case PCI_PRODUCT_INTEL_82801EB_IDE: 225 case PCI_PRODUCT_INTEL_6300ESB_IDE: 226 sc->sc_wdcdev.UDMA_cap = 5; 227 break; 228 default: 229 sc->sc_wdcdev.UDMA_cap = 2; 230 } 231 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 232 sc->sc_wdcdev.set_modes = piix_setup_channel; 233 else 234 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 235 sc->sc_wdcdev.channels = sc->wdc_chanarray; 236 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 237 238 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 239 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 240 DEBUG_PROBE); 241 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 242 WDCDEBUG_PRINT((", sidetim=0x%x", 243 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 244 DEBUG_PROBE); 245 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 246 WDCDEBUG_PRINT((", udamreg 0x%x", 247 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 248 DEBUG_PROBE); 249 } 250 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 251 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 253 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 254 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 255 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 256 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 257 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 258 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 259 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 260 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 261 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 262 DEBUG_PROBE); 263 } 264 265 } 266 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 267 268 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 269 cp = &sc->pciide_channels[channel]; 270 /* PIIX is compat-only */ 271 if (pciide_chansetup(sc, channel, 0) == 0) 272 continue; 273 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 274 if ((PIIX_IDETIM_READ(idetim, channel) & 275 PIIX_IDETIM_IDE) == 0) { 276 #if 1 277 aprint_normal("%s: %s channel ignored (disabled)\n", 278 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 279 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 280 continue; 281 #else 282 pcireg_t interface; 283 284 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 285 channel); 286 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 287 idetim); 288 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 289 sc->sc_tag, PCI_CLASS_REG)); 290 aprint_normal("channel %d idetim=%08x interface=%02x\n", 291 channel, idetim, interface); 292 #endif 293 } 294 /* PIIX are compat-only pciide devices */ 295 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 296 } 297 298 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 299 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 300 DEBUG_PROBE); 301 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 302 WDCDEBUG_PRINT((", sidetim=0x%x", 303 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 304 DEBUG_PROBE); 305 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 306 WDCDEBUG_PRINT((", udamreg 0x%x", 307 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 308 DEBUG_PROBE); 309 } 310 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 311 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 312 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 313 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 314 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 315 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 316 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 317 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 318 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 319 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 320 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 321 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 322 DEBUG_PROBE); 323 } 324 } 325 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 326 } 327 328 static void 329 piix_setup_channel(struct wdc_channel *chp) 330 { 331 u_int8_t mode[2], drive; 332 u_int32_t oidetim, idetim, idedma_ctl; 333 struct pciide_channel *cp = (struct pciide_channel*)chp; 334 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 335 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 336 337 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 338 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 339 idedma_ctl = 0; 340 341 /* set up new idetim: Enable IDE registers decode */ 342 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 343 chp->ch_channel); 344 345 /* setup DMA */ 346 pciide_channel_dma_setup(cp); 347 348 /* 349 * Here we have to mess up with drives mode: PIIX can't have 350 * different timings for master and slave drives. 351 * We need to find the best combination. 352 */ 353 354 /* If both drives supports DMA, take the lower mode */ 355 if ((drvp[0].drive_flags & DRIVE_DMA) && 356 (drvp[1].drive_flags & DRIVE_DMA)) { 357 mode[0] = mode[1] = 358 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 359 drvp[0].DMA_mode = mode[0]; 360 drvp[1].DMA_mode = mode[1]; 361 goto ok; 362 } 363 /* 364 * If only one drive supports DMA, use its mode, and 365 * put the other one in PIO mode 0 if mode not compatible 366 */ 367 if (drvp[0].drive_flags & DRIVE_DMA) { 368 mode[0] = drvp[0].DMA_mode; 369 mode[1] = drvp[1].PIO_mode; 370 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 371 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 372 mode[1] = drvp[1].PIO_mode = 0; 373 goto ok; 374 } 375 if (drvp[1].drive_flags & DRIVE_DMA) { 376 mode[1] = drvp[1].DMA_mode; 377 mode[0] = drvp[0].PIO_mode; 378 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 379 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 380 mode[0] = drvp[0].PIO_mode = 0; 381 goto ok; 382 } 383 /* 384 * If both drives are not DMA, takes the lower mode, unless 385 * one of them is PIO mode < 2 386 */ 387 if (drvp[0].PIO_mode < 2) { 388 mode[0] = drvp[0].PIO_mode = 0; 389 mode[1] = drvp[1].PIO_mode; 390 } else if (drvp[1].PIO_mode < 2) { 391 mode[1] = drvp[1].PIO_mode = 0; 392 mode[0] = drvp[0].PIO_mode; 393 } else { 394 mode[0] = mode[1] = 395 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 396 drvp[0].PIO_mode = mode[0]; 397 drvp[1].PIO_mode = mode[1]; 398 } 399 ok: /* The modes are setup */ 400 for (drive = 0; drive < 2; drive++) { 401 if (drvp[drive].drive_flags & DRIVE_DMA) { 402 idetim |= piix_setup_idetim_timings( 403 mode[drive], 1, chp->ch_channel); 404 goto end; 405 } 406 } 407 /* If we are there, none of the drives are DMA */ 408 if (mode[0] >= 2) 409 idetim |= piix_setup_idetim_timings( 410 mode[0], 0, chp->ch_channel); 411 else 412 idetim |= piix_setup_idetim_timings( 413 mode[1], 0, chp->ch_channel); 414 end: /* 415 * timing mode is now set up in the controller. Enable 416 * it per-drive 417 */ 418 for (drive = 0; drive < 2; drive++) { 419 /* If no drive, skip */ 420 if ((drvp[drive].drive_flags & DRIVE) == 0) 421 continue; 422 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 423 if (drvp[drive].drive_flags & DRIVE_DMA) 424 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 425 } 426 if (idedma_ctl != 0) { 427 /* Add software bits in status register */ 428 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 429 idedma_ctl); 430 } 431 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 432 } 433 434 static void 435 piix3_4_setup_channel(struct wdc_channel *chp) 436 { 437 struct ata_drive_datas *drvp; 438 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 439 struct pciide_channel *cp = (struct pciide_channel*)chp; 440 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 441 struct wdc_softc *wdc = &sc->sc_wdcdev; 442 int drive; 443 int channel = chp->ch_channel; 444 445 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 446 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 447 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 448 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 449 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 450 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 451 PIIX_SIDETIM_RTC_MASK(channel)); 452 idedma_ctl = 0; 453 454 /* set up new idetim: Enable IDE registers decode */ 455 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 456 457 /* setup DMA if needed */ 458 pciide_channel_dma_setup(cp); 459 460 for (drive = 0; drive < 2; drive++) { 461 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 462 PIIX_UDMATIM_SET(0x3, channel, drive)); 463 drvp = &chp->ch_drive[drive]; 464 /* If no drive, skip */ 465 if ((drvp->drive_flags & DRIVE) == 0) 466 continue; 467 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 468 (drvp->drive_flags & DRIVE_UDMA) == 0)) 469 goto pio; 470 471 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 478 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 481 ideconf |= PIIX_CONFIG_PINGPONG; 482 } 483 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 490 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 491 /* setup Ultra/100 */ 492 if (drvp->UDMA_mode > 2 && 493 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 494 drvp->UDMA_mode = 2; 495 if (drvp->UDMA_mode > 4) { 496 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 497 } else { 498 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 499 if (drvp->UDMA_mode > 2) { 500 ideconf |= PIIX_CONFIG_UDMA66(channel, 501 drive); 502 } else { 503 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 504 drive); 505 } 506 } 507 } 508 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 509 /* setup Ultra/66 */ 510 if (drvp->UDMA_mode > 2 && 511 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 512 drvp->UDMA_mode = 2; 513 if (drvp->UDMA_mode > 2) 514 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 515 else 516 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 517 } 518 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 519 (drvp->drive_flags & DRIVE_UDMA)) { 520 /* use Ultra/DMA */ 521 drvp->drive_flags &= ~DRIVE_DMA; 522 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 523 udmareg |= PIIX_UDMATIM_SET( 524 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 525 } else { 526 /* use Multiword DMA */ 527 drvp->drive_flags &= ~DRIVE_UDMA; 528 if (drive == 0) { 529 idetim |= piix_setup_idetim_timings( 530 drvp->DMA_mode, 1, channel); 531 } else { 532 sidetim |= piix_setup_sidetim_timings( 533 drvp->DMA_mode, 1, channel); 534 idetim =PIIX_IDETIM_SET(idetim, 535 PIIX_IDETIM_SITRE, channel); 536 } 537 } 538 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 539 540 pio: /* use PIO mode */ 541 idetim |= piix_setup_idetim_drvs(drvp); 542 if (drive == 0) { 543 idetim |= piix_setup_idetim_timings( 544 drvp->PIO_mode, 0, channel); 545 } else { 546 sidetim |= piix_setup_sidetim_timings( 547 drvp->PIO_mode, 0, channel); 548 idetim =PIIX_IDETIM_SET(idetim, 549 PIIX_IDETIM_SITRE, channel); 550 } 551 } 552 if (idedma_ctl != 0) { 553 /* Add software bits in status register */ 554 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 555 idedma_ctl); 556 } 557 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 558 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 559 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 560 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 561 } 562 563 564 /* setup ISP and RTC fields, based on mode */ 565 static u_int32_t 566 piix_setup_idetim_timings(mode, dma, channel) 567 u_int8_t mode; 568 u_int8_t dma; 569 u_int8_t channel; 570 { 571 572 if (dma) 573 return PIIX_IDETIM_SET(0, 574 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 575 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 576 channel); 577 else 578 return PIIX_IDETIM_SET(0, 579 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 580 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 581 channel); 582 } 583 584 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 585 static u_int32_t 586 piix_setup_idetim_drvs(drvp) 587 struct ata_drive_datas *drvp; 588 { 589 u_int32_t ret = 0; 590 struct wdc_channel *chp = drvp->chnl_softc; 591 u_int8_t channel = chp->ch_channel; 592 u_int8_t drive = drvp->drive; 593 594 /* 595 * If drive is using UDMA, timings setups are independant 596 * So just check DMA and PIO here. 597 */ 598 if (drvp->drive_flags & DRIVE_DMA) { 599 /* if mode = DMA mode 0, use compatible timings */ 600 if ((drvp->drive_flags & DRIVE_DMA) && 601 drvp->DMA_mode == 0) { 602 drvp->PIO_mode = 0; 603 return ret; 604 } 605 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 606 /* 607 * PIO and DMA timings are the same, use fast timings for PIO 608 * too, else use compat timings. 609 */ 610 if ((piix_isp_pio[drvp->PIO_mode] != 611 piix_isp_dma[drvp->DMA_mode]) || 612 (piix_rtc_pio[drvp->PIO_mode] != 613 piix_rtc_dma[drvp->DMA_mode])) 614 drvp->PIO_mode = 0; 615 /* if PIO mode <= 2, use compat timings for PIO */ 616 if (drvp->PIO_mode <= 2) { 617 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 618 channel); 619 return ret; 620 } 621 } 622 623 /* 624 * Now setup PIO modes. If mode < 2, use compat timings. 625 * Else enable fast timings. Enable IORDY and prefetch/post 626 * if PIO mode >= 3. 627 */ 628 629 if (drvp->PIO_mode < 2) 630 return ret; 631 632 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 633 if (drvp->PIO_mode >= 3) { 634 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 635 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 636 } 637 return ret; 638 } 639 640 /* setup values in SIDETIM registers, based on mode */ 641 static u_int32_t 642 piix_setup_sidetim_timings(mode, dma, channel) 643 u_int8_t mode; 644 u_int8_t dma; 645 u_int8_t channel; 646 { 647 if (dma) 648 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 649 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 650 else 651 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 652 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 653 } 654 655 static void 656 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 657 { 658 struct pciide_channel *cp; 659 bus_size_t cmdsize, ctlsize; 660 pcireg_t interface; 661 int channel; 662 663 if (pciide_chipen(sc, pa) == 0) 664 return; 665 666 aprint_normal("%s: bus-master DMA support present", 667 sc->sc_wdcdev.sc_dev.dv_xname); 668 pciide_mapreg_dma(sc, pa); 669 aprint_normal("\n"); 670 671 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 672 WDC_CAPABILITY_MODE; 673 sc->sc_wdcdev.PIO_cap = 4; 674 if (sc->sc_dma_ok) { 675 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 676 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 677 sc->sc_wdcdev.irqack = pciide_irqack; 678 sc->sc_wdcdev.DMA_cap = 2; 679 sc->sc_wdcdev.UDMA_cap = 6; 680 } 681 sc->sc_wdcdev.set_modes = sata_setup_channel; 682 683 sc->sc_wdcdev.channels = sc->wdc_chanarray; 684 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 685 686 interface = PCI_INTERFACE(pa->pa_class); 687 688 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 689 cp = &sc->pciide_channels[channel]; 690 if (pciide_chansetup(sc, channel, interface) == 0) 691 continue; 692 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 693 pciide_pci_intr); 694 } 695 }
Cache object: 06e0e785859e634d3292ab4b22c9fb95
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