Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/pci/siside.c
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1 /* $NetBSD: siside.c,v 1.5.2.1 2004/07/23 22:00:31 he Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_sis_reg.h> 40 41 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void sis_setup_channel(struct wdc_channel *); 43 static void sis96x_setup_channel(struct wdc_channel *); 44 45 static int sis_hostbr_match(struct pci_attach_args *); 46 static int sis_south_match(struct pci_attach_args *); 47 48 static int siside_match(struct device *, struct cfdata *, void *); 49 static void siside_attach(struct device *, struct device *, void *); 50 51 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 52 siside_match, siside_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_sis_products[] = { 55 { PCI_PRODUCT_SIS_5597_IDE, 56 0, 57 NULL, 58 sis_chip_map, 59 }, 60 { 0, 61 0, 62 NULL, 63 NULL 64 } 65 }; 66 67 static int 68 siside_match(struct device *parent, struct cfdata *match, void *aux) 69 { 70 struct pci_attach_args *pa = aux; 71 72 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 73 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 74 return (2); 75 } 76 return (0); 77 } 78 79 static void 80 siside_attach(struct device *parent, struct device *self, void *aux) 81 { 82 struct pci_attach_args *pa = aux; 83 struct pciide_softc *sc = (struct pciide_softc *)self; 84 85 pciide_common_attach(sc, pa, 86 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 87 88 } 89 90 static struct sis_hostbr_type { 91 u_int16_t id; 92 u_int8_t rev; 93 u_int8_t udma_mode; 94 char *name; 95 u_int8_t type; 96 #define SIS_TYPE_NOUDMA 0 97 #define SIS_TYPE_66 1 98 #define SIS_TYPE_100OLD 2 99 #define SIS_TYPE_100NEW 3 100 #define SIS_TYPE_133OLD 4 101 #define SIS_TYPE_133NEW 5 102 #define SIS_TYPE_SOUTH 6 103 } sis_hostbr_type[] = { 104 /* Most infos here are from sos@freebsd.org */ 105 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 106 #if 0 107 /* 108 * controllers associated to a rev 0x2 530 Host to PCI Bridge 109 * have problems with UDMA (info provided by Christos) 110 */ 111 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 112 #endif 113 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 114 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 115 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 116 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 117 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 118 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 119 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 120 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 121 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 122 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 123 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 124 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 125 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 126 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 127 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 128 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 129 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 130 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 131 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 132 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 134 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 135 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 136 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 137 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 138 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 139 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 140 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 141 /* 142 * From sos@freebsd.org: the 0x961 ID will never be found in real world 143 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 144 */ 145 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 146 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 147 }; 148 149 static struct sis_hostbr_type *sis_hostbr_type_match; 150 151 static int 152 sis_hostbr_match(struct pci_attach_args *pa) 153 { 154 int i; 155 156 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 157 return 0; 158 sis_hostbr_type_match = NULL; 159 for (i = 0; 160 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 161 i++) { 162 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 163 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 164 sis_hostbr_type_match = &sis_hostbr_type[i]; 165 } 166 return (sis_hostbr_type_match != NULL); 167 } 168 169 static int 170 sis_south_match(struct pci_attach_args *pa) 171 { 172 173 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 174 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 175 PCI_REVISION(pa->pa_class) >= 0x10); 176 } 177 178 static void 179 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 180 { 181 struct pciide_channel *cp; 182 int channel; 183 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 184 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 185 pcireg_t rev = PCI_REVISION(pa->pa_class); 186 bus_size_t cmdsize, ctlsize; 187 188 if (pciide_chipen(sc, pa) == 0) 189 return; 190 191 aprint_normal("%s: Silicon Integrated System ", 192 sc->sc_wdcdev.sc_dev.dv_xname); 193 pci_find_device(NULL, sis_hostbr_match); 194 if (sis_hostbr_type_match) { 195 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 196 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 197 pciide_pci_read(sc->sc_pc, sc->sc_tag, 198 SIS_REG_57) & 0x7f); 199 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 200 PCI_ID_REG)) == SIS_PRODUCT_5518) { 201 aprint_normal("96X UDMA%d", 202 sis_hostbr_type_match->udma_mode); 203 sc->sis_type = SIS_TYPE_133NEW; 204 sc->sc_wdcdev.UDMA_cap = 205 sis_hostbr_type_match->udma_mode; 206 } else { 207 if (pci_find_device(NULL, sis_south_match)) { 208 sc->sis_type = SIS_TYPE_133OLD; 209 sc->sc_wdcdev.UDMA_cap = 210 sis_hostbr_type_match->udma_mode; 211 } else { 212 sc->sis_type = SIS_TYPE_100NEW; 213 sc->sc_wdcdev.UDMA_cap = 214 sis_hostbr_type_match->udma_mode; 215 } 216 } 217 } else { 218 sc->sis_type = sis_hostbr_type_match->type; 219 sc->sc_wdcdev.UDMA_cap = 220 sis_hostbr_type_match->udma_mode; 221 } 222 aprint_normal(sis_hostbr_type_match->name); 223 } else { 224 aprint_normal("5597/5598"); 225 if (rev >= 0xd0) { 226 sc->sc_wdcdev.UDMA_cap = 2; 227 sc->sis_type = SIS_TYPE_66; 228 } else { 229 sc->sc_wdcdev.UDMA_cap = 0; 230 sc->sis_type = SIS_TYPE_NOUDMA; 231 } 232 } 233 aprint_normal(" IDE controller (rev. 0x%02x)\n", 234 PCI_REVISION(pa->pa_class)); 235 aprint_normal("%s: bus-master DMA support present", 236 sc->sc_wdcdev.sc_dev.dv_xname); 237 pciide_mapreg_dma(sc, pa); 238 aprint_normal("\n"); 239 240 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 241 WDC_CAPABILITY_MODE; 242 if (sc->sc_dma_ok) { 243 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 244 sc->sc_wdcdev.irqack = pciide_irqack; 245 if (sc->sis_type >= SIS_TYPE_66) 246 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 247 } 248 249 sc->sc_wdcdev.PIO_cap = 4; 250 sc->sc_wdcdev.DMA_cap = 2; 251 252 sc->sc_wdcdev.channels = sc->wdc_chanarray; 253 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 254 switch(sc->sis_type) { 255 case SIS_TYPE_NOUDMA: 256 case SIS_TYPE_66: 257 case SIS_TYPE_100OLD: 258 sc->sc_wdcdev.set_modes = sis_setup_channel; 259 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 260 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 261 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 262 break; 263 case SIS_TYPE_100NEW: 264 case SIS_TYPE_133OLD: 265 sc->sc_wdcdev.set_modes = sis_setup_channel; 266 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 267 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 268 break; 269 case SIS_TYPE_133NEW: 270 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 271 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 272 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 273 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 274 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 275 break; 276 } 277 278 279 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 280 cp = &sc->pciide_channels[channel]; 281 if (pciide_chansetup(sc, channel, interface) == 0) 282 continue; 283 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 284 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 285 aprint_normal("%s: %s channel ignored (disabled)\n", 286 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 287 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 288 continue; 289 } 290 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 291 pciide_pci_intr); 292 } 293 } 294 295 static void 296 sis96x_setup_channel(struct wdc_channel *chp) 297 { 298 struct ata_drive_datas *drvp; 299 int drive; 300 u_int32_t sis_tim; 301 u_int32_t idedma_ctl; 302 int regtim; 303 struct pciide_channel *cp = (struct pciide_channel*)chp; 304 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 305 306 sis_tim = 0; 307 idedma_ctl = 0; 308 /* setup DMA if needed */ 309 pciide_channel_dma_setup(cp); 310 311 for (drive = 0; drive < 2; drive++) { 312 regtim = SIS_TIM133( 313 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 314 chp->ch_channel, drive); 315 drvp = &chp->ch_drive[drive]; 316 /* If no drive, skip */ 317 if ((drvp->drive_flags & DRIVE) == 0) 318 continue; 319 /* add timing values, setup DMA if needed */ 320 if (drvp->drive_flags & DRIVE_UDMA) { 321 /* use Ultra/DMA */ 322 drvp->drive_flags &= ~DRIVE_DMA; 323 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 324 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 325 if (drvp->UDMA_mode > 2) 326 drvp->UDMA_mode = 2; 327 } 328 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 329 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 330 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 331 } else if (drvp->drive_flags & DRIVE_DMA) { 332 /* 333 * use Multiword DMA 334 * Timings will be used for both PIO and DMA, 335 * so adjust DMA mode if needed 336 */ 337 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 338 drvp->PIO_mode = drvp->DMA_mode + 2; 339 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 340 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 341 drvp->PIO_mode - 2 : 0; 342 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 343 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 344 } else { 345 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 346 } 347 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 348 "channel %d drive %d: 0x%x (reg 0x%x)\n", 349 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 350 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 351 } 352 if (idedma_ctl != 0) { 353 /* Add software bits in status register */ 354 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 355 idedma_ctl); 356 } 357 } 358 359 static void 360 sis_setup_channel(struct wdc_channel *chp) 361 { 362 struct ata_drive_datas *drvp; 363 int drive; 364 u_int32_t sis_tim; 365 u_int32_t idedma_ctl; 366 struct pciide_channel *cp = (struct pciide_channel*)chp; 367 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 368 369 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 370 "channel %d 0x%x\n", chp->ch_channel, 371 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 372 DEBUG_PROBE); 373 sis_tim = 0; 374 idedma_ctl = 0; 375 /* setup DMA if needed */ 376 pciide_channel_dma_setup(cp); 377 378 for (drive = 0; drive < 2; drive++) { 379 drvp = &chp->ch_drive[drive]; 380 /* If no drive, skip */ 381 if ((drvp->drive_flags & DRIVE) == 0) 382 continue; 383 /* add timing values, setup DMA if needed */ 384 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 385 (drvp->drive_flags & DRIVE_UDMA) == 0) 386 goto pio; 387 388 if (drvp->drive_flags & DRIVE_UDMA) { 389 /* use Ultra/DMA */ 390 drvp->drive_flags &= ~DRIVE_DMA; 391 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 392 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 393 if (drvp->UDMA_mode > 2) 394 drvp->UDMA_mode = 2; 395 } 396 switch (sc->sis_type) { 397 case SIS_TYPE_66: 398 case SIS_TYPE_100OLD: 399 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 400 SIS_TIM66_UDMA_TIME_OFF(drive); 401 break; 402 case SIS_TYPE_100NEW: 403 sis_tim |= 404 sis_udma100new_tim[drvp->UDMA_mode] << 405 SIS_TIM100_UDMA_TIME_OFF(drive); 406 case SIS_TYPE_133OLD: 407 sis_tim |= 408 sis_udma133old_tim[drvp->UDMA_mode] << 409 SIS_TIM100_UDMA_TIME_OFF(drive); 410 break; 411 default: 412 aprint_error("unknown SiS IDE type %d\n", 413 sc->sis_type); 414 } 415 } else { 416 /* 417 * use Multiword DMA 418 * Timings will be used for both PIO and DMA, 419 * so adjust DMA mode if needed 420 */ 421 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 422 drvp->PIO_mode = drvp->DMA_mode + 2; 423 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 424 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 425 drvp->PIO_mode - 2 : 0; 426 if (drvp->DMA_mode == 0) 427 drvp->PIO_mode = 0; 428 } 429 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 430 pio: switch (sc->sis_type) { 431 case SIS_TYPE_NOUDMA: 432 case SIS_TYPE_66: 433 case SIS_TYPE_100OLD: 434 sis_tim |= sis_pio_act[drvp->PIO_mode] << 435 SIS_TIM66_ACT_OFF(drive); 436 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 437 SIS_TIM66_REC_OFF(drive); 438 break; 439 case SIS_TYPE_100NEW: 440 case SIS_TYPE_133OLD: 441 sis_tim |= sis_pio_act[drvp->PIO_mode] << 442 SIS_TIM100_ACT_OFF(drive); 443 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 444 SIS_TIM100_REC_OFF(drive); 445 break; 446 default: 447 aprint_error("unknown SiS IDE type %d\n", 448 sc->sis_type); 449 } 450 } 451 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 452 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 453 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 454 sis_tim); 455 if (idedma_ctl != 0) { 456 /* Add software bits in status register */ 457 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 458 idedma_ctl); 459 } 460 }
Cache object: 172ffa06c30840b708824a5426dbed46
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