Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/pci/tga.c
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1 /* $NetBSD: tga.c,v 1.57 2003/11/13 03:09:29 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.57 2003/11/13 03:09:29 chs Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 int tgamatch __P((struct device *, struct cfdata *, void *)); 63 void tgaattach __P((struct device *, struct device *, void *)); 64 int tgaprint __P((void *, const char *)); 65 66 CFATTACH_DECL(tga, sizeof(struct tga_softc), 67 tgamatch, tgaattach, NULL, NULL); 68 69 int tga_identify __P((struct tga_devconfig *)); 70 const struct tga_conf *tga_getconf __P((int)); 71 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 72 pcitag_t tag, struct tga_devconfig *dc)); 73 74 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 75 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 76 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 77 unsigned tga_getdotclock __P((struct tga_devconfig *dc)); 78 79 struct tga_devconfig tga_console_dc; 80 81 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 82 paddr_t tga_mmap __P((void *, off_t, int)); 83 static void tga_copyrows __P((void *, int, int, int)); 84 static void tga_copycols __P((void *, int, int, int, int)); 85 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 86 void **, int *, int *, long *)); 87 static void tga_free_screen __P((void *, void *)); 88 static int tga_show_screen __P((void *, void *, int, 89 void (*) (void *, int, int), void *)); 90 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 91 struct rasops_info *, int, int)); 92 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 93 int, struct rasops_info *, int, int )); 94 static void tga_putchar __P((void *c, int row, int col, 95 u_int uc, long attr)); 96 static void tga_eraserows __P((void *, int, int, long)); 97 static void tga_erasecols __P((void *, int, int, int, long)); 98 void tga2_init __P((struct tga_devconfig *)); 99 100 static void tga_config_interrupts __P((struct device *)); 101 102 /* RAMDAC interface functions */ 103 static int tga_sched_update __P((void *, void (*)(void *))); 104 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 105 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 106 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 107 static u_int8_t tga_bt463_rd __P((void *, u_int)); 108 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 109 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 110 111 /* Interrupt handler */ 112 static int tga_intr __P((void *)); 113 114 /* The NULL entries will get filled in by rasops_init(). 115 * XXX and the non-NULL ones will be overwritten; reset after calling it. 116 */ 117 struct wsdisplay_emulops tga_emulops = { 118 NULL, 119 NULL, 120 tga_putchar, 121 tga_copycols, 122 tga_erasecols, 123 tga_copyrows, 124 tga_eraserows, 125 NULL, 126 }; 127 128 struct wsscreen_descr tga_stdscreen = { 129 "std", 130 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 131 &tga_emulops, 132 0, 0, 133 WSSCREEN_REVERSE 134 }; 135 136 const struct wsscreen_descr *_tga_scrlist[] = { 137 &tga_stdscreen, 138 /* XXX other formats, graphics screen? */ 139 }; 140 141 struct wsscreen_list tga_screenlist = { 142 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 143 }; 144 145 struct wsdisplay_accessops tga_accessops = { 146 tga_ioctl, 147 tga_mmap, 148 tga_alloc_screen, 149 tga_free_screen, 150 tga_show_screen, 151 0 /* load_font */ 152 }; 153 154 static void tga_blank __P((struct tga_devconfig *)); 155 static void tga_unblank __P((struct tga_devconfig *)); 156 157 int 158 tga_cnmatch(iot, memt, pc, tag) 159 bus_space_tag_t iot, memt; 160 pci_chipset_tag_t pc; 161 pcitag_t tag; 162 { 163 return tga_matchcommon(memt, pc, tag); 164 } 165 166 int 167 tgamatch(parent, match, aux) 168 struct device *parent; 169 struct cfdata *match; 170 void *aux; 171 { 172 struct pci_attach_args *pa = aux; 173 174 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 175 return (0); 176 177 switch (PCI_PRODUCT(pa->pa_id)) { 178 case PCI_PRODUCT_DEC_21030: 179 case PCI_PRODUCT_DEC_PBXGB: 180 break; 181 default: 182 return 0; 183 } 184 185 /* short-circuit the following test, as we 186 * already have the memory mapped and hence 187 * cannot perform it---and we are the console 188 * anyway. 189 */ 190 if (pa->pa_tag == tga_console_dc.dc_pcitag) 191 return 10; 192 193 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 194 } 195 196 static int 197 tga_matchcommon(memt, pc, tag) 198 bus_space_tag_t memt; 199 pci_chipset_tag_t pc; 200 pcitag_t tag; 201 { 202 struct tga_devconfig tmp_dc; 203 struct tga_devconfig *dc = &tmp_dc; 204 bus_size_t pcisize; 205 206 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 207 dc->dc_tga_type = tga_identify(dc); 208 209 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 210 bus_space_unmap(memt, dc->dc_memh, pcisize); 211 if (dc->dc_tgaconf) 212 return 10; 213 return 0; 214 } 215 216 static void 217 tga_mapaddrs(memt, pc, tag, pcisize, dc) 218 bus_space_tag_t memt; 219 pci_chipset_tag_t pc; 220 pcitag_t tag; 221 bus_size_t *pcisize; 222 struct tga_devconfig *dc; 223 { 224 int flags; 225 226 dc->dc_memt = memt; 227 dc->dc_tgaconf = NULL; 228 229 /* XXX magic number */ 230 if (pci_mapreg_info(pc, tag, 0x10, 231 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 232 &dc->dc_pcipaddr, pcisize, &flags)) 233 panic("tga_mapaddrs: pci_mapreg_info() failed"); 234 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 235 panic("tga memory not prefetchable"); 236 237 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 238 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 239 panic("tga_mapaddrs: could not map TGA address space"); 240 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 241 242 bus_space_subregion(dc->dc_memt, dc->dc_memh, 243 TGA_MEM_CREGS, TGA_CREGS_SIZE, 244 &dc->dc_regs); 245 } 246 247 static void 248 tga_init(memt, pc, tag, dc) 249 bus_space_tag_t memt; 250 pci_chipset_tag_t pc; 251 pcitag_t tag; 252 struct tga_devconfig *dc; 253 { 254 const struct tga_conf *tgac; 255 struct rasops_info *rip; 256 int cookie; 257 bus_size_t pcisize; 258 int i; 259 260 dc->dc_pcitag = tag; 261 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 262 dc->dc_tga_type = tga_identify(dc); 263 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 264 #if 0 265 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 266 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 267 panic("tga_init: memory size mismatch?"); 268 #endif 269 270 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 271 case 0x01: 272 case 0x02: 273 case 0x03: 274 case 0x04: 275 dc->dc_tga2 = 0; 276 break; 277 case 0x20: 278 case 0x21: 279 case 0x22: 280 dc->dc_tga2 = 1; 281 break; 282 default: 283 panic("tga_init: TGA Revision not recognized"); 284 } 285 286 if (dc->dc_tga2) 287 tga2_init(dc); 288 289 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 290 case 0: 291 dc->dc_wid = 8192; 292 break; 293 294 case 1: 295 dc->dc_wid = 8196; 296 break; 297 298 default: 299 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 300 break; 301 } 302 303 /* 304 * XXX XXX Turning off "odd" shouldn't be necessary, 305 * XXX XXX but I can't make X work with the weird size. 306 */ 307 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 308 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 309 TGAWREG(dc, TGA_REG_VHCR, 310 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 311 dc->dc_wid -= 4; 312 } 313 314 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 315 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 316 317 /* XXX this seems to be what DEC does */ 318 TGAWREG(dc, TGA_REG_CCBR, 0); 319 TGAWREG(dc, TGA_REG_VVBR, 1); 320 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 321 1 * tgac->tgac_vvbr_units; 322 dc->dc_blanked = 1; 323 tga_unblank(dc); 324 325 /* 326 * Set all bits in the pixel mask, to enable writes to all pixels. 327 * It seems that the console firmware clears some of them 328 * under some circumstances, which causes cute vertical stripes. 329 */ 330 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 331 332 /* clear the screen */ 333 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 334 *(u_int32_t *)(dc->dc_videobase + i) = 0; 335 336 /* Initialize rasops descriptor */ 337 rip = &dc->dc_rinfo; 338 rip->ri_flg = RI_CENTER; 339 rip->ri_depth = tgac->tgac_phys_depth; 340 rip->ri_bits = (void *)dc->dc_videobase; 341 rip->ri_width = dc->dc_wid; 342 rip->ri_height = dc->dc_ht; 343 rip->ri_stride = dc->dc_rowbytes; 344 rip->ri_hw = dc; 345 346 if (tgac->tgac_phys_depth == 32) { 347 rip->ri_rnum = 8; 348 rip->ri_gnum = 8; 349 rip->ri_bnum = 8; 350 rip->ri_rpos = 16; 351 rip->ri_gpos = 8; 352 rip->ri_bpos = 0; 353 } 354 355 wsfont_init(); 356 /* prefer 8 pixel wide font */ 357 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 358 WSDISPLAY_FONTORDER_L2R); 359 if (cookie <= 0) 360 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 361 WSDISPLAY_FONTORDER_L2R); 362 if (cookie <= 0) { 363 printf("tga: no appropriate fonts.\n"); 364 return; 365 } 366 367 /* the accelerated tga_putchar() needs LSbit left */ 368 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 369 printf("tga: couldn't lock font\n"); 370 return; 371 } 372 dc->dc_rinfo.ri_wsfcookie = cookie; 373 374 rasops_init(rip, 34, 80); 375 376 /* add our accelerated functions */ 377 /* XXX shouldn't have to do this; rasops should leave non-NULL 378 * XXX entries alone. 379 */ 380 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 381 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 382 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 383 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 384 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 385 386 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 387 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 388 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 389 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 390 391 392 dc->dc_intrenabled = 0; 393 } 394 395 void 396 tgaattach(parent, self, aux) 397 struct device *parent, *self; 398 void *aux; 399 { 400 struct pci_attach_args *pa = aux; 401 struct tga_softc *sc = (struct tga_softc *)self; 402 struct wsemuldisplaydev_attach_args aa; 403 pci_intr_handle_t intrh; 404 const char *intrstr; 405 u_int8_t rev; 406 int console; 407 408 #if defined(__alpha__) || defined(arc) 409 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 410 #else 411 console = 0; 412 #endif 413 if (console) { 414 sc->sc_dc = &tga_console_dc; 415 sc->nscreens = 1; 416 } else { 417 sc->sc_dc = (struct tga_devconfig *) 418 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 419 M_WAITOK|M_ZERO); 420 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 421 } 422 if (sc->sc_dc->dc_vaddr == 0) { 423 printf(": couldn't map memory space; punt!\n"); 424 return; 425 } 426 427 /* XXX say what's going on. */ 428 intrstr = NULL; 429 if (pci_intr_map(pa, &intrh)) { 430 printf(": couldn't map interrupt"); 431 return; 432 } 433 intrstr = pci_intr_string(pa->pa_pc, intrh); 434 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 435 sc->sc_dc); 436 if (sc->sc_intr == NULL) { 437 printf(": couldn't establish interrupt"); 438 if (intrstr != NULL) 439 printf("at %s", intrstr); 440 printf("\n"); 441 return; 442 } 443 444 rev = PCI_REVISION(pa->pa_class); 445 switch (rev) { 446 case 0x1: 447 case 0x2: 448 case 0x3: 449 printf(": DC21030 step %c", 'A' + rev - 1); 450 break; 451 case 0x20: 452 printf(": TGA2 abstract software model"); 453 break; 454 case 0x21: 455 case 0x22: 456 printf(": TGA2 pass %d", rev - 0x20); 457 break; 458 459 default: 460 printf("unknown stepping (0x%x)", rev); 461 break; 462 } 463 printf(", "); 464 465 /* 466 * Get RAMDAC function vectors and call the RAMDAC functions 467 * to allocate its private storage and pass that back to us. 468 */ 469 470 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 471 if (!sc->sc_dc->dc_tga2) { 472 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 473 sc->sc_dc->dc_ramdac_cookie = 474 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 475 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 476 else 477 sc->sc_dc->dc_ramdac_cookie = 478 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 479 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 480 } else { 481 sc->sc_dc->dc_ramdac_cookie = 482 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 483 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 484 485 /* XXX this is a bit of a hack, setting the dotclock here */ 486 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 487 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 488 (sc->sc_dc->dc_ramdac_cookie, 489 tga_getdotclock(sc->sc_dc)); 490 } 491 492 /* 493 * Initialize the RAMDAC. Initialization includes disabling 494 * cursor, setting a sane colormap, etc. We presume that we've 495 * filled in the necessary dot clock for PowerStorm 4d20. 496 */ 497 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 498 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 499 500 if (sc->sc_dc->dc_tgaconf == NULL) { 501 printf("unknown board configuration\n"); 502 return; 503 } 504 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 505 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 506 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 507 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 508 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 509 510 if (intrstr != NULL) 511 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 512 intrstr); 513 514 aa.console = console; 515 aa.scrdata = &tga_screenlist; 516 aa.accessops = &tga_accessops; 517 aa.accesscookie = sc; 518 519 config_found(self, &aa, wsemuldisplaydevprint); 520 521 config_interrupts(self, tga_config_interrupts); 522 } 523 524 static void 525 tga_config_interrupts (d) 526 struct device *d; 527 { 528 struct tga_softc *sc = (struct tga_softc *)d; 529 sc->sc_dc->dc_intrenabled = 1; 530 } 531 532 int 533 tga_ioctl(v, cmd, data, flag, p) 534 void *v; 535 u_long cmd; 536 caddr_t data; 537 int flag; 538 struct proc *p; 539 { 540 struct tga_softc *sc = v; 541 struct tga_devconfig *dc = sc->sc_dc; 542 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 543 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 544 545 switch (cmd) { 546 case WSDISPLAYIO_GTYPE: 547 *(u_int *)data = WSDISPLAY_TYPE_TGA; 548 return (0); 549 550 case WSDISPLAYIO_GINFO: 551 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 552 wsd_fbip->height = sc->sc_dc->dc_ht; 553 wsd_fbip->width = sc->sc_dc->dc_wid; 554 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 555 #if 0 556 wsd_fbip->cmsize = 256; /* XXX ??? */ 557 #else 558 wsd_fbip->cmsize = 1024; /* XXX ??? */ 559 #endif 560 #undef wsd_fbip 561 return (0); 562 563 case WSDISPLAYIO_GETCMAP: 564 return (*dcrf->ramdac_get_cmap)(dcrc, 565 (struct wsdisplay_cmap *)data); 566 567 case WSDISPLAYIO_PUTCMAP: 568 return (*dcrf->ramdac_set_cmap)(dcrc, 569 (struct wsdisplay_cmap *)data); 570 571 case WSDISPLAYIO_SVIDEO: 572 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 573 tga_blank(sc->sc_dc); 574 else 575 tga_unblank(sc->sc_dc); 576 return (0); 577 578 case WSDISPLAYIO_GVIDEO: 579 *(u_int *)data = dc->dc_blanked ? 580 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 581 return (0); 582 583 case WSDISPLAYIO_GCURPOS: 584 return (*dcrf->ramdac_get_curpos)(dcrc, 585 (struct wsdisplay_curpos *)data); 586 587 case WSDISPLAYIO_SCURPOS: 588 return (*dcrf->ramdac_set_curpos)(dcrc, 589 (struct wsdisplay_curpos *)data); 590 591 case WSDISPLAYIO_GCURMAX: 592 return (*dcrf->ramdac_get_curmax)(dcrc, 593 (struct wsdisplay_curpos *)data); 594 595 case WSDISPLAYIO_GCURSOR: 596 return (*dcrf->ramdac_get_cursor)(dcrc, 597 (struct wsdisplay_cursor *)data); 598 599 case WSDISPLAYIO_SCURSOR: 600 return (*dcrf->ramdac_set_cursor)(dcrc, 601 (struct wsdisplay_cursor *)data); 602 } 603 return (EPASSTHROUGH); 604 } 605 606 static int 607 tga_sched_update(v, f) 608 void *v; 609 void (*f) __P((void *)); 610 { 611 struct tga_devconfig *dc = v; 612 613 if (dc->dc_intrenabled) { 614 /* Arrange for f to be called at the next end-of-frame interrupt */ 615 dc->dc_ramdac_intr = f; 616 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 617 } else { 618 /* Spin until the end-of-frame, then call f */ 619 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 620 TGAREGWB(dc, TGA_REG_SISR, 1); 621 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 622 ; 623 f(dc->dc_ramdac_cookie); 624 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 625 TGAREGWB(dc, TGA_REG_SISR, 1); 626 } 627 628 return 0; 629 } 630 631 static int 632 tga_intr(v) 633 void *v; 634 { 635 struct tga_devconfig *dc = v; 636 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 637 638 u_int32_t reg; 639 640 reg = TGARREG(dc, TGA_REG_SISR); 641 if (( reg & 0x00010001) != 0x00010001) { 642 /* Odd. We never set any of the other interrupt enables. */ 643 if ((reg & 0x1f) != 0) { 644 /* Clear the mysterious pending interrupts. */ 645 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 646 TGAREGWB(dc, TGA_REG_SISR, 1); 647 /* This was our interrupt, even if we're puzzled as to why 648 * we got it. Don't make the interrupt handler think it 649 * was a stray. 650 */ 651 return -1; 652 } else { 653 return 0; 654 } 655 } 656 /* if we have something to do, do it */ 657 if (dc->dc_ramdac_intr) { 658 dc->dc_ramdac_intr(dcrc); 659 dc->dc_ramdac_intr = NULL; 660 } 661 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 662 TGAREGWB(dc, TGA_REG_SISR, 1); 663 return (1); 664 } 665 666 paddr_t 667 tga_mmap(v, offset, prot) 668 void *v; 669 off_t offset; 670 int prot; 671 { 672 struct tga_softc *sc = v; 673 674 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 675 return -1; 676 677 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 678 offset, prot, BUS_SPACE_MAP_LINEAR)); 679 } 680 681 static int 682 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 683 void *v; 684 const struct wsscreen_descr *type; 685 void **cookiep; 686 int *curxp, *curyp; 687 long *attrp; 688 { 689 struct tga_softc *sc = v; 690 long defattr; 691 692 if (sc->nscreens > 0) 693 return (ENOMEM); 694 695 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 696 *curxp = 0; 697 *curyp = 0; 698 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 699 0, 0, 0, &defattr); 700 *attrp = defattr; 701 sc->nscreens++; 702 return (0); 703 } 704 705 static void 706 tga_free_screen(v, cookie) 707 void *v; 708 void *cookie; 709 { 710 struct tga_softc *sc = v; 711 712 if (sc->sc_dc == &tga_console_dc) 713 panic("tga_free_screen: console"); 714 715 sc->nscreens--; 716 } 717 718 static int 719 tga_show_screen(v, cookie, waitok, cb, cbarg) 720 void *v; 721 void *cookie; 722 int waitok; 723 void (*cb) __P((void *, int, int)); 724 void *cbarg; 725 { 726 727 return (0); 728 } 729 730 int 731 tga_cnattach(iot, memt, pc, bus, device, function) 732 bus_space_tag_t iot, memt; 733 pci_chipset_tag_t pc; 734 int bus, device, function; 735 { 736 struct tga_devconfig *dcp = &tga_console_dc; 737 long defattr; 738 739 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 740 741 /* sanity checks */ 742 if (dcp->dc_vaddr == 0) 743 panic("tga_console(%d, %d): couldn't map memory space", 744 device, function); 745 if (dcp->dc_tgaconf == NULL) 746 panic("tga_console(%d, %d): unknown board configuration", 747 device, function); 748 749 /* 750 * Initialize the RAMDAC but DO NOT allocate any private storage. 751 * Initialization includes disabling cursor, setting a sane 752 * colormap, etc. It will be reinitialized in tgaattach(). 753 */ 754 if (dcp->dc_tga2) { 755 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 756 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 757 tga2_ramdac_rd); 758 else 759 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 760 tga2_ramdac_rd, tga_getdotclock(dcp)); 761 } else { 762 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 763 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 764 tga_ramdac_rd); 765 else { 766 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 767 tga_bt463_rd); 768 } 769 } 770 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 771 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 772 773 return(0); 774 } 775 776 /* 777 * Functions to blank and unblank the display. 778 */ 779 static void 780 tga_blank(dc) 781 struct tga_devconfig *dc; 782 { 783 784 if (!dc->dc_blanked) { 785 dc->dc_blanked = 1; 786 /* XXX */ 787 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 788 } 789 } 790 791 static void 792 tga_unblank(dc) 793 struct tga_devconfig *dc; 794 { 795 796 if (dc->dc_blanked) { 797 dc->dc_blanked = 0; 798 /* XXX */ 799 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 800 } 801 } 802 803 /* 804 * Functions to manipulate the built-in cursor handing hardware. 805 */ 806 int 807 tga_builtin_set_cursor(dc, cursorp) 808 struct tga_devconfig *dc; 809 struct wsdisplay_cursor *cursorp; 810 { 811 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 812 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 813 u_char image[512]; 814 u_int count, v; 815 int error; 816 817 v = cursorp->which; 818 if (v & WSDISPLAY_CURSOR_DOCMAP) { 819 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 820 if (error) 821 return (error); 822 } 823 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 824 if ((u_int)cursorp->size.x != 64 || 825 (u_int)cursorp->size.y > 64) 826 return (EINVAL); 827 /* The cursor is 2 bits deep, and there is no mask */ 828 count = (cursorp->size.y * 64 * 2) / NBBY; 829 error = copyin(cursorp->image, image, count); 830 if (error) 831 return error; 832 } 833 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 834 return EINVAL; 835 836 /* parameters are OK; do it */ 837 if (v & WSDISPLAY_CURSOR_DOCUR) { 838 if (cursorp->enable) 839 /* XXX */ 840 TGAWREG(dc, TGA_REG_VVVR, 841 TGARREG(dc, TGA_REG_VVVR) | 0x04); 842 else 843 /* XXX */ 844 TGAWREG(dc, TGA_REG_VVVR, 845 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 846 } 847 if (v & WSDISPLAY_CURSOR_DOPOS) { 848 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 849 (cursorp->pos.x & 0xfff)); 850 } 851 if (v & WSDISPLAY_CURSOR_DOCMAP) { 852 dcrf->ramdac_set_curcmap(dcrc, cursorp); 853 } 854 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 855 count = ((64 * 2) / NBBY) * cursorp->size.y; 856 TGAWREG(dc, TGA_REG_CCBR, 857 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 858 (cursorp->size.y << 10)); 859 memcpy((char *)(dc->dc_vaddr + 860 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 861 image, count); 862 } 863 return (0); 864 } 865 866 int 867 tga_builtin_get_cursor(dc, cursorp) 868 struct tga_devconfig *dc; 869 struct wsdisplay_cursor *cursorp; 870 { 871 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 872 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 873 int count, error; 874 875 cursorp->which = WSDISPLAY_CURSOR_DOALL & 876 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 877 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 878 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 879 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 880 cursorp->size.x = 64; 881 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 882 883 if (cursorp->image != NULL) { 884 count = (cursorp->size.y * 64 * 2) / NBBY; 885 error = copyout((char *)(dc->dc_vaddr + 886 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 887 cursorp->image, count); 888 if (error) 889 return (error); 890 /* No mask */ 891 } 892 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 893 return (error); 894 } 895 896 int 897 tga_builtin_set_curpos(dc, curposp) 898 struct tga_devconfig *dc; 899 struct wsdisplay_curpos *curposp; 900 { 901 902 TGAWREG(dc, TGA_REG_CXYR, 903 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 904 return (0); 905 } 906 907 int 908 tga_builtin_get_curpos(dc, curposp) 909 struct tga_devconfig *dc; 910 struct wsdisplay_curpos *curposp; 911 { 912 913 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 914 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 915 return (0); 916 } 917 918 int 919 tga_builtin_get_curmax(dc, curposp) 920 struct tga_devconfig *dc; 921 struct wsdisplay_curpos *curposp; 922 { 923 924 curposp->x = curposp->y = 64; 925 return (0); 926 } 927 928 /* 929 * Copy columns (characters) in a row (line). 930 */ 931 static void 932 tga_copycols(id, row, srccol, dstcol, ncols) 933 void *id; 934 int row, srccol, dstcol, ncols; 935 { 936 struct rasops_info *ri = id; 937 int y, srcx, dstx, nx; 938 939 y = ri->ri_font->fontheight * row; 940 srcx = ri->ri_font->fontwidth * srccol; 941 dstx = ri->ri_font->fontwidth * dstcol; 942 nx = ri->ri_font->fontwidth * ncols; 943 944 tga_rop(ri, dstx, y, 945 nx, ri->ri_font->fontheight, RAS_SRC, 946 ri, srcx, y); 947 } 948 949 /* 950 * Copy rows (lines). 951 */ 952 static void 953 tga_copyrows(id, srcrow, dstrow, nrows) 954 void *id; 955 int srcrow, dstrow, nrows; 956 { 957 struct rasops_info *ri = id; 958 int srcy, dsty, ny; 959 960 srcy = ri->ri_font->fontheight * srcrow; 961 dsty = ri->ri_font->fontheight * dstrow; 962 ny = ri->ri_font->fontheight * nrows; 963 964 tga_rop(ri, 0, dsty, 965 ri->ri_emuwidth, ny, RAS_SRC, 966 ri, 0, srcy); 967 } 968 969 /* Do we need the src? */ 970 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 971 972 /* A mapping between our API and the TGA card */ 973 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 974 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 975 }; 976 977 /* 978 * Generic TGA raster op. 979 * This covers all possible raster ops, and 980 * clips the sizes and all of that. 981 */ 982 static int 983 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 984 struct rasops_info *dst; 985 int dx, dy, w, h, rop; 986 struct rasops_info *src; 987 int sx, sy; 988 { 989 if (!dst) 990 return -1; 991 if (needsrc[RAS_GETOP(rop)]) { 992 if (src == NULL) 993 return -1; /* We want a src */ 994 /* Clip against src */ 995 if (sx < 0) { 996 w += sx; 997 sx = 0; 998 } 999 if (sy < 0) { 1000 h += sy; 1001 sy = 0; 1002 } 1003 if (sx + w > src->ri_emuwidth) 1004 w = src->ri_emuwidth - sx; 1005 if (sy + h > src->ri_emuheight) 1006 h = src->ri_emuheight - sy; 1007 } else { 1008 if (src != NULL) 1009 return -1; /* We need no src */ 1010 } 1011 /* Clip against dst. We modify src regardless of using it, 1012 * since it really doesn't matter. 1013 */ 1014 if (dx < 0) { 1015 w += dx; 1016 sx -= dx; 1017 dx = 0; 1018 } 1019 if (dy < 0) { 1020 h += dy; 1021 sy -= dy; 1022 dy = 0; 1023 } 1024 if (dx + w > dst->ri_emuwidth) 1025 w = dst->ri_emuwidth - dx; 1026 if (dy + h > dst->ri_emuheight) 1027 h = dst->ri_emuheight - dy; 1028 if (w <= 0 || h <= 0) 1029 return 0; /* Vacuously true; */ 1030 if (!src) { 1031 /* XXX Punt! */ 1032 return -1; 1033 } 1034 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1035 } 1036 1037 1038 1039 /* 1040 * Video to Video raster ops. 1041 * This function deals with all raster ops that have a src and dst 1042 * that are on the card. 1043 */ 1044 static int 1045 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1046 struct rasops_info *dst; 1047 int dx, dy, w, h, rop; 1048 struct rasops_info *src; 1049 int sx, sy; 1050 { 1051 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1052 int srcb, dstb, tga_srcb, tga_dstb; 1053 int x, y, wb; 1054 int xstart, xend, xdir; 1055 int ystart, yend, ydir, yinc; 1056 int xleft, lastx, lastleft; 1057 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1058 1059 /* 1060 * I don't yet want to deal with unaligned guys, really. And we don't 1061 * deal with copies from one card to another. 1062 */ 1063 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1064 /* XXX Punt! */ 1065 /* XXX should never happen, since it's only being used to 1066 * XXX copy 8-pixel-wide characters. 1067 */ 1068 return -1; 1069 } 1070 1071 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1072 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1073 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1074 (sx + src->ri_xorigin) * (src->ri_depth/8); 1075 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1076 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1077 1078 if (sy >= dy) { 1079 ystart = 0; 1080 yend = (h - 1) * dst->ri_stride; 1081 ydir = 1; 1082 } else { 1083 ystart = (h - 1) * dst->ri_stride; 1084 yend = 0; 1085 ydir = -1; 1086 } 1087 yinc = ydir * dst->ri_stride; 1088 1089 wb = w * (dst->ri_depth / 8); 1090 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1091 xstart = 0; 1092 xend = wb; 1093 xdir = 1; 1094 } else { /* copy backwards */ 1095 xstart = wb; 1096 xend = 0; 1097 xdir = -1; 1098 } 1099 1100 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1101 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1102 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1103 1104 /* 1105 * we have 3 sizes of pixels to move in X direction: 1106 * 4 * 64 (unrolled TGA ops) 1107 * 64 (single TGA op) 1108 * 4 (CPU, using long word) 1109 */ 1110 1111 if (xdir == 1) { /* move to the left */ 1112 1113 if (wb & ~63) 1114 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1115 /* 4*64 byte chunks */ 1116 for (xleft = wb, x = xstart; xleft >= 4*64; 1117 x += 4*64, xleft -= 4*64) { 1118 1119 /* XXX XXX Eight writes to different addresses should fill 1120 * XXX XXX up the write buffers on 21064 and 21164 chips, 1121 * XXX XXX but later CPUs might have larger write buffers which 1122 * XXX XXX require further unrolling of this loop, or the 1123 * XXX XXX insertion of memory barriers. 1124 */ 1125 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1126 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1127 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1128 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1129 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1130 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1131 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1132 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1133 } 1134 1135 /* 64 byte chunks */ 1136 for (; xleft >= 64; x += 64, xleft -= 64) { 1137 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1138 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1139 } 1140 } 1141 1142 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1143 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1144 1145 lastleft = wb & 63; 1146 if (lastleft) { 1147 lastx = xstart + (wb & ~63); 1148 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1149 /* 4 byte granularity */ 1150 for (x = lastx, xleft = lastleft; xleft >= 4; 1151 x += 4, xleft -= 4) { 1152 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1153 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1154 } 1155 } 1156 } 1157 } 1158 else { /* above move to the left, below move to the right */ 1159 1160 if (wb & ~63) 1161 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1162 /* 4*64 byte chunks */ 1163 for (xleft = wb, x = xstart; xleft >= 4*64; 1164 x -= 4*64, xleft -= 4*64) { 1165 1166 /* XXX XXX Eight writes to different addresses should fill 1167 * XXX XXX up the write buffers on 21064 and 21164 chips, 1168 * XXX XXX but later CPUs might have larger write buffers which 1169 * XXX XXX require further unrolling of this loop, or the 1170 * XXX XXX insertion of memory barriers. 1171 */ 1172 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1173 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1174 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1175 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1176 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1177 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1178 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1179 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1180 } 1181 1182 /* 64 byte chunks */ 1183 for (; xleft >= 64; x -= 64, xleft -= 64) { 1184 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1185 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1186 } 1187 } 1188 1189 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1190 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1191 1192 lastleft = wb & 63; 1193 if (lastleft) { 1194 lastx = xstart - (wb & ~63); 1195 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1196 /* 4 byte granularity */ 1197 for (x = lastx, xleft = lastleft; xleft >= 4; 1198 x -= 4, xleft -= 4) { 1199 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1200 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1201 } 1202 } 1203 } 1204 } 1205 return 0; 1206 } 1207 1208 1209 void tga_putchar (c, row, col, uc, attr) 1210 void *c; 1211 int row, col; 1212 u_int uc; 1213 long attr; 1214 { 1215 struct rasops_info *ri = c; 1216 struct tga_devconfig *dc = ri->ri_hw; 1217 int fs, height, width; 1218 u_char *fr; 1219 int32_t *rp; 1220 1221 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1222 1223 height = ri->ri_font->fontheight; 1224 width = ri->ri_font->fontwidth; 1225 1226 uc -= ri->ri_font->firstchar; 1227 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1228 fs = ri->ri_font->stride; 1229 1230 /* Set foreground and background color. XXX memoize this somehow? 1231 * The rasops code has already expanded the color entry to 32 bits 1232 * for us, even for 8-bit displays, so we don't have to do anything. 1233 */ 1234 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1235 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1236 1237 /* Set raster operation to "copy"... */ 1238 if (ri->ri_depth == 8) 1239 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1240 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1241 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1242 1243 /* Set which pixels we're drawing (of a possible 32). */ 1244 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1245 1246 /* Set drawing mode to opaque stipple. */ 1247 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1248 1249 /* Insert write barrier before actually sending data */ 1250 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1251 TGAREGWB(dc, TGA_REG_GMOR, 1); 1252 1253 while(height--) { 1254 /* The actual stipple write */ 1255 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1256 1257 fr += fs; 1258 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1259 } 1260 1261 /* Do underline */ 1262 if ((attr & 1) != 0) { 1263 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1264 *rp = 0xffffffff; 1265 } 1266 1267 /* Set grapics mode back to normal. */ 1268 TGAWREG(dc, TGA_REG_GMOR, 0); 1269 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1270 1271 } 1272 1273 static void 1274 tga_eraserows(c, row, num, attr) 1275 void *c; 1276 int row, num; 1277 long attr; 1278 { 1279 struct rasops_info *ri = c; 1280 struct tga_devconfig *dc = ri->ri_hw; 1281 int32_t color, lines, pixels; 1282 int32_t *rp; 1283 1284 color = ri->ri_devcmap[(attr >> 16) & 15]; 1285 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1286 lines = num * ri->ri_font->fontheight; 1287 pixels = ri->ri_emuwidth - 1; 1288 1289 /* Set fill color in block-color registers */ 1290 TGAWREG(dc, TGA_REG_GBCR0, color); 1291 TGAWREG(dc, TGA_REG_GBCR1, color); 1292 if (ri->ri_depth != 8) { 1293 TGAWREG(dc, TGA_REG_GBCR2, color); 1294 TGAWREG(dc, TGA_REG_GBCR3, color); 1295 TGAWREG(dc, TGA_REG_GBCR4, color); 1296 TGAWREG(dc, TGA_REG_GBCR5, color); 1297 TGAWREG(dc, TGA_REG_GBCR6, color); 1298 TGAWREG(dc, TGA_REG_GBCR7, color); 1299 } 1300 1301 /* Set raster operation to "copy"... */ 1302 if (ri->ri_depth == 8) 1303 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1304 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1305 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1306 1307 /* Set which pixels we're drawing (of a possible 32). */ 1308 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1309 1310 /* Set drawing mode to block fill. */ 1311 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1312 1313 /* Insert write barrier before actually sending data */ 1314 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1315 TGAREGWB(dc, TGA_REG_GMOR, 1); 1316 1317 while (lines--) { 1318 *rp = pixels; 1319 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1320 } 1321 1322 /* Set grapics mode back to normal. */ 1323 TGAWREG(dc, TGA_REG_GMOR, 0); 1324 1325 } 1326 1327 static void 1328 tga_erasecols (c, row, col, num, attr) 1329 void *c; 1330 int row, col, num; 1331 long attr; 1332 { 1333 struct rasops_info *ri = c; 1334 struct tga_devconfig *dc = ri->ri_hw; 1335 int32_t color, lines, pixels; 1336 int32_t *rp; 1337 1338 color = ri->ri_devcmap[(attr >> 16) & 15]; 1339 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1340 lines = ri->ri_font->fontheight; 1341 pixels = (num * ri->ri_font->fontwidth) - 1; 1342 1343 /* Set fill color in block-color registers */ 1344 TGAWREG(dc, TGA_REG_GBCR0, color); 1345 TGAWREG(dc, TGA_REG_GBCR1, color); 1346 if (ri->ri_depth != 8) { 1347 TGAWREG(dc, TGA_REG_GBCR2, color); 1348 TGAWREG(dc, TGA_REG_GBCR3, color); 1349 TGAWREG(dc, TGA_REG_GBCR4, color); 1350 TGAWREG(dc, TGA_REG_GBCR5, color); 1351 TGAWREG(dc, TGA_REG_GBCR6, color); 1352 TGAWREG(dc, TGA_REG_GBCR7, color); 1353 } 1354 1355 /* Set raster operation to "copy"... */ 1356 if (ri->ri_depth == 8) 1357 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1358 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1359 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1360 1361 /* Set which pixels we're drawing (of a possible 32). */ 1362 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1363 1364 /* Set drawing mode to block fill. */ 1365 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1366 1367 /* Insert write barrier before actually sending data */ 1368 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1369 TGAREGWB(dc, TGA_REG_GMOR, 1); 1370 1371 while (lines--) { 1372 *rp = pixels; 1373 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1374 } 1375 1376 /* Set grapics mode back to normal. */ 1377 TGAWREG(dc, TGA_REG_GMOR, 0); 1378 } 1379 1380 1381 static void 1382 tga_ramdac_wr(v, btreg, val) 1383 void *v; 1384 u_int btreg; 1385 u_int8_t val; 1386 { 1387 struct tga_devconfig *dc = v; 1388 1389 if (btreg > BT485_REG_MAX) 1390 panic("tga_ramdac_wr: reg %d out of range", btreg); 1391 1392 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1393 TGAREGWB(dc, TGA_REG_EPDR, 1); 1394 } 1395 1396 static void 1397 tga2_ramdac_wr(v, btreg, val) 1398 void *v; 1399 u_int btreg; 1400 u_int8_t val; 1401 { 1402 struct tga_devconfig *dc = v; 1403 bus_space_handle_t ramdac; 1404 1405 if (btreg > BT485_REG_MAX) 1406 panic("tga_ramdac_wr: reg %d out of range", btreg); 1407 1408 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1409 (0xe << 12) + (btreg << 8), 4, &ramdac); 1410 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1411 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1412 } 1413 1414 static u_int8_t 1415 tga_bt463_rd(v, btreg) 1416 void *v; 1417 u_int btreg; 1418 { 1419 struct tga_devconfig *dc = v; 1420 tga_reg_t rdval; 1421 1422 /* 1423 * Strobe CE# (high->low->high) since status and data are latched on 1424 * the falling and rising edges (repsectively) of this active-low signal. 1425 */ 1426 1427 TGAREGWB(dc, TGA_REG_EPSR, 1); 1428 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1429 TGAREGWB(dc, TGA_REG_EPSR, 1); 1430 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1431 1432 TGAREGRB(dc, TGA_REG_EPSR, 1); 1433 1434 rdval = TGARREG(dc, TGA_REG_EPDR); 1435 TGAREGWB(dc, TGA_REG_EPSR, 1); 1436 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1437 1438 return (rdval >> 16) & 0xff; 1439 } 1440 1441 static void 1442 tga_bt463_wr(v, btreg, val) 1443 void *v; 1444 u_int btreg; 1445 u_int8_t val; 1446 { 1447 struct tga_devconfig *dc = v; 1448 1449 /* 1450 * In spite of the 21030 documentation, to set the MPU bus bits for 1451 * a write, you set them in the upper bits of EPDR, not EPSR. 1452 */ 1453 1454 /* 1455 * Strobe CE# (high->low->high) since status and data are latched on 1456 * the falling and rising edges of this active-low signal. 1457 */ 1458 1459 TGAREGWB(dc, TGA_REG_EPDR, 1); 1460 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1461 TGAREGWB(dc, TGA_REG_EPDR, 1); 1462 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1463 TGAREGWB(dc, TGA_REG_EPDR, 1); 1464 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1465 1466 } 1467 1468 static u_int8_t 1469 tga_ramdac_rd(v, btreg) 1470 void *v; 1471 u_int btreg; 1472 { 1473 struct tga_devconfig *dc = v; 1474 tga_reg_t rdval; 1475 1476 if (btreg > BT485_REG_MAX) 1477 panic("tga_ramdac_rd: reg %d out of range", btreg); 1478 1479 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1480 TGAREGWB(dc, TGA_REG_EPSR, 1); 1481 1482 rdval = TGARREG(dc, TGA_REG_EPDR); 1483 return (rdval >> 16) & 0xff; /* XXX */ 1484 } 1485 1486 static u_int8_t 1487 tga2_ramdac_rd(v, btreg) 1488 void *v; 1489 u_int btreg; 1490 { 1491 struct tga_devconfig *dc = v; 1492 bus_space_handle_t ramdac; 1493 u_int8_t retval; 1494 1495 if (btreg > BT485_REG_MAX) 1496 panic("tga_ramdac_rd: reg %d out of range", btreg); 1497 1498 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1499 (0xe << 12) + (btreg << 8), 4, &ramdac); 1500 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1501 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1502 return retval; 1503 } 1504 1505 #include <dev/ic/decmonitors.c> 1506 void tga2_ics9110_wr __P(( 1507 struct tga_devconfig *dc, 1508 int dotclock 1509 )); 1510 1511 struct monitor *tga_getmonitor __P((struct tga_devconfig *dc)); 1512 1513 void 1514 tga2_init(dc) 1515 struct tga_devconfig *dc; 1516 { 1517 struct monitor *m = tga_getmonitor(dc); 1518 1519 /* Deal with the dot clocks. 1520 */ 1521 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1522 /* Set this up as a reference clock for the 1523 * ibm561's PLL. 1524 */ 1525 tga2_ics9110_wr(dc, 14300000); 1526 /* XXX Can't set up the dotclock properly, until such time 1527 * as the RAMDAC is configured. 1528 */ 1529 } else { 1530 /* otherwise the ics9110 is our clock. */ 1531 tga2_ics9110_wr(dc, m->dotclock); 1532 } 1533 #if 0 1534 TGAWREG(dc, TGA_REG_VHCR, 1535 ((m->hbp / 4) << 21) | 1536 ((m->hsync / 4) << 14) | 1537 (((m->hfp - 4) / 4) << 9) | 1538 ((m->cols + 4) / 4)); 1539 #else 1540 TGAWREG(dc, TGA_REG_VHCR, 1541 ((m->hbp / 4) << 21) | 1542 ((m->hsync / 4) << 14) | 1543 (((m->hfp) / 4) << 9) | 1544 ((m->cols) / 4)); 1545 #endif 1546 TGAWREG(dc, TGA_REG_VVCR, 1547 (m->vbp << 22) | 1548 (m->vsync << 16) | 1549 (m->vfp << 11) | 1550 (m->rows)); 1551 TGAWREG(dc, TGA_REG_VVBR, 1); 1552 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1553 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1554 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1555 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1556 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1557 } 1558 1559 void 1560 tga2_ics9110_wr(dc, dotclock) 1561 struct tga_devconfig *dc; 1562 int dotclock; 1563 { 1564 bus_space_handle_t clock; 1565 u_int32_t valU; 1566 int N, M, R, V, X; 1567 int i; 1568 1569 switch (dotclock) { 1570 case 130808000: 1571 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1572 case 119840000: 1573 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1574 case 108180000: 1575 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1576 case 103994000: 1577 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1578 case 175000000: 1579 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1580 case 75000000: 1581 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1582 case 74000000: 1583 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1584 case 69000000: 1585 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1586 case 65000000: 1587 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1588 case 50000000: 1589 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1590 case 40000000: 1591 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1592 case 31500000: 1593 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1594 case 25175000: 1595 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1596 case 135000000: 1597 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1598 case 110000000: 1599 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1600 case 202500000: 1601 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1602 case 14300000: /* this one is just a ref clock */ 1603 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1604 default: 1605 panic("unrecognized clock rate %d", dotclock); 1606 } 1607 1608 /* XXX -- hard coded, bad */ 1609 valU = N | ( M << 7 ) | (V << 14); 1610 valU |= (X << 15) | (R << 17); 1611 valU |= 0x17 << 19; 1612 1613 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1614 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1615 1616 for (i=24; i>0; i--) { 1617 u_int32_t writeval; 1618 1619 writeval = valU & 0x1; 1620 if (i == 1) 1621 writeval |= 0x2; 1622 valU >>= 1; 1623 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1624 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1625 } 1626 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1627 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1628 &clock); /* XXX */ 1629 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1630 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1631 } 1632 1633 struct monitor * 1634 tga_getmonitor(dc) 1635 struct tga_devconfig *dc; 1636 { 1637 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1638 } 1639 1640 unsigned 1641 tga_getdotclock(dc) 1642 struct tga_devconfig *dc; 1643 { 1644 return tga_getmonitor(dc)->dotclock; 1645 }
Cache object: ca98011298280abeccf349862a539bee
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