The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/tgareg.h

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    1 /* $NetBSD: tgareg.h,v 1.4 2000/03/12 05:32:30 nathanw Exp $ */
    2 
    3 /*
    4  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
    5  * All rights reserved.
    6  *
    7  * Author: Chris G. Demetriou
    8  * 
    9  * Permission to use, copy, modify and distribute this software and
   10  * its documentation is hereby granted, provided that both the copyright
   11  * notice and this permission notice appear in all copies of the
   12  * software, derivative works or modified versions, and any portions
   13  * thereof, and that both notices appear in supporting documentation.
   14  * 
   15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
   16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
   17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   18  * 
   19  * Carnegie Mellon requests users of this software to return to
   20  *
   21  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   22  *  School of Computer Science
   23  *  Carnegie Mellon University
   24  *  Pittsburgh PA 15213-3890
   25  *
   26  * any improvements or extensions that they make and grant Carnegie the
   27  * rights to redistribute these changes.
   28  */
   29 
   30 #ifndef _ALPHA_INCLUDE_TGAREG_H_
   31 #define _ALPHA_INCLUDE_TGAREG_H_
   32 
   33 /*
   34  * Device-specific PCI register offsets and contents.
   35  */
   36 
   37 #define TGA_PCIREG_PVRR 0x40            /* PCI Address Extension Register */
   38 
   39 #define TGA_PCIREG_PAER 0x44            /* PCI VGA Redirect Register */
   40 
   41 /*
   42  * TGA Memory Space offsets
   43  */
   44 
   45 #define TGA_MEM_ALTROM  0x0000000       /* 0MB -- Alternate ROM space */
   46 #define TGA2_MEM_EXTDEV 0x0000000       /* 0MB -- External Device Access */
   47 #define TGA_MEM_CREGS   0x0100000       /* 1MB -- Core Registers */
   48 #define TGA_CREGS_SIZE  0x0100000       /* Core registers occupy 1MB */
   49 #define TGA_CREGS_ALIAS 0x0000400       /* Register copies every 1kB */
   50 
   51 #define TGA2_MEM_CLOCK  0x0060000       /* TGA2 Clock access */
   52 #define TGA2_MEM_RAMDAC 0x0080000       /* TGA2 RAMDAC access */
   53 
   54 /* Display and Back Buffers mapped at config-dependent addresses */
   55 
   56 /*
   57  * TGA Core Space register numbers and contents.
   58  */
   59 
   60 typedef u_int32_t tga_reg_t;
   61 
   62 #define TGA_REG_GCBR0   0x000           /* Copy buffer 0 */
   63 #define TGA_REG_GCBR1   0x001           /* Copy buffer 1 */
   64 #define TGA_REG_GCBR2   0x002           /* Copy buffer 2 */
   65 #define TGA_REG_GCBR3   0x003           /* Copy buffer 3 */
   66 #define TGA_REG_GCBR4   0x004           /* Copy buffer 4 */
   67 #define TGA_REG_GCBR5   0x005           /* Copy buffer 5 */
   68 #define TGA_REG_GCBR6   0x006           /* Copy buffer 6 */
   69 #define TGA_REG_GCBR7   0x007           /* Copy buffer 7 */
   70 
   71 #define TGA_REG_GFGR    0x008           /* Foreground */
   72 #define TGA_REG_GBGR    0x009           /* Background */
   73 #define TGA_REG_GPMR    0x00a           /* Plane Mask */
   74 #define TGA_REG_GPXR_S  0x00b           /* Pixel Mask (one-shot) */
   75 #define TGA_REG_GMOR    0x00c           /* Mode */
   76 #define TGA_REG_GOPR    0x00d           /* Raster Operation */
   77 #define TGA_REG_GPSR    0x00e           /* Pixel Shift */
   78 #define TGA_REG_GADR    0x00f           /* Address */
   79 
   80 #define TGA_REG_GB1R    0x010           /* Bresenham 1 */
   81 #define TGA_REG_GB2R    0x011           /* Bresenham 2 */
   82 #define TGA_REG_GB3R    0x012           /* Bresenham 3 */
   83 
   84 #define TGA_REG_GCTR    0x013           /* Continue */
   85 #define TGA_REG_GDER    0x014           /* Deep */
   86 #define TGA_REG_GREV    0x015           /* Start/Version on TGA,
   87                                          * Revision on TGA2 */
   88 #define TGA_REG_GSMR    0x016           /* Stencil Mode */
   89 #define TGA_REG_GPXR_P  0x017           /* Pixel Mask (persistent) */
   90 #define TGA_REG_CCBR    0x018           /* Cursor Base Address */
   91 #define TGA_REG_VHCR    0x019           /* Horizontal Control */
   92 #define TGA_REG_VVCR    0x01a           /* Vertical Control */
   93 #define TGA_REG_VVBR    0x01b           /* Video Base Address */
   94 #define TGA_REG_VVVR    0x01c           /* Video Valid */
   95 #define TGA_REG_CXYR    0x01d           /* Cursor XY */
   96 #define TGA_REG_VSAR    0x01e           /* Video Shift Address */
   97 #define TGA_REG_SISR    0x01f           /* Interrupt Status */
   98 #define TGA_REG_GDAR    0x020           /* Data */
   99 #define TGA_REG_GRIR    0x021           /* Red Increment */
  100 #define TGA_REG_GGIR    0x022           /* Green Increment */
  101 #define TGA_REG_GBIR    0x023           /* Blue Increment */
  102 #define TGA_REG_GZIR_L  0x024           /* Z-increment Low */
  103 #define TGA_REG_GZIR_H  0x025           /* Z-Increment High */
  104 #define TGA_REG_GDBR    0x026           /* DMA Base Address */
  105 #define TGA_REG_GBWR    0x027           /* Bresenham Width */
  106 #define TGA_REG_GZVR_L  0x028           /* Z-value Low */
  107 #define TGA_REG_GZVR_H  0x029           /* Z-value High */
  108 #define TGA_REG_GZBR    0x02a           /* Z-base address */
  109 /*      GADR alias      0x02b */
  110 #define TGA_REG_GRVR    0x02c           /* Red Value */
  111 #define TGA_REG_GGVR    0x02d           /* Green Value */
  112 #define TGA_REG_GBVR    0x02e           /* Blue Value */
  113 #define TGA_REG_GSWR    0x02f           /* Span Width */
  114 #define TGA_REG_EPSR    0x030           /* Pallete and DAC Setup */
  115 
  116 /*      reserved        0x031 - 0x3f */
  117 
  118 #define TGA_REG_GSNR0   0x040           /* Slope-no-go 0 */
  119 #define TGA_REG_GSNR1   0x041           /* Slope-no-go 1 */
  120 #define TGA_REG_GSNR2   0x042           /* Slope-no-go 2 */
  121 #define TGA_REG_GSNR3   0x043           /* Slope-no-go 3 */
  122 #define TGA_REG_GSNR4   0x044           /* Slope-no-go 4 */
  123 #define TGA_REG_GSNR5   0x045           /* Slope-no-go 5 */
  124 #define TGA_REG_GSNR6   0x046           /* Slope-no-go 6 */
  125 #define TGA_REG_GSNR7   0x047           /* Slope-no-go 7 */
  126 
  127 #define TGA_REG_GSLR0   0x048           /* Slope 0 */
  128 #define TGA_REG_GSLR1   0x049           /* Slope 1 */
  129 #define TGA_REG_GSLR2   0x04a           /* Slope 2 */
  130 #define TGA_REG_GSLR3   0x04b           /* Slope 3 */
  131 #define TGA_REG_GSLR4   0x04c           /* Slope 4 */
  132 #define TGA_REG_GSLR5   0x04d           /* Slope 5 */
  133 #define TGA_REG_GSLR6   0x04e           /* Slope 6 */
  134 #define TGA_REG_GSLR7   0x04f           /* Slope 7 */
  135 
  136 #define TGA_REG_GBCR0   0x050           /* Block Color 0 */
  137 #define TGA_REG_GBCR1   0x051           /* Block Color 1 */
  138 #define TGA_REG_GBCR2   0x052           /* Block Color 2 */
  139 #define TGA_REG_GBCR3   0x053           /* Block Color 3 */
  140 #define TGA_REG_GBCR4   0x054           /* Block Color 4 */
  141 #define TGA_REG_GBCR5   0x055           /* Block Color 5 */
  142 #define TGA_REG_GBCR6   0x056           /* Block Color 6 */
  143 #define TGA_REG_GBCR7   0x057           /* Block Color 7 */
  144 
  145 #define TGA_REG_GCSR    0x058           /* Copy 64 Source */
  146 #define TGA_REG_GCDR    0x059           /* Copy 64 Destination */
  147 /*      GC[SD]R aliases 0x05a - 0x05f */
  148 
  149 /*      reserved        0x060 - 0x077 */
  150 
  151 #define TGA_REG_ERWR    0x078           /* EEPROM write */
  152 
  153 /*      reserved        0x079 */
  154 
  155 #define TGA_REG_ECGR    0x07a           /* Clock */
  156 
  157 /*      reserved        0x07b */
  158 
  159 #define TGA_REG_EPDR    0x07c           /* Pallete and DAC Data */
  160 
  161 /*      reserved        0x07d */
  162 
  163 #define TGA_REG_SCSR    0x07e           /* Command Status */
  164 
  165 /*      reserved        0x07f */
  166 
  167 /*
  168  * Video Valid Register
  169  */
  170 #define VVR_VIDEOVALID  0x00000001      /* 0 VGA, 1 TGA2 (TGA2 only) */
  171 #define VVR_BLANK       0x00000002      /* 0 active, 1 blank */
  172 #define VVR_CURSOR      0x00000004      /* 0 disable, 1 enable (TGA2 R/O) */
  173 #define VVR_INTERLACE   0x00000008      /* 0 N/Int, 1 Int. (TGA2 R/O) */
  174 #define VVR_DPMS_MASK   0x00000030      /* See "DMPS mask" below */
  175 #define VVR_DPMS_SHIFT  4
  176 #define VVR_DDC         0x00000040      /* DDC-in pin value (R/O) */
  177 #define VVR_TILED       0x00000400      /* 0 linear, 1 tiled (not on TGA2) */
  178 #define VVR_LDDLY_MASK  0x01ff0000      /* load delay in quad pixel clock ticks
  179                                            (not on TGA2) */
  180 #define VVR_LDDLY_SHIFT 16
  181 
  182 #endif /* _ALPHA_INCLUDE_TGAREG_H_ */

Cache object: 82710a49357fe4585fdd44e03fc832d0


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