FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/tgavar.h
1 /* $NetBSD: tgavar.h,v 1.12 2001/12/12 07:50:05 elric Exp $ */
2
3 /*
4 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30 #include <dev/ic/ramdac.h>
31 #include <dev/pci/tgareg.h>
32 #include <dev/wscons/wsconsio.h>
33 #include <dev/wscons/wscons_raster.h>
34 #include <dev/wscons/wsdisplayvar.h>
35 #include <dev/rasops/rasops.h>
36
37 struct tga_devconfig;
38 struct fbcmap;
39 struct fbcursor;
40 struct fbcurpos;
41
42 struct tga_conf {
43 char *tgac_name; /* name for this board type */
44
45 struct ramdac_funcs *(*ramdac_funcs) __P((void));
46
47 int tgac_phys_depth; /* physical frame buffer depth */
48 vsize_t tgac_cspace_size; /* core space size */
49 vsize_t tgac_vvbr_units; /* what '1' in the VVBR means */
50
51 int tgac_ndbuf; /* number of display buffers */
52 vaddr_t tgac_dbuf[2]; /* display buffer offsets/addresses */
53 vsize_t tgac_dbufsz[2]; /* display buffer sizes */
54
55 int tgac_nbbuf; /* number of display buffers */
56 vaddr_t tgac_bbuf[2]; /* back buffer offsets/addresses */
57 vsize_t tgac_bbufsz[2]; /* back buffer sizes */
58 };
59
60 struct tga_devconfig {
61 bus_space_tag_t dc_memt;
62 bus_space_handle_t dc_memh;
63
64 pcitag_t dc_pcitag; /* PCI tag */
65 bus_addr_t dc_pcipaddr; /* PCI phys addr. */
66
67 bus_space_handle_t dc_regs; /* registers; XXX: need aliases */
68
69 int dc_tga_type; /* the device type; see below */
70 int dc_tga2; /* True if it is a TGA2 */
71 const struct tga_conf *dc_tgaconf; /* device buffer configuration */
72
73 struct ramdac_funcs
74 *dc_ramdac_funcs; /* The RAMDAC functions */
75 struct ramdac_cookie
76 *dc_ramdac_cookie; /* the RAMDAC type; see above */
77
78 vaddr_t dc_vaddr; /* memory space virtual base address */
79
80 int dc_wid; /* width of frame buffer */
81 int dc_ht; /* height of frame buffer */
82 int dc_rowbytes; /* bytes in a FB scan line */
83
84 vaddr_t dc_videobase; /* base of flat frame buffer */
85
86 struct rasops_info dc_rinfo; /* raster display data */
87
88 int dc_blanked; /* currently had video disabled */
89 void *dc_ramdac_private; /* RAMDAC private storage */
90
91 void (*dc_ramdac_intr) __P((void *));
92 int dc_intrenabled; /* can we depend on interrupts yet? */
93 };
94
95 struct tga_softc {
96 struct device sc_dev;
97
98 struct tga_devconfig *sc_dc; /* device configuration */
99 void *sc_intr; /* interrupt handler info */
100 /* XXX should record intr fns/arg */
101
102 int nscreens;
103 };
104
105 #define TGA_TYPE_T8_01 0 /* 8bpp, 1MB */
106 #define TGA_TYPE_T8_02 1 /* 8bpp, 2MB */
107 #define TGA_TYPE_T8_22 2 /* 8bpp, 4MB */
108 #define TGA_TYPE_T8_44 3 /* 8bpp, 8MB */
109 #define TGA_TYPE_T32_04 4 /* 32bpp, 4MB */
110 #define TGA_TYPE_T32_08 5 /* 32bpp, 8MB */
111 #define TGA_TYPE_T32_88 6 /* 32bpp, 16MB */
112 #define TGA_TYPE_POWERSTORM_4D20 7 /* unknown */
113 #define TGA_TYPE_UNKNOWN 8 /* unknown */
114
115 #define DEVICE_IS_TGA(class, id) \
116 (((PCI_VENDOR(id) == PCI_VENDOR_DEC && \
117 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) || \
118 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_PBXGB) ? 10 : 0)
119
120 int tga_cnmatch __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t,
121 pcitag_t));
122 int tga_cnattach __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t,
123 int, int, int));
124
125 int tga_identify __P((struct tga_devconfig *));
126 const struct tga_conf *tga_getconf __P((int));
127
128 int tga_builtin_set_cursor __P((struct tga_devconfig *,
129 struct wsdisplay_cursor *));
130 int tga_builtin_get_cursor __P((struct tga_devconfig *,
131 struct wsdisplay_cursor *));
132 int tga_builtin_set_curpos __P((struct tga_devconfig *,
133 struct wsdisplay_curpos *));
134 int tga_builtin_get_curpos __P((struct tga_devconfig *,
135 struct wsdisplay_curpos *));
136 int tga_builtin_get_curmax __P((struct tga_devconfig *,
137 struct wsdisplay_curpos *));
138
139 /* Read a TGA register */
140 #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \
141 (reg) << 2))
142
143 /* Write a TGA register */
144 #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
145 (reg) << 2, (val))
146
147 /* Write a TGA register at an alternate aliased location */
148 #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
149 (dc)->dc_memt, (dc)->dc_regs, \
150 ((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \
151 (val))
152
153 /* Insert a write barrier */
154 #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \
155 (dc)->dc_memt, (dc)->dc_regs, \
156 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE)
157
158 /* Insert a read barrier */
159 #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \
160 (dc)->dc_memt, (dc)->dc_regs, \
161 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ)
162
163 /* Insert a read/write barrier */
164 #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \
165 (dc)->dc_memt, (dc)->dc_regs, \
166 ((reg) << 2), 4 * (nregs), \
167 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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