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sys/dev/pci/trm.c
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1 /* $NetBSD: trm.c,v 1.14 2003/10/30 01:58:17 simonb Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich@tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.14 2003/10/30 01:58:17 simonb Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsi_message.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/trmreg.h> 77 78 /* 79 * feature of chip set MAX value 80 */ 81 #define TRM_MAX_TARGETS 16 82 #define TRM_MAX_LUNS 8 83 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 #define TRM_MAX_SRB 32 /* XXX */ 85 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 #define TRM_MAX_OFFSET 15 87 #define TRM_MAX_PERIOD 125 88 89 /* 90 * Segment Entry 91 */ 92 struct trm_sg_entry { 93 u_int32_t address; 94 u_int32_t length; 95 }; 96 97 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 99 /* 100 ********************************************************************** 101 * The SEEPROM structure for TRM_S1040 102 ********************************************************************** 103 */ 104 struct nvram_target { 105 u_int8_t config0; /* Target configuration byte 0 */ 106 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 u_int8_t period; /* Target period */ 113 u_int8_t config2; /* Target configuration byte 2 */ 114 u_int8_t config3; /* Target configuration byte 3 */ 115 }; 116 117 struct trm_nvram { 118 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 u_int8_t subclass; /* 4 Sub Class */ 121 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 u_int8_t device_id[2]; /* 7,8 Device ID */ 123 u_int8_t reserved0; /* 9 Reserved */ 124 struct nvram_target target[TRM_MAX_TARGETS]; 125 /* 10,11,12,13 126 * 14,15,16,17 127 * .... 128 * 70,71,72,73 */ 129 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 u_int8_t channel_cfg; /* 75 Channel configuration */ 131 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 u_int8_t delay_time; /* 76 Power on delay time */ 137 u_int8_t max_tag; /* 77 Maximum tags */ 138 u_int8_t reserved1; /* 78 */ 139 u_int8_t boot_target; /* 79 */ 140 u_int8_t boot_lun; /* 80 */ 141 u_int8_t reserved2; /* 81 */ 142 u_int8_t reserved3[44]; /* 82,..125 */ 143 u_int8_t checksum0; /* 126 */ 144 u_int8_t checksum1; /* 127 */ 145 #define TRM_NVRAM_CKSUM 0x1234 146 }; 147 148 /* Nvram Initiater bits definition */ 149 #define MORE2_DRV 0x00000001 150 #define GREATER_1G 0x00000002 151 #define RST_SCSI_BUS 0x00000004 152 #define ACTIVE_NEGATION 0x00000008 153 #define NO_SEEK 0x00000010 154 #define LUN_CHECK 0x00000020 155 156 #define trm_eeprom_wait() DELAY(30) 157 158 /* 159 *----------------------------------------------------------------------- 160 * SCSI Request Block 161 *----------------------------------------------------------------------- 162 */ 163 struct trm_srb { 164 TAILQ_ENTRY(trm_srb) next; 165 166 struct trm_sg_entry *sgentry; 167 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 bus_dmamap_t dmap; 169 bus_size_t sgoffset; /* Xfer buf offset */ 170 171 u_int32_t buflen; /* Total xfer length */ 172 u_int32_t sgaddr; /* SGList physical starting address */ 173 174 int sgcnt; 175 int sgindex; 176 177 int hastat; /* Host Adapter Status */ 178 #define H_STATUS_GOOD 0x00 179 #define H_SEL_TIMEOUT 0x11 180 #define H_OVER_UNDER_RUN 0x12 181 #define H_UNEXP_BUS_FREE 0x13 182 #define H_TARGET_PHASE_F 0x14 183 #define H_INVALID_CCB_OP 0x16 184 #define H_LINK_CCB_BAD 0x17 185 #define H_BAD_TARGET_DIR 0x18 186 #define H_DUPLICATE_CCB 0x19 187 #define H_BAD_CCB_OR_SG 0x1A 188 #define H_ABORT 0xFF 189 int tastat; /* Target SCSI Status Byte */ 190 int flag; /* SRBFlag */ 191 #define AUTO_REQSENSE 0x0001 192 #define PARITY_ERROR 0x0002 193 #define SRB_TIMEOUT 0x0004 194 195 int cmdlen; /* SCSI command length */ 196 u_int8_t cmd[12]; /* SCSI command */ 197 198 u_int8_t tag[2]; 199 }; 200 201 /* 202 * some info about each target and lun on the SCSI bus 203 */ 204 struct trm_linfo { 205 int used; /* number of slots in use */ 206 int avail; /* where to start scanning */ 207 int busy; /* lun in use */ 208 struct trm_srb *untagged; 209 struct trm_srb *queued[TRM_MAX_TAG]; 210 }; 211 212 struct trm_tinfo { 213 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 #define SYNC_NEGO_ENABLE 0x0001 215 #define SYNC_NEGO_DOING 0x0002 216 #define SYNC_NEGO_DONE 0x0004 217 #define WIDE_NEGO_ENABLE 0x0008 218 #define WIDE_NEGO_DOING 0x0010 219 #define WIDE_NEGO_DONE 0x0020 220 #define USE_TAG_QUEUING 0x0040 221 #define NO_RESELECT 0x0080 222 struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 224 u_int8_t config0; /* Target Config */ 225 u_int8_t period; /* Max Period for nego. */ 226 u_int8_t synctl; /* Sync control for reg. */ 227 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 }; 229 230 /* 231 *----------------------------------------------------------------------- 232 * Adapter Control Block 233 *----------------------------------------------------------------------- 234 */ 235 struct trm_softc { 236 struct device sc_dev; 237 238 bus_space_tag_t sc_iot; 239 bus_space_handle_t sc_ioh; 240 bus_dma_tag_t sc_dmat; 241 bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 243 struct trm_srb *sc_actsrb; 244 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 246 TAILQ_HEAD(, trm_srb) sc_freesrb, 247 sc_readysrb; 248 struct trm_srb *sc_srb; /* SRB array */ 249 250 struct trm_sg_entry *sc_sglist; 251 252 int sc_maxid; 253 /* 254 * Link to the generic SCSI driver 255 */ 256 struct scsipi_channel sc_channel; 257 struct scsipi_adapter sc_adapter; 258 259 int sc_id; /* Adapter SCSI Target ID */ 260 261 int sc_state; /* SRB State */ 262 #define TRM_IDLE 0 263 #define TRM_WAIT 1 264 #define TRM_READY 2 265 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 #define TRM_MSGIN 4 267 #define TRM_EXTEND_MSGIN 5 268 #define TRM_COMMAND 6 269 #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 #define TRM_DISCONNECTED 8 271 #define TRM_DATA_XFER 9 272 #define TRM_XFERPAD 10 273 #define TRM_STATUS 11 274 #define TRM_COMPLETED 12 275 #define TRM_ABORT_SENT 13 276 #define TRM_UNEXPECT_RESEL 14 277 278 int sc_phase; /* SCSI phase */ 279 int sc_config; 280 #define HCC_WIDE_CARD 0x01 281 #define HCC_SCSI_RESET 0x02 282 #define HCC_PARITY 0x04 283 #define HCC_AUTOTERM 0x08 284 #define HCC_LOW8TERM 0x10 285 #define HCC_UP8TERM 0x20 286 287 int sc_flag; 288 #define RESET_DEV 0x01 289 #define RESET_DETECT 0x02 290 #define RESET_DONE 0x04 291 #define WAIT_TAGMSG 0x08 /* XXX */ 292 293 int sc_msgcnt; 294 295 int resel_target; /* XXX */ 296 int resel_lun; /* XXX */ 297 298 u_int8_t *sc_msg; 299 u_int8_t sc_msgbuf[6]; 300 }; 301 302 /* 303 * SCSI Status codes not defined in scsi_all.h 304 */ 305 #define SCSI_COND_MET 0x04 /* Condition Met */ 306 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 311 static int trm_probe(struct device *, struct cfdata *, void *); 312 static void trm_attach(struct device *, struct device *, void *); 313 314 static int trm_init(struct trm_softc *); 315 316 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 void *); 318 static void trm_update_xfer_mode(struct trm_softc *, int); 319 static void trm_sched(struct trm_softc *); 320 static int trm_select(struct trm_softc *, struct trm_srb *); 321 static void trm_reset(struct trm_softc *); 322 static void trm_timeout(void *); 323 static int trm_intr(void *); 324 325 static void trm_dataout_phase0(struct trm_softc *, int); 326 static void trm_datain_phase0(struct trm_softc *, int); 327 static void trm_status_phase0(struct trm_softc *); 328 static void trm_msgin_phase0(struct trm_softc *); 329 static void trm_command_phase1(struct trm_softc *); 330 static void trm_status_phase1(struct trm_softc *); 331 static void trm_msgout_phase1(struct trm_softc *); 332 static void trm_msgin_phase1(struct trm_softc *); 333 334 static void trm_dataio_xfer(struct trm_softc *, int); 335 static void trm_disconnect(struct trm_softc *); 336 static void trm_reselect(struct trm_softc *); 337 static void trm_done(struct trm_softc *, struct trm_srb *); 338 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 341 static void trm_scsi_reset_detect(struct trm_softc *); 342 static void trm_reset_scsi_bus(struct trm_softc *); 343 344 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 351 CFATTACH_DECL(trm, sizeof(struct trm_softc), 352 trm_probe, trm_attach, NULL, NULL); 353 354 /* real period: */ 355 static const u_int8_t trm_clock_period[] = { 356 12, /* 48 ns 20.0 MB/sec */ 357 18, /* 72 ns 13.3 MB/sec */ 358 25, /* 100 ns 10.0 MB/sec */ 359 31, /* 124 ns 8.0 MB/sec */ 360 37, /* 148 ns 6.6 MB/sec */ 361 43, /* 172 ns 5.7 MB/sec */ 362 50, /* 200 ns 5.0 MB/sec */ 363 62 /* 248 ns 4.0 MB/sec */ 364 }; 365 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 366 367 static int 368 trm_probe(parent, match, aux) 369 struct device *parent; 370 struct cfdata *match; 371 void *aux; 372 { 373 struct pci_attach_args *pa = aux; 374 375 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 376 switch (PCI_PRODUCT(pa->pa_id)) { 377 case PCI_PRODUCT_TEKRAM2_DC315: 378 return (1); 379 } 380 return (0); 381 } 382 383 /* 384 * attach and init a host adapter 385 */ 386 static void 387 trm_attach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pci_attach_args *const pa = aux; 393 struct trm_softc *sc = (struct trm_softc *)self; 394 bus_space_tag_t iot; 395 bus_space_handle_t ioh; 396 pci_intr_handle_t ih; 397 pcireg_t command; 398 const char *intrstr; 399 400 /* 401 * These cards do not allow memory mapped accesses 402 * pa_pc: chipset tag 403 * pa_tag: pci tag 404 */ 405 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 406 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 407 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 408 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 409 pci_conf_write(pa->pa_pc, pa->pa_tag, 410 PCI_COMMAND_STATUS_REG, command); 411 } 412 /* 413 * mask for get correct base address of pci IO port 414 */ 415 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 416 &iot, &ioh, NULL, NULL)) { 417 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 418 return; 419 } 420 /* 421 * test checksum of eeprom.. & initialize softc... 422 */ 423 sc->sc_iot = iot; 424 sc->sc_ioh = ioh; 425 sc->sc_dmat = pa->pa_dmat; 426 427 if (trm_init(sc) != 0) { 428 /* 429 * Error during initialization! 430 */ 431 printf(": Error during initialization\n"); 432 return; 433 } 434 /* 435 * Now try to attach all the sub-devices 436 */ 437 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 438 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 439 "Ultra Wide SCSI Adapter\n"); 440 else 441 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 442 "Ultra SCSI Adapter\n"); 443 444 /* 445 * Now tell the generic SCSI layer about our bus. 446 * map and establish interrupt 447 */ 448 if (pci_intr_map(pa, &ih)) { 449 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 450 return; 451 } 452 intrstr = pci_intr_string(pa->pa_pc, ih); 453 454 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 455 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 456 if (intrstr != NULL) 457 printf(" at %s", intrstr); 458 printf("\n"); 459 return; 460 } 461 if (intrstr != NULL) 462 printf("%s: interrupting at %s\n", 463 sc->sc_dev.dv_xname, intrstr); 464 465 sc->sc_adapter.adapt_dev = &sc->sc_dev; 466 sc->sc_adapter.adapt_nchannels = 1; 467 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 468 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 469 sc->sc_adapter.adapt_request = trm_scsipi_request; 470 sc->sc_adapter.adapt_minphys = minphys; 471 472 sc->sc_channel.chan_adapter = &sc->sc_adapter; 473 sc->sc_channel.chan_bustype = &scsi_bustype; 474 sc->sc_channel.chan_channel = 0; 475 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 476 sc->sc_channel.chan_nluns = 8; 477 sc->sc_channel.chan_id = sc->sc_id; 478 479 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 480 } 481 482 /* 483 * initialize the internal structures for a given SCSI host 484 */ 485 static int 486 trm_init(sc) 487 struct trm_softc *sc; 488 { 489 bus_space_tag_t iot = sc->sc_iot; 490 bus_space_handle_t ioh = sc->sc_ioh; 491 bus_dma_segment_t seg; 492 struct trm_nvram eeprom; 493 struct trm_srb *srb; 494 struct trm_tinfo *ti; 495 struct nvram_target *tconf; 496 int error, rseg, all_sgsize; 497 int i, target; 498 u_int8_t bval; 499 500 DPRINTF(("\n")); 501 502 /* 503 * allocate the space for all SCSI control blocks (SRB) for DMA memory 504 */ 505 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 506 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 507 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 508 printf(": unable to allocate SCSI REQUEST BLOCKS, " 509 "error = %d\n", error); 510 return (1); 511 } 512 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 513 all_sgsize, (caddr_t *) &sc->sc_sglist, 514 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 515 printf(": unable to map SCSI REQUEST BLOCKS, " 516 "error = %d\n", error); 517 return (1); 518 } 519 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 520 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 521 printf(": unable to create SRB DMA maps, " 522 "error = %d\n", error); 523 return (1); 524 } 525 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 526 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 527 printf(": unable to load SRB DMA maps, " 528 "error = %d\n", error); 529 return (1); 530 } 531 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 532 memset(sc->sc_sglist, 0, all_sgsize); 533 534 /* 535 * EEPROM CHECKSUM 536 */ 537 trm_check_eeprom(sc, &eeprom); 538 539 sc->sc_maxid = 7; 540 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 541 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 542 sc->sc_config |= HCC_WIDE_CARD; 543 sc->sc_maxid = 15; 544 } 545 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 546 sc->sc_config |= HCC_SCSI_RESET; 547 548 sc->sc_actsrb = NULL; 549 sc->sc_id = eeprom.scsi_id; 550 sc->sc_flag = 0; 551 552 /* 553 * initialize and link all device's SRB queues of this adapter 554 */ 555 TAILQ_INIT(&sc->sc_freesrb); 556 TAILQ_INIT(&sc->sc_readysrb); 557 558 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 559 M_DEVBUF, M_NOWAIT|M_ZERO); 560 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 561 if (sc->sc_srb == NULL) { 562 printf(": can not allocate SRB\n"); 563 return (1); 564 } 565 566 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 567 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 568 srb->sgoffset = TRM_SG_SIZE * i; 569 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 570 /* 571 * map all SRB space to SRB_array 572 */ 573 if (bus_dmamap_create(sc->sc_dmat, 574 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 575 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 576 printf(": unable to create DMA transfer map...\n"); 577 free(sc->sc_srb, M_DEVBUF); 578 return (1); 579 } 580 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 581 srb++; 582 } 583 584 /* 585 * initialize all target info structures 586 */ 587 for (target = 0; target < TRM_MAX_TARGETS; target++) { 588 ti = &sc->sc_tinfo[target]; 589 ti->synctl = 0; 590 ti->offset = 0; 591 tconf = &eeprom.target[target]; 592 ti->config0 = tconf->config0; 593 ti->period = trm_clock_period[tconf->period & 0x07]; 594 ti->flag = 0; 595 if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 596 (sc->sc_config & HCC_WIDE_CARD) != 0) 597 ti->flag |= WIDE_NEGO_ENABLE; 598 if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 599 ti->flag |= SYNC_NEGO_ENABLE; 600 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 601 #ifdef notyet 602 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 603 ti->flag |= USE_TAG_QUEUING; 604 #endif 605 } else 606 ti->flag |= NO_RESELECT; 607 608 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 609 target, ti->config0, ti->period)); 610 DPRINTF((", flag = 0x%02x\n", ti->flag)); 611 } 612 613 /* program configuration 0 */ 614 bval = PHASELATCH | INITIATOR | BLOCKRST; 615 if ((sc->sc_config & HCC_PARITY) != 0) 616 bval |= PARITYCHECK; 617 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 618 619 /* program configuration 1 */ 620 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 621 ACTIVE_NEG | ACTIVE_NEGPLUS); 622 623 /* 250ms selection timeout */ 624 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 625 626 /* Mask all interrupts */ 627 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 628 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 629 630 /* Reset SCSI module */ 631 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 632 633 /* program Host ID */ 634 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 635 636 /* set asynchronous transfer */ 637 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 638 639 /* Turn LED control off */ 640 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 641 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 642 643 /* DMA config */ 644 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 645 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 646 647 /* Clear pending interrupt status */ 648 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 649 650 /* Enable SCSI interrupt */ 651 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 652 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 653 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 654 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 655 656 trm_reset(sc); 657 658 return (0); 659 } 660 661 /* 662 * enqueues a SCSI command 663 * called by the higher level SCSI driver 664 */ 665 static void 666 trm_scsipi_request(chan, req, arg) 667 struct scsipi_channel *chan; 668 scsipi_adapter_req_t req; 669 void *arg; 670 { 671 bus_space_tag_t iot; 672 bus_space_handle_t ioh; 673 struct trm_softc *sc; 674 struct trm_srb *srb; 675 struct scsipi_xfer *xs; 676 int error, i, target, lun, s; 677 678 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 679 iot = sc->sc_iot; 680 ioh = sc->sc_ioh; 681 682 switch (req) { 683 case ADAPTER_REQ_RUN_XFER: 684 xs = arg; 685 target = xs->xs_periph->periph_target; 686 lun = xs->xs_periph->periph_lun; 687 DPRINTF(("trm_scsipi_request.....\n")); 688 DPRINTF(("target= %d lun= %d\n", target, lun)); 689 if (xs->xs_control & XS_CTL_RESET) { 690 trm_reset(sc); 691 xs->error = XS_NOERROR | XS_RESET; 692 return; 693 } 694 if (xs->xs_status & XS_STS_DONE) { 695 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 696 xs->xs_status &= ~XS_STS_DONE; 697 } 698 699 s = splbio(); 700 701 /* Get SRB */ 702 srb = TAILQ_FIRST(&sc->sc_freesrb); 703 if (srb != NULL) { 704 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 705 } else { 706 xs->error = XS_RESOURCE_SHORTAGE; 707 scsipi_done(xs); 708 splx(s); 709 return; 710 } 711 712 srb->xs = xs; 713 srb->cmdlen = xs->cmdlen; 714 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 715 716 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 717 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 718 xs->data, xs->datalen, NULL, 719 ((xs->xs_control & XS_CTL_NOSLEEP) ? 720 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 721 BUS_DMA_STREAMING | 722 ((xs->xs_control & XS_CTL_DATA_IN) ? 723 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 724 printf("%s: DMA transfer map unable to load, " 725 "error = %d\n", sc->sc_dev.dv_xname, error); 726 xs->error = XS_DRIVER_STUFFUP; 727 /* 728 * free SRB 729 */ 730 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 731 splx(s); 732 return; 733 } 734 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 735 srb->dmap->dm_mapsize, 736 (xs->xs_control & XS_CTL_DATA_IN) ? 737 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 738 739 /* Set up the scatter gather list */ 740 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 741 srb->sgentry[i].address = 742 htole32(srb->dmap->dm_segs[i].ds_addr); 743 srb->sgentry[i].length = 744 htole32(srb->dmap->dm_segs[i].ds_len); 745 } 746 srb->buflen = xs->datalen; 747 srb->sgcnt = srb->dmap->dm_nsegs; 748 } else { 749 srb->sgentry[0].address = 0; 750 srb->sgentry[0].length = 0; 751 srb->buflen = 0; 752 srb->sgcnt = 0; 753 } 754 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 755 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 756 757 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 758 759 srb->sgindex = 0; 760 srb->hastat = 0; 761 srb->tastat = 0; 762 srb->flag = 0; 763 764 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 765 if (sc->sc_actsrb == NULL) 766 trm_sched(sc); 767 splx(s); 768 769 if ((xs->xs_control & XS_CTL_POLL) != 0) { 770 int timeout = xs->timeout; 771 772 s = splbio(); 773 do { 774 while (--timeout) { 775 DELAY(1000); 776 if (bus_space_read_2(iot, ioh, 777 TRM_SCSI_STATUS) & SCSIINTERRUPT) 778 break; 779 } 780 if (timeout == 0) { 781 trm_timeout(srb); 782 break; 783 } else 784 trm_intr(sc); 785 } while ((xs->xs_status & XS_STS_DONE) == 0); 786 splx(s); 787 } 788 return; 789 790 case ADAPTER_REQ_GROW_RESOURCES: 791 /* XXX Not supported. */ 792 return; 793 794 case ADAPTER_REQ_SET_XFER_MODE: 795 { 796 struct trm_tinfo *ti; 797 struct scsipi_xfer_mode *xm; 798 799 xm = arg; 800 ti = &sc->sc_tinfo[xm->xm_target]; 801 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 802 803 #ifdef notyet 804 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 805 ti->flag |= USE_TAG_QUEUING; 806 else 807 #endif 808 ti->flag &= ~USE_TAG_QUEUING; 809 810 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 811 ti->flag |= WIDE_NEGO_ENABLE; 812 ti->flag &= ~WIDE_NEGO_DONE; 813 } 814 815 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 816 ti->flag |= SYNC_NEGO_ENABLE; 817 ti->flag &= ~SYNC_NEGO_DONE; 818 ti->period = trm_clock_period[0]; 819 } 820 821 /* 822 * If we're not going to negotiate, send the 823 * notification now, since it won't happen later. 824 */ 825 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 826 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 827 trm_update_xfer_mode(sc, xm->xm_target); 828 829 return; 830 } 831 } 832 } 833 834 static void 835 trm_update_xfer_mode(sc, target) 836 struct trm_softc *sc; 837 int target; 838 { 839 struct scsipi_xfer_mode xm; 840 struct trm_tinfo *ti; 841 842 ti = &sc->sc_tinfo[target]; 843 xm.xm_target = target; 844 xm.xm_mode = 0; 845 xm.xm_period = 0; 846 xm.xm_offset = 0; 847 848 if ((ti->synctl & WIDE_SYNC) != 0) 849 xm.xm_mode |= PERIPH_CAP_WIDE16; 850 851 if (ti->period > 0) { 852 xm.xm_mode |= PERIPH_CAP_SYNC; 853 xm.xm_period = ti->period; 854 xm.xm_offset = ti->offset; 855 } 856 857 #ifdef notyet 858 if ((ti->flag & USE_TAG_QUEUING) != 0) 859 xm.xm_mode |= PERIPH_CAP_TQING; 860 #endif 861 862 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 863 } 864 865 static void 866 trm_sched(sc) 867 struct trm_softc *sc; 868 { 869 struct trm_srb *srb; 870 struct scsipi_periph *periph; 871 struct trm_tinfo *ti; 872 struct trm_linfo *li; 873 int s, lun, tag; 874 875 DPRINTF(("trm_sched...\n")); 876 877 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 878 periph = srb->xs->xs_periph; 879 ti = &sc->sc_tinfo[periph->periph_target]; 880 lun = periph->periph_lun; 881 882 /* select type of tag for this command */ 883 if ((ti->flag & NO_RESELECT) != 0 || 884 (ti->flag & USE_TAG_QUEUING) == 0 || 885 (srb->flag & AUTO_REQSENSE) != 0 || 886 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 887 tag = 0; 888 else 889 tag = srb->xs->xs_tag_type; 890 #if 0 891 /* XXX use tags for polled commands? */ 892 if (srb->xs->xs_control & XS_CTL_POLL) 893 tag = 0; 894 #endif 895 896 s = splbio(); 897 li = ti->linfo[lun]; 898 if (li == NULL) { 899 /* initialize lun info */ 900 if ((li = malloc(sizeof(*li), M_DEVBUF, 901 M_NOWAIT|M_ZERO)) == NULL) { 902 splx(s); 903 continue; 904 } 905 ti->linfo[lun] = li; 906 } 907 908 if (tag == 0) { 909 /* try to issue this srb as an un-tagged command */ 910 if (li->untagged == NULL) 911 li->untagged = srb; 912 } 913 if (li->untagged != NULL) { 914 tag = 0; 915 if (li->busy != 1 && li->used == 0) { 916 /* we need to issue the untagged command now */ 917 srb = li->untagged; 918 periph = srb->xs->xs_periph; 919 } else { 920 /* not ready yet */ 921 splx(s); 922 continue; 923 } 924 } 925 srb->tag[0] = tag; 926 if (tag != 0) { 927 li->queued[srb->xs->xs_tag_id] = srb; 928 srb->tag[1] = srb->xs->xs_tag_id; 929 li->used++; 930 } 931 932 if (li->untagged != NULL && li->busy != 1) { 933 li->busy = 1; 934 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 935 sc->sc_actsrb = srb; 936 trm_select(sc, srb); 937 splx(s); 938 break; 939 } 940 if (li->untagged == NULL && tag != 0) { 941 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 942 sc->sc_actsrb = srb; 943 trm_select(sc, srb); 944 splx(s); 945 break; 946 } else 947 splx(s); 948 } 949 } 950 951 static int 952 trm_select(sc, srb) 953 struct trm_softc *sc; 954 struct trm_srb *srb; 955 { 956 bus_space_tag_t iot = sc->sc_iot; 957 bus_space_handle_t ioh = sc->sc_ioh; 958 struct scsipi_periph *periph = srb->xs->xs_periph; 959 int target = periph->periph_target; 960 int lun = periph->periph_lun; 961 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 962 u_int8_t scsicmd; 963 964 DPRINTF(("trm_select.....\n")); 965 966 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 967 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 968 trm_timeout, srb); 969 } 970 971 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 972 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 973 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 974 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 975 /* Flush FIFO */ 976 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 977 DELAY(10); 978 979 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 980 981 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 982 983 if (((ti->flag & WIDE_NEGO_ENABLE) && 984 (ti->flag & WIDE_NEGO_DONE) == 0) || 985 ((ti->flag & SYNC_NEGO_ENABLE) && 986 (ti->flag & SYNC_NEGO_DONE) == 0)) { 987 sc->sc_state = TRM_MSGOUT; 988 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 989 MSG_IDENTIFY(lun, 0)); 990 bus_space_write_multi_1(iot, ioh, 991 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 992 /* it's important for atn stop */ 993 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 994 DO_DATALATCH | DO_HWRESELECT); 995 /* SCSI command */ 996 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 997 DPRINTF(("select with SEL_ATNSTOP\n")); 998 return (0); 999 } 1000 1001 if (srb->tag[0] != 0) { 1002 /* Send identify message */ 1003 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1004 MSG_IDENTIFY(lun, 1)); 1005 /* Send Tag id */ 1006 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1007 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1008 scsicmd = SCMD_SEL_ATN3; 1009 DPRINTF(("select with SEL_ATN3\n")); 1010 } else { 1011 /* Send identify message */ 1012 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1013 MSG_IDENTIFY(lun, 1014 (ti->flag & NO_RESELECT) == 0 && 1015 (srb->flag & AUTO_REQSENSE) == 0 && 1016 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1017 scsicmd = SCMD_SEL_ATN; 1018 DPRINTF(("select with SEL_ATN\n")); 1019 } 1020 sc->sc_state = TRM_START; 1021 1022 /* 1023 * Send CDB ..command block... 1024 */ 1025 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1026 1027 /* 1028 * If trm_select returns 0: current interrupt status 1029 * is interrupt enable. It's said that SCSI processor is 1030 * unoccupied. 1031 */ 1032 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1033 /* SCSI command */ 1034 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1035 return (0); 1036 } 1037 1038 /* 1039 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1040 */ 1041 static void 1042 trm_reset(sc) 1043 struct trm_softc *sc; 1044 { 1045 bus_space_tag_t iot = sc->sc_iot; 1046 bus_space_handle_t ioh = sc->sc_ioh; 1047 int s; 1048 1049 DPRINTF(("trm_reset.........\n")); 1050 1051 s = splbio(); 1052 1053 /* disable SCSI and DMA interrupt */ 1054 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1055 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1056 1057 trm_reset_scsi_bus(sc); 1058 DELAY(100000); 1059 1060 /* Enable SCSI interrupt */ 1061 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1062 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1063 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1064 1065 /* Enable DMA interrupt */ 1066 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1067 1068 /* Clear DMA FIFO */ 1069 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1070 1071 /* Clear SCSI FIFO */ 1072 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1073 1074 sc->sc_actsrb = NULL; 1075 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1076 1077 splx(s); 1078 } 1079 1080 static void 1081 trm_timeout(arg) 1082 void *arg; 1083 { 1084 struct trm_srb *srb = (struct trm_srb *)arg; 1085 struct scsipi_xfer *xs = srb->xs; 1086 struct scsipi_periph *periph = xs->xs_periph; 1087 struct trm_softc *sc; 1088 int s; 1089 1090 if (xs == NULL) 1091 printf("trm_timeout called with xs == NULL\n"); 1092 1093 else { 1094 scsipi_printaddr(xs->xs_periph); 1095 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1096 } 1097 1098 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1099 1100 trm_reset_scsi_bus(sc); 1101 s = splbio(); 1102 srb->flag |= SRB_TIMEOUT; 1103 trm_done(sc, srb); 1104 /* XXX needs more.. */ 1105 splx(s); 1106 } 1107 1108 /* 1109 * Catch an interrupt from the adapter 1110 * Process pending device interrupts. 1111 */ 1112 static int 1113 trm_intr(arg) 1114 void *arg; 1115 { 1116 bus_space_tag_t iot; 1117 bus_space_handle_t ioh; 1118 struct trm_softc *sc; 1119 int intstat, stat; 1120 1121 DPRINTF(("trm_intr......\n")); 1122 sc = (struct trm_softc *)arg; 1123 if (sc == NULL) 1124 return (0); 1125 1126 iot = sc->sc_iot; 1127 ioh = sc->sc_ioh; 1128 1129 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1130 if ((stat & SCSIINTERRUPT) == 0) 1131 return (0); 1132 1133 DPRINTF(("stat = %04x, ", stat)); 1134 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1135 1136 DPRINTF(("intstat=%02x, ", intstat)); 1137 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1138 DPRINTF(("\n")); 1139 trm_disconnect(sc); 1140 return (1); 1141 } 1142 if (intstat & INT_RESELECTED) { 1143 DPRINTF(("\n")); 1144 trm_reselect(sc); 1145 return (1); 1146 } 1147 if (intstat & INT_SCSIRESET) { 1148 DPRINTF(("\n")); 1149 trm_scsi_reset_detect(sc); 1150 return (1); 1151 } 1152 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1153 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1154 sc->sc_phase, sc->sc_state)); 1155 /* 1156 * software sequential machine 1157 */ 1158 1159 /* 1160 * call phase0 functions... "phase entry" handle 1161 * every phase before start transfer 1162 */ 1163 switch (sc->sc_phase) { 1164 case PH_DATA_OUT: 1165 trm_dataout_phase0(sc, stat); 1166 break; 1167 case PH_DATA_IN: 1168 trm_datain_phase0(sc, stat); 1169 break; 1170 case PH_COMMAND: 1171 break; 1172 case PH_STATUS: 1173 trm_status_phase0(sc); 1174 stat = PH_BUS_FREE; 1175 break; 1176 case PH_MSG_OUT: 1177 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1178 sc->sc_state == TRM_ABORT_SENT) 1179 stat = PH_BUS_FREE; 1180 break; 1181 case PH_MSG_IN: 1182 trm_msgin_phase0(sc); 1183 stat = PH_BUS_FREE; 1184 break; 1185 case PH_BUS_FREE: 1186 break; 1187 default: 1188 printf("%s: unexpected phase in trm_intr() phase0\n", 1189 sc->sc_dev.dv_xname); 1190 break; 1191 } 1192 1193 sc->sc_phase = stat & PHASEMASK; 1194 1195 switch (sc->sc_phase) { 1196 case PH_DATA_OUT: 1197 trm_dataio_xfer(sc, XFERDATAOUT); 1198 break; 1199 case PH_DATA_IN: 1200 trm_dataio_xfer(sc, XFERDATAIN); 1201 break; 1202 case PH_COMMAND: 1203 trm_command_phase1(sc); 1204 break; 1205 case PH_STATUS: 1206 trm_status_phase1(sc); 1207 break; 1208 case PH_MSG_OUT: 1209 trm_msgout_phase1(sc); 1210 break; 1211 case PH_MSG_IN: 1212 trm_msgin_phase1(sc); 1213 break; 1214 case PH_BUS_FREE: 1215 break; 1216 default: 1217 printf("%s: unexpected phase in trm_intr() phase1\n", 1218 sc->sc_dev.dv_xname); 1219 break; 1220 } 1221 1222 return (1); 1223 } 1224 return (0); 1225 } 1226 1227 static void 1228 trm_msgout_phase1(sc) 1229 struct trm_softc *sc; 1230 { 1231 bus_space_tag_t iot = sc->sc_iot; 1232 bus_space_handle_t ioh = sc->sc_ioh; 1233 struct trm_srb *srb; 1234 struct scsipi_periph *periph; 1235 struct trm_tinfo *ti; 1236 1237 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1238 1239 srb = sc->sc_actsrb; 1240 1241 /* message out phase */ 1242 if (srb != NULL) { 1243 periph = srb->xs->xs_periph; 1244 ti = &sc->sc_tinfo[periph->periph_target]; 1245 1246 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1247 (ti->flag & WIDE_NEGO_ENABLE)) { 1248 /* send WDTR */ 1249 ti->flag &= ~SYNC_NEGO_DONE; 1250 1251 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1252 sc->sc_msgbuf[1] = MSG_EXTENDED; 1253 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1254 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1255 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1256 sc->sc_msgcnt = 5; 1257 1258 ti->flag |= WIDE_NEGO_DOING; 1259 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1260 (ti->flag & SYNC_NEGO_ENABLE)) { 1261 /* send SDTR */ 1262 int cnt = 0; 1263 1264 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1265 sc->sc_msgbuf[cnt++] = 1266 MSG_IDENTIFY(periph->periph_lun, 0); 1267 1268 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1269 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1270 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1271 sc->sc_msgbuf[cnt++] = ti->period; 1272 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1273 sc->sc_msgcnt = cnt; 1274 ti->flag |= SYNC_NEGO_DOING; 1275 } 1276 } 1277 if (sc->sc_msgcnt == 0) { 1278 sc->sc_msgbuf[0] = MSG_ABORT; 1279 sc->sc_msgcnt = 1; 1280 sc->sc_state = TRM_ABORT_SENT; 1281 } 1282 1283 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1284 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1285 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1286 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1287 1288 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1289 sc->sc_msgbuf, sc->sc_msgcnt); 1290 sc->sc_msgcnt = 0; 1291 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1292 1293 /* it's important for atn stop */ 1294 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1295 1296 /* 1297 * SCSI command 1298 */ 1299 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1300 } 1301 1302 static void 1303 trm_command_phase1(sc) 1304 struct trm_softc *sc; 1305 { 1306 bus_space_tag_t iot = sc->sc_iot; 1307 bus_space_handle_t ioh = sc->sc_ioh; 1308 struct trm_srb *srb; 1309 1310 srb = sc->sc_actsrb; 1311 if (srb == NULL) { 1312 DPRINTF(("trm_command_phase1: no active srb\n")); 1313 return; 1314 } 1315 1316 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1317 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1318 1319 sc->sc_state = TRM_COMMAND; 1320 /* it's important for atn stop */ 1321 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1322 1323 /* 1324 * SCSI command 1325 */ 1326 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1327 } 1328 1329 static void 1330 trm_dataout_phase0(sc, stat) 1331 struct trm_softc *sc; 1332 int stat; 1333 { 1334 bus_space_tag_t iot = sc->sc_iot; 1335 bus_space_handle_t ioh = sc->sc_ioh; 1336 struct trm_srb *srb; 1337 struct scsipi_periph *periph; 1338 struct trm_tinfo *ti; 1339 struct trm_sg_entry *sg; 1340 int sgindex; 1341 u_int32_t xferlen, leftcnt = 0; 1342 1343 if (sc->sc_state == TRM_XFERPAD) 1344 return; 1345 1346 srb = sc->sc_actsrb; 1347 if (srb == NULL) { 1348 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1349 return; 1350 } 1351 periph = srb->xs->xs_periph; 1352 ti = &sc->sc_tinfo[periph->periph_target]; 1353 1354 if ((stat & PARITYERROR) != 0) 1355 srb->flag |= PARITY_ERROR; 1356 1357 if ((stat & SCSIXFERDONE) == 0) { 1358 /* 1359 * when data transfer from DMA FIFO to SCSI FIFO 1360 * if there was some data left in SCSI FIFO 1361 */ 1362 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1363 SCSI_FIFOCNT_MASK; 1364 if (ti->synctl & WIDE_SYNC) 1365 /* 1366 * if WIDE scsi SCSI FIFOCNT unit is word 1367 * so need to * 2 1368 */ 1369 leftcnt <<= 1; 1370 } 1371 /* 1372 * calculate all the residue data that was not yet transferred 1373 * SCSI transfer counter + left in SCSI FIFO data 1374 * 1375 * .....TRM_SCSI_XCNT (24bits) 1376 * The counter always decrements by one for every SCSI 1377 * byte transfer. 1378 * .....TRM_SCSI_FIFOCNT ( 5bits) 1379 * The counter is SCSI FIFO offset counter 1380 */ 1381 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1382 if (leftcnt == 1) { 1383 leftcnt = 0; 1384 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1385 } 1386 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1387 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1388 DMAXFERCOMP) == 0) 1389 ; /* XXX needs timeout */ 1390 1391 srb->buflen = 0; 1392 } else { 1393 /* Update SG list */ 1394 1395 /* 1396 * if transfer not yet complete 1397 * there were some data residue in SCSI FIFO or 1398 * SCSI transfer counter not empty 1399 */ 1400 if (srb->buflen != leftcnt) { 1401 /* data that had transferred length */ 1402 xferlen = srb->buflen - leftcnt; 1403 1404 /* next time to be transferred length */ 1405 srb->buflen = leftcnt; 1406 1407 /* 1408 * parsing from last time disconnect sgindex 1409 */ 1410 sg = srb->sgentry + srb->sgindex; 1411 for (sgindex = srb->sgindex; 1412 sgindex < srb->sgcnt; 1413 sgindex++, sg++) { 1414 /* 1415 * find last time which SG transfer 1416 * be disconnect 1417 */ 1418 if (xferlen >= le32toh(sg->length)) 1419 xferlen -= le32toh(sg->length); 1420 else { 1421 /* 1422 * update last time 1423 * disconnected SG list 1424 */ 1425 /* residue data length */ 1426 sg->length = 1427 htole32(le32toh(sg->length) 1428 - xferlen); 1429 /* residue data pointer */ 1430 sg->address = 1431 htole32(le32toh(sg->address) 1432 + xferlen); 1433 srb->sgindex = sgindex; 1434 break; 1435 } 1436 } 1437 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1438 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1439 } 1440 } 1441 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1442 } 1443 1444 static void 1445 trm_datain_phase0(sc, stat) 1446 struct trm_softc *sc; 1447 int stat; 1448 { 1449 bus_space_tag_t iot = sc->sc_iot; 1450 bus_space_handle_t ioh = sc->sc_ioh; 1451 struct trm_srb *srb; 1452 struct trm_sg_entry *sg; 1453 int sgindex; 1454 u_int32_t xferlen, leftcnt = 0; 1455 1456 if (sc->sc_state == TRM_XFERPAD) 1457 return; 1458 1459 srb = sc->sc_actsrb; 1460 if (srb == NULL) { 1461 DPRINTF(("trm_datain_phase0: no active srb\n")); 1462 return; 1463 } 1464 1465 if (stat & PARITYERROR) 1466 srb->flag |= PARITY_ERROR; 1467 1468 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1469 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1470 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1471 DMAXFERCOMP) == 0) 1472 ; /* XXX needs timeout */ 1473 1474 srb->buflen = 0; 1475 } else { /* phase changed */ 1476 /* 1477 * parsing the case: 1478 * when a transfer not yet complete 1479 * but be disconnected by upper layer 1480 * if transfer not yet complete 1481 * there were some data residue in SCSI FIFO or 1482 * SCSI transfer counter not empty 1483 */ 1484 if (srb->buflen != leftcnt) { 1485 /* 1486 * data that had transferred length 1487 */ 1488 xferlen = srb->buflen - leftcnt; 1489 1490 /* 1491 * next time to be transferred length 1492 */ 1493 srb->buflen = leftcnt; 1494 1495 /* 1496 * parsing from last time disconnect sgindex 1497 */ 1498 sg = srb->sgentry + srb->sgindex; 1499 for (sgindex = srb->sgindex; 1500 sgindex < srb->sgcnt; 1501 sgindex++, sg++) { 1502 /* 1503 * find last time which SG transfer 1504 * be disconnect 1505 */ 1506 if (xferlen >= le32toh(sg->length)) 1507 xferlen -= le32toh(sg->length); 1508 else { 1509 /* 1510 * update last time 1511 * disconnected SG list 1512 */ 1513 /* residue data length */ 1514 sg->length = 1515 htole32(le32toh(sg->length) 1516 - xferlen); 1517 /* residue data pointer */ 1518 sg->address = 1519 htole32(le32toh(sg->address) 1520 + xferlen); 1521 srb->sgindex = sgindex; 1522 break; 1523 } 1524 } 1525 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1526 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1527 } 1528 } 1529 } 1530 1531 static void 1532 trm_dataio_xfer(sc, iodir) 1533 struct trm_softc *sc; 1534 int iodir; 1535 { 1536 bus_space_tag_t iot = sc->sc_iot; 1537 bus_space_handle_t ioh = sc->sc_ioh; 1538 struct trm_srb *srb; 1539 struct scsipi_periph *periph; 1540 struct trm_tinfo *ti; 1541 1542 srb = sc->sc_actsrb; 1543 if (srb == NULL) { 1544 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1545 return; 1546 } 1547 periph = srb->xs->xs_periph; 1548 ti = &sc->sc_tinfo[periph->periph_target]; 1549 1550 if (srb->sgindex < srb->sgcnt) { 1551 if (srb->buflen > 0) { 1552 /* 1553 * load what physical address of Scatter/Gather 1554 * list table want to be transfer 1555 */ 1556 sc->sc_state = TRM_DATA_XFER; 1557 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1558 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1559 srb->sgaddr + 1560 srb->sgindex * sizeof(struct trm_sg_entry)); 1561 /* 1562 * load how many bytes in the Scatter/Gather list table 1563 */ 1564 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1565 (srb->sgcnt - srb->sgindex) 1566 * sizeof(struct trm_sg_entry)); 1567 /* 1568 * load total xfer length (24bits) max value 16Mbyte 1569 */ 1570 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1571 /* Start DMA transfer */ 1572 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1573 iodir | SGXFER); 1574 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1575 STARTDMAXFER); 1576 1577 /* Start SCSI transfer */ 1578 /* it's important for atn stop */ 1579 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1580 DO_DATALATCH); 1581 1582 /* 1583 * SCSI command 1584 */ 1585 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1586 (iodir == XFERDATAOUT) ? 1587 SCMD_DMA_OUT : SCMD_DMA_IN); 1588 } else { /* xfer pad */ 1589 if (srb->sgcnt) { 1590 srb->hastat = H_OVER_UNDER_RUN; 1591 } 1592 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1593 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1594 1595 if (iodir == XFERDATAOUT) 1596 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1597 else 1598 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1599 1600 sc->sc_state = TRM_XFERPAD; 1601 /* it's important for atn stop */ 1602 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1603 DO_DATALATCH); 1604 1605 /* 1606 * SCSI command 1607 */ 1608 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1609 (iodir == XFERDATAOUT) ? 1610 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1611 } 1612 } 1613 } 1614 1615 static void 1616 trm_status_phase0(sc) 1617 struct trm_softc *sc; 1618 { 1619 bus_space_tag_t iot = sc->sc_iot; 1620 bus_space_handle_t ioh = sc->sc_ioh; 1621 struct trm_srb *srb; 1622 1623 srb = sc->sc_actsrb; 1624 if (srb == NULL) { 1625 DPRINTF(("trm_status_phase0: no active srb\n")); 1626 return; 1627 } 1628 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1629 sc->sc_state = TRM_COMPLETED; 1630 /* it's important for atn stop */ 1631 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1632 1633 /* 1634 * SCSI command 1635 */ 1636 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1637 } 1638 1639 static void 1640 trm_status_phase1(sc) 1641 struct trm_softc *sc; 1642 { 1643 bus_space_tag_t iot = sc->sc_iot; 1644 bus_space_handle_t ioh = sc->sc_ioh; 1645 1646 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1647 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1648 & SCSI_FIFO_EMPTY) == 0) 1649 bus_space_write_2(iot, ioh, 1650 TRM_SCSI_CONTROL, DO_CLRFIFO); 1651 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1652 & DMA_FIFO_EMPTY) == 0) 1653 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1654 } else { 1655 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1656 & DMA_FIFO_EMPTY) == 0) 1657 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1658 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1659 & SCSI_FIFO_EMPTY) == 0) 1660 bus_space_write_2(iot, ioh, 1661 TRM_SCSI_CONTROL, DO_CLRFIFO); 1662 } 1663 sc->sc_state = TRM_STATUS; 1664 /* it's important for atn stop */ 1665 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1666 1667 /* 1668 * SCSI command 1669 */ 1670 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1671 } 1672 1673 static void 1674 trm_msgin_phase0(sc) 1675 struct trm_softc *sc; 1676 { 1677 bus_space_tag_t iot = sc->sc_iot; 1678 bus_space_handle_t ioh = sc->sc_ioh; 1679 struct trm_srb *srb; 1680 struct scsipi_periph *periph; 1681 struct trm_tinfo *ti; 1682 int index; 1683 u_int8_t msgin_code; 1684 1685 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1686 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1687 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1688 switch (msgin_code) { 1689 case MSG_DISCONNECT: 1690 sc->sc_state = TRM_DISCONNECTED; 1691 break; 1692 1693 case MSG_SAVEDATAPOINTER: 1694 break; 1695 1696 case MSG_EXTENDED: 1697 case MSG_SIMPLE_Q_TAG: 1698 case MSG_HEAD_OF_Q_TAG: 1699 case MSG_ORDERED_Q_TAG: 1700 sc->sc_state = TRM_EXTEND_MSGIN; 1701 /* extended message (01h) */ 1702 sc->sc_msgbuf[0] = msgin_code; 1703 1704 sc->sc_msgcnt = 1; 1705 /* extended message length (n) */ 1706 sc->sc_msg = &sc->sc_msgbuf[1]; 1707 1708 break; 1709 case MSG_MESSAGE_REJECT: 1710 /* Reject message */ 1711 srb = sc->sc_actsrb; 1712 if (srb == NULL) { 1713 DPRINTF(("trm_msgin_phase0: " 1714 " message reject without actsrb\n")); 1715 break; 1716 } 1717 periph = srb->xs->xs_periph; 1718 ti = &sc->sc_tinfo[periph->periph_target]; 1719 1720 if (ti->flag & WIDE_NEGO_ENABLE) { 1721 /* do wide nego reject */ 1722 ti->flag |= WIDE_NEGO_DONE; 1723 ti->flag &= 1724 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1725 if ((ti->flag & SYNC_NEGO_ENABLE) && 1726 (ti->flag & SYNC_NEGO_DONE) == 0) { 1727 /* Set ATN, in case ATN was clear */ 1728 sc->sc_state = TRM_MSGOUT; 1729 bus_space_write_2(iot, ioh, 1730 TRM_SCSI_CONTROL, DO_SETATN); 1731 } else 1732 /* Clear ATN */ 1733 bus_space_write_2(iot, ioh, 1734 TRM_SCSI_CONTROL, DO_CLRATN); 1735 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1736 /* do sync nego reject */ 1737 bus_space_write_2(iot, ioh, 1738 TRM_SCSI_CONTROL, DO_CLRATN); 1739 if (ti->flag & SYNC_NEGO_DOING) { 1740 ti->flag &=~(SYNC_NEGO_ENABLE | 1741 SYNC_NEGO_DONE); 1742 ti->synctl = 0; 1743 ti->offset = 0; 1744 bus_space_write_1(iot, ioh, 1745 TRM_SCSI_SYNC, ti->synctl); 1746 bus_space_write_1(iot, ioh, 1747 TRM_SCSI_OFFSET, ti->offset); 1748 } 1749 } 1750 break; 1751 1752 case MSG_IGN_WIDE_RESIDUE: 1753 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1754 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1755 break; 1756 1757 default: 1758 /* 1759 * Restore data pointer message 1760 * Save data pointer message 1761 * Completion message 1762 * NOP message 1763 */ 1764 break; 1765 } 1766 } else { 1767 /* 1768 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1769 * Parsing incoming extented messages 1770 */ 1771 *sc->sc_msg++ = msgin_code; 1772 sc->sc_msgcnt++; 1773 1774 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1775 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1776 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1777 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1778 1779 switch (sc->sc_msgbuf[0]) { 1780 case MSG_SIMPLE_Q_TAG: 1781 case MSG_HEAD_OF_Q_TAG: 1782 case MSG_ORDERED_Q_TAG: 1783 /* 1784 * is QUEUE tag message : 1785 * 1786 * byte 0: 1787 * HEAD QUEUE TAG (20h) 1788 * ORDERED QUEUE TAG (21h) 1789 * SIMPLE QUEUE TAG (22h) 1790 * byte 1: 1791 * Queue tag (00h - FFh) 1792 */ 1793 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1794 /* XXX XXX XXX */ 1795 struct trm_linfo *li; 1796 int tagid; 1797 1798 sc->sc_flag &= ~WAIT_TAGMSG; 1799 tagid = sc->sc_msgbuf[1]; 1800 ti = &sc->sc_tinfo[sc->resel_target]; 1801 li = ti->linfo[sc->resel_lun]; 1802 srb = li->queued[tagid]; 1803 if (srb != NULL) { 1804 sc->sc_actsrb = srb; 1805 sc->sc_state = TRM_DATA_XFER; 1806 break; 1807 } else { 1808 printf("%s: invalid tag id\n", 1809 sc->sc_dev.dv_xname); 1810 } 1811 1812 sc->sc_state = TRM_UNEXPECT_RESEL; 1813 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1814 sc->sc_msgcnt = 1; 1815 bus_space_write_2(iot, ioh, 1816 TRM_SCSI_CONTROL, DO_SETATN); 1817 } else 1818 sc->sc_state = TRM_IDLE; 1819 break; 1820 1821 case MSG_EXTENDED: 1822 srb = sc->sc_actsrb; 1823 if (srb == NULL) { 1824 DPRINTF(("trm_msgin_phase0: " 1825 "extended message without actsrb\n")); 1826 break; 1827 } 1828 periph = srb->xs->xs_periph; 1829 ti = &sc->sc_tinfo[periph->periph_target]; 1830 1831 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1832 sc->sc_msgcnt == 4) { 1833 /* 1834 * is Wide data xfer Extended message : 1835 * ====================================== 1836 * WIDE DATA TRANSFER REQUEST 1837 * ====================================== 1838 * byte 0 : Extended message (01h) 1839 * byte 1 : Extended message length (02h) 1840 * byte 2 : WIDE DATA TRANSFER code (03h) 1841 * byte 3 : Transfer width exponent 1842 */ 1843 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1844 /* Length is wrong, reject it */ 1845 ti->flag &= ~(WIDE_NEGO_ENABLE | 1846 WIDE_NEGO_DONE); 1847 sc->sc_state = TRM_MSGOUT; 1848 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1849 sc->sc_msgcnt = 1; 1850 bus_space_write_2(iot, ioh, 1851 TRM_SCSI_CONTROL, DO_SETATN); 1852 break; 1853 } 1854 1855 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1856 sc->sc_msgbuf[3] = 1857 MSG_EXT_WDTR_BUS_8_BIT; 1858 1859 if (sc->sc_msgbuf[3] > 1860 MSG_EXT_WDTR_BUS_32_BIT) { 1861 /* reject_msg: */ 1862 ti->flag &= ~(WIDE_NEGO_ENABLE | 1863 WIDE_NEGO_DONE); 1864 sc->sc_state = TRM_MSGOUT; 1865 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1866 sc->sc_msgcnt = 1; 1867 bus_space_write_2(iot, ioh, 1868 TRM_SCSI_CONTROL, DO_SETATN); 1869 break; 1870 } 1871 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1872 /* do 16 bits */ 1873 sc->sc_msgbuf[3] = 1874 MSG_EXT_WDTR_BUS_16_BIT; 1875 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1876 ti->flag |= WIDE_NEGO_DONE; 1877 ti->flag &= ~(SYNC_NEGO_DONE | 1878 WIDE_NEGO_ENABLE); 1879 if (sc->sc_msgbuf[3] != 1880 MSG_EXT_WDTR_BUS_8_BIT) 1881 /* is Wide data xfer */ 1882 ti->synctl |= WIDE_SYNC; 1883 trm_update_xfer_mode(sc, 1884 periph->periph_target); 1885 } 1886 1887 sc->sc_state = TRM_MSGOUT; 1888 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1889 DO_SETATN); 1890 break; 1891 1892 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1893 sc->sc_msgcnt == 5) { 1894 /* 1895 * is 8bit transfer Extended message : 1896 * ================================= 1897 * SYNCHRONOUS DATA TRANSFER REQUEST 1898 * ================================= 1899 * byte 0 : Extended message (01h) 1900 * byte 1 : Extended message length (03) 1901 * byte 2 : SYNC DATA TRANSFER code (01h) 1902 * byte 3 : Transfer period factor 1903 * byte 4 : REQ/ACK offset 1904 */ 1905 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1906 /* reject_msg */ 1907 sc->sc_state = TRM_MSGOUT; 1908 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1909 sc->sc_msgcnt = 1; 1910 bus_space_write_2(iot, ioh, 1911 TRM_SCSI_CONTROL, DO_SETATN); 1912 break; 1913 } 1914 1915 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1916 ti->flag &= 1917 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1918 ti->flag |= SYNC_NEGO_DONE; 1919 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1920 sc->sc_msgbuf[3] = 0; 1921 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1922 sc->sc_msgbuf[4] = 1923 TRM_MAX_OFFSET; 1924 1925 if (sc->sc_msgbuf[3] == 0 || 1926 sc->sc_msgbuf[4] == 0) { 1927 /* set async */ 1928 ti->synctl = 0; 1929 ti->offset = 0; 1930 } else { 1931 /* set sync */ 1932 /* Transfer period factor */ 1933 ti->period = sc->sc_msgbuf[3]; 1934 /* REQ/ACK offset */ 1935 ti->offset = sc->sc_msgbuf[4]; 1936 for (index = 0; 1937 index < NPERIOD; 1938 index++) 1939 if (ti->period <= 1940 trm_clock_period[ 1941 index]) 1942 break; 1943 1944 ti->synctl |= ALT_SYNC | index; 1945 } 1946 /* 1947 * program SCSI control register 1948 */ 1949 bus_space_write_1(iot, ioh, 1950 TRM_SCSI_SYNC, ti->synctl); 1951 bus_space_write_1(iot, ioh, 1952 TRM_SCSI_OFFSET, ti->offset); 1953 trm_update_xfer_mode(sc, 1954 periph->periph_target); 1955 } 1956 sc->sc_state = TRM_IDLE; 1957 } 1958 break; 1959 default: 1960 break; 1961 } 1962 } 1963 1964 /* it's important for atn stop */ 1965 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1966 1967 /* 1968 * SCSI command 1969 */ 1970 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1971 } 1972 1973 static void 1974 trm_msgin_phase1(sc) 1975 struct trm_softc *sc; 1976 { 1977 bus_space_tag_t iot = sc->sc_iot; 1978 bus_space_handle_t ioh = sc->sc_ioh; 1979 1980 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1981 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1982 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1983 sc->sc_state = TRM_MSGIN; 1984 } 1985 1986 /* it's important for atn stop */ 1987 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1988 1989 /* 1990 * SCSI command 1991 */ 1992 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1993 } 1994 1995 static void 1996 trm_disconnect(sc) 1997 struct trm_softc *sc; 1998 { 1999 bus_space_tag_t iot = sc->sc_iot; 2000 bus_space_handle_t ioh = sc->sc_ioh; 2001 struct trm_srb *srb; 2002 int s; 2003 2004 s = splbio(); 2005 2006 srb = sc->sc_actsrb; 2007 DPRINTF(("trm_disconnect...............\n")); 2008 2009 if (srb == NULL) { 2010 DPRINTF(("trm_disconnect: no active srb\n")); 2011 DELAY(1000); /* 1 msec */ 2012 2013 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2014 DO_CLRFIFO | DO_HWRESELECT); 2015 return; 2016 } 2017 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2018 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2019 DO_CLRFIFO | DO_HWRESELECT); 2020 DELAY(100); 2021 2022 switch (sc->sc_state) { 2023 case TRM_UNEXPECT_RESEL: 2024 sc->sc_state = TRM_IDLE; 2025 break; 2026 2027 case TRM_ABORT_SENT: 2028 goto finish; 2029 2030 case TRM_START: 2031 case TRM_MSGOUT: 2032 { 2033 /* Selection time out - discard all LUNs if empty */ 2034 struct scsipi_periph *periph; 2035 struct trm_tinfo *ti; 2036 struct trm_linfo *li; 2037 int lun; 2038 2039 DPRINTF(("selection timeout\n")); 2040 2041 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2042 2043 periph = srb->xs->xs_periph; 2044 ti = &sc->sc_tinfo[periph->periph_target]; 2045 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2046 li = ti->linfo[lun]; 2047 if (li != NULL && 2048 li->untagged == NULL && li->used == 0) { 2049 ti->linfo[lun] = NULL; 2050 free(li, M_DEVBUF); 2051 } 2052 } 2053 } 2054 goto finish; 2055 2056 case TRM_DISCONNECTED: 2057 sc->sc_actsrb = NULL; 2058 sc->sc_state = TRM_IDLE; 2059 goto sched; 2060 2061 case TRM_COMPLETED: 2062 goto finish; 2063 } 2064 2065 out: 2066 splx(s); 2067 return; 2068 2069 finish: 2070 sc->sc_state = TRM_IDLE; 2071 trm_done(sc, srb); 2072 goto out; 2073 2074 sched: 2075 trm_sched(sc); 2076 goto out; 2077 } 2078 2079 static void 2080 trm_reselect(sc) 2081 struct trm_softc *sc; 2082 { 2083 bus_space_tag_t iot = sc->sc_iot; 2084 bus_space_handle_t ioh = sc->sc_ioh; 2085 struct trm_tinfo *ti; 2086 struct trm_linfo *li; 2087 int target, lun; 2088 2089 DPRINTF(("trm_reselect.................\n")); 2090 2091 if (sc->sc_actsrb != NULL) { 2092 /* arbitration lost but reselection win */ 2093 sc->sc_state = TRM_READY; 2094 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2095 ti = &sc->sc_tinfo[target]; 2096 } else { 2097 /* Read Reselected Target Id and LUN */ 2098 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2099 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2100 ti = &sc->sc_tinfo[target]; 2101 li = ti->linfo[lun]; 2102 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2103 2104 /* 2105 * Check to see if we are running an un-tagged command. 2106 * Otherwise ack the IDENTIFY and wait for a tag message. 2107 */ 2108 if (li != NULL) { 2109 if (li->untagged != NULL && li->busy) { 2110 sc->sc_actsrb = li->untagged; 2111 sc->sc_state = TRM_DATA_XFER; 2112 } else { 2113 sc->resel_target = target; 2114 sc->resel_lun = lun; 2115 /* XXX XXX XXX */ 2116 sc->sc_flag |= WAIT_TAGMSG; 2117 } 2118 } 2119 2120 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2121 sc->sc_actsrb == NULL) { 2122 printf("%s: reselect from target %d lun %d " 2123 "without nexus; sending abort\n", 2124 sc->sc_dev.dv_xname, target, lun); 2125 sc->sc_state = TRM_UNEXPECT_RESEL; 2126 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2127 sc->sc_msgcnt = 1; 2128 bus_space_write_2(iot, ioh, 2129 TRM_SCSI_CONTROL, DO_SETATN); 2130 } 2131 } 2132 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2133 /* 2134 * Program HA ID, target ID, period and offset 2135 */ 2136 /* target ID */ 2137 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2138 2139 /* host ID */ 2140 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2141 2142 /* period */ 2143 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2144 2145 /* offset */ 2146 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2147 2148 /* it's important for atn stop */ 2149 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2150 /* 2151 * SCSI command 2152 */ 2153 /* to rls the /ACK signal */ 2154 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2155 } 2156 2157 /* 2158 * Complete execution of a SCSI command 2159 * Signal completion to the generic SCSI driver 2160 */ 2161 static void 2162 trm_done(sc, srb) 2163 struct trm_softc *sc; 2164 struct trm_srb *srb; 2165 { 2166 struct scsipi_xfer *xs = srb->xs; 2167 2168 DPRINTF(("trm_done..................\n")); 2169 2170 if (xs == NULL) 2171 return; 2172 2173 if ((xs->xs_control & XS_CTL_POLL) == 0) 2174 callout_stop(&xs->xs_callout); 2175 2176 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2177 srb->flag & AUTO_REQSENSE) { 2178 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2179 srb->dmap->dm_mapsize, 2180 ((xs->xs_control & XS_CTL_DATA_IN) || 2181 (srb->flag & AUTO_REQSENSE)) ? 2182 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2183 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2184 } 2185 2186 /* 2187 * target status 2188 */ 2189 xs->status = srb->tastat; 2190 2191 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2192 2193 switch (xs->status) { 2194 case SCSI_OK: 2195 /* 2196 * process initiator status...... 2197 * Adapter (initiator) status 2198 */ 2199 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2200 printf("%s: over/under run error\n", 2201 sc->sc_dev.dv_xname); 2202 srb->tastat = 0; 2203 /* Illegal length (over/under run) */ 2204 xs->error = XS_DRIVER_STUFFUP; 2205 } else if ((srb->flag & PARITY_ERROR) != 0) { 2206 printf("%s: parity error\n", 2207 sc->sc_dev.dv_xname); 2208 /* Driver failed to perform operation */ 2209 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2210 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2211 xs->resid = srb->buflen; 2212 xs->error = XS_TIMEOUT; 2213 } else { 2214 /* No error */ 2215 xs->resid = srb->buflen; 2216 srb->hastat = 0; 2217 if (srb->flag & AUTO_REQSENSE) { 2218 /* there is no error, (sense is invalid) */ 2219 xs->error = XS_SENSE; 2220 } else { 2221 srb->tastat = 0; 2222 xs->error = XS_NOERROR; 2223 } 2224 } 2225 break; 2226 2227 case SCSI_CHECK: 2228 if ((srb->flag & AUTO_REQSENSE) != 0 || 2229 trm_request_sense(sc, srb) != 0) { 2230 printf("%s: request sense failed\n", 2231 sc->sc_dev.dv_xname); 2232 xs->error = XS_DRIVER_STUFFUP; 2233 break; 2234 } 2235 xs->error = XS_SENSE; 2236 return; 2237 2238 case SCSI_SEL_TIMEOUT: 2239 srb->hastat = H_SEL_TIMEOUT; 2240 srb->tastat = 0; 2241 xs->error = XS_SELTIMEOUT; 2242 break; 2243 2244 case SCSI_QUEUE_FULL: 2245 case SCSI_BUSY: 2246 xs->error = XS_BUSY; 2247 break; 2248 2249 case SCSI_RESV_CONFLICT: 2250 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2251 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2252 xs->error = XS_BUSY; 2253 break; 2254 2255 default: 2256 srb->hastat = 0; 2257 printf("%s: trm_done(): unknown status = %02x\n", 2258 sc->sc_dev.dv_xname, xs->status); 2259 xs->error = XS_DRIVER_STUFFUP; 2260 break; 2261 } 2262 2263 trm_dequeue(sc, srb); 2264 if (srb == sc->sc_actsrb) { 2265 sc->sc_actsrb = NULL; 2266 trm_sched(sc); 2267 } 2268 2269 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2270 2271 /* Notify cmd done */ 2272 scsipi_done(xs); 2273 } 2274 2275 static int 2276 trm_request_sense(sc, srb) 2277 struct trm_softc *sc; 2278 struct trm_srb *srb; 2279 { 2280 struct scsipi_xfer *xs; 2281 struct scsipi_periph *periph; 2282 struct trm_tinfo *ti; 2283 struct trm_linfo *li; 2284 struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2285 int error; 2286 2287 DPRINTF(("trm_request_sense...\n")); 2288 2289 xs = srb->xs; 2290 periph = xs->xs_periph; 2291 2292 srb->flag |= AUTO_REQSENSE; 2293 2294 /* Status of initiator/target */ 2295 srb->hastat = 0; 2296 srb->tastat = 0; 2297 2298 ss->opcode = REQUEST_SENSE; 2299 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2300 ss->unused[0] = ss->unused[1] = 0; 2301 ss->length = sizeof(struct scsipi_sense_data); 2302 ss->control = 0; 2303 2304 srb->buflen = sizeof(struct scsipi_sense_data); 2305 srb->sgcnt = 1; 2306 srb->sgindex = 0; 2307 srb->cmdlen = sizeof(struct scsipi_sense); 2308 2309 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2310 &xs->sense.scsi_sense, srb->buflen, NULL, 2311 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2312 return error; 2313 } 2314 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2315 srb->buflen, BUS_DMASYNC_PREREAD); 2316 2317 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2318 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2319 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2320 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2321 2322 ti = &sc->sc_tinfo[periph->periph_target]; 2323 li = ti->linfo[periph->periph_lun]; 2324 if (li->busy > 0) 2325 li->busy = 0; 2326 trm_dequeue(sc, srb); 2327 li->untagged = srb; /* must be executed first to fix C/A */ 2328 li->busy = 2; 2329 2330 if (srb == sc->sc_actsrb) 2331 trm_select(sc, srb); 2332 else { 2333 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2334 if (sc->sc_actsrb == NULL) 2335 trm_sched(sc); 2336 } 2337 return 0; 2338 } 2339 2340 static void 2341 trm_dequeue(sc, srb) 2342 struct trm_softc *sc; 2343 struct trm_srb *srb; 2344 { 2345 struct scsipi_periph *periph; 2346 struct trm_tinfo *ti; 2347 struct trm_linfo *li; 2348 2349 periph = srb->xs->xs_periph; 2350 ti = &sc->sc_tinfo[periph->periph_target]; 2351 li = ti->linfo[periph->periph_lun]; 2352 2353 if (li->untagged == srb) { 2354 li->busy = 0; 2355 li->untagged = NULL; 2356 } 2357 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2358 li->queued[srb->tag[1]] = NULL; 2359 li->used--; 2360 } 2361 } 2362 2363 static void 2364 trm_reset_scsi_bus(sc) 2365 struct trm_softc *sc; 2366 { 2367 bus_space_tag_t iot = sc->sc_iot; 2368 bus_space_handle_t ioh = sc->sc_ioh; 2369 int timeout, s; 2370 2371 DPRINTF(("trm_reset_scsi_bus.........\n")); 2372 2373 s = splbio(); 2374 2375 sc->sc_flag |= RESET_DEV; 2376 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2377 for (timeout = 20000; timeout >= 0; timeout--) { 2378 DELAY(1); 2379 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2380 INT_SCSIRESET) == 0) 2381 break; 2382 } 2383 if (timeout == 0) 2384 printf(": scsibus reset timeout\n"); 2385 2386 splx(s); 2387 } 2388 2389 static void 2390 trm_scsi_reset_detect(sc) 2391 struct trm_softc *sc; 2392 { 2393 bus_space_tag_t iot = sc->sc_iot; 2394 bus_space_handle_t ioh = sc->sc_ioh; 2395 int s; 2396 2397 DPRINTF(("trm_scsi_reset_detect...............\n")); 2398 DELAY(1000000); /* delay 1 sec */ 2399 2400 s = splbio(); 2401 2402 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2403 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2404 2405 if (sc->sc_flag & RESET_DEV) { 2406 sc->sc_flag |= RESET_DONE; 2407 } else { 2408 sc->sc_flag |= RESET_DETECT; 2409 sc->sc_actsrb = NULL; 2410 sc->sc_flag = 0; 2411 trm_sched(sc); 2412 } 2413 splx(s); 2414 } 2415 2416 /* 2417 * read seeprom 128 bytes to struct eeprom and check checksum. 2418 * If it is wrong, update with default value. 2419 */ 2420 static void 2421 trm_check_eeprom(sc, eeprom) 2422 struct trm_softc *sc; 2423 struct trm_nvram *eeprom; 2424 { 2425 struct nvram_target *target; 2426 u_int16_t *ep; 2427 u_int16_t chksum; 2428 int i; 2429 2430 DPRINTF(("trm_check_eeprom......\n")); 2431 trm_eeprom_read_all(sc, eeprom); 2432 ep = (u_int16_t *)eeprom; 2433 chksum = 0; 2434 for (i = 0; i < 64; i++) 2435 chksum += le16toh(*ep++); 2436 2437 if (chksum != TRM_NVRAM_CKSUM) { 2438 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2439 /* 2440 * Checksum error, load default 2441 */ 2442 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2443 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2444 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2445 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2446 eeprom->subclass = 0x00; 2447 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2448 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2449 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2450 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2451 eeprom->reserved0 = 0x00; 2452 2453 for (i = 0, target = eeprom->target; 2454 i < TRM_MAX_TARGETS; 2455 i++, target++) { 2456 target->config0 = 0x77; 2457 target->period = 0x00; 2458 target->config2 = 0x00; 2459 target->config3 = 0x00; 2460 } 2461 2462 eeprom->scsi_id = 7; 2463 eeprom->channel_cfg = 0x0F; 2464 eeprom->delay_time = 0; 2465 eeprom->max_tag = 4; 2466 eeprom->reserved1 = 0x15; 2467 eeprom->boot_target = 0; 2468 eeprom->boot_lun = 0; 2469 eeprom->reserved2 = 0; 2470 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2471 2472 chksum = 0; 2473 ep = (u_int16_t *)eeprom; 2474 for (i = 0; i < 63; i++) 2475 chksum += le16toh(*ep++); 2476 2477 chksum = TRM_NVRAM_CKSUM - chksum; 2478 eeprom->checksum0 = chksum & 0xFF; 2479 eeprom->checksum1 = chksum >> 8; 2480 2481 trm_eeprom_write_all(sc, eeprom); 2482 } 2483 } 2484 2485 /* 2486 * write struct eeprom 128 bytes to seeprom 2487 */ 2488 static void 2489 trm_eeprom_write_all(sc, eeprom) 2490 struct trm_softc *sc; 2491 struct trm_nvram *eeprom; 2492 { 2493 bus_space_tag_t iot = sc->sc_iot; 2494 bus_space_handle_t ioh = sc->sc_ioh; 2495 u_int8_t *buf = (u_int8_t *)eeprom; 2496 u_int8_t addr; 2497 2498 /* Enable SEEPROM */ 2499 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2500 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2501 2502 /* 2503 * Write enable 2504 */ 2505 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2506 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2507 trm_eeprom_wait(); 2508 2509 for (addr = 0; addr < 128; addr++, buf++) 2510 trm_eeprom_set_data(sc, addr, *buf); 2511 2512 /* 2513 * Write disable 2514 */ 2515 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2516 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2517 trm_eeprom_wait(); 2518 2519 /* Disable SEEPROM */ 2520 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2521 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2522 } 2523 2524 /* 2525 * write one byte to seeprom 2526 */ 2527 static void 2528 trm_eeprom_set_data(sc, addr, data) 2529 struct trm_softc *sc; 2530 u_int8_t addr; 2531 u_int8_t data; 2532 { 2533 bus_space_tag_t iot = sc->sc_iot; 2534 bus_space_handle_t ioh = sc->sc_ioh; 2535 int i; 2536 u_int8_t send; 2537 2538 /* 2539 * Send write command & address 2540 */ 2541 trm_eeprom_write_cmd(sc, 0x05, addr); 2542 /* 2543 * Write data 2544 */ 2545 for (i = 0; i < 8; i++, data <<= 1) { 2546 send = NVR_SELECT; 2547 if (data & 0x80) /* Start from bit 7 */ 2548 send |= NVR_BITOUT; 2549 2550 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2551 trm_eeprom_wait(); 2552 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2553 trm_eeprom_wait(); 2554 } 2555 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2556 trm_eeprom_wait(); 2557 /* 2558 * Disable chip select 2559 */ 2560 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2561 trm_eeprom_wait(); 2562 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2563 trm_eeprom_wait(); 2564 /* 2565 * Wait for write ready 2566 */ 2567 for (;;) { 2568 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2569 NVR_SELECT | NVR_CLOCK); 2570 trm_eeprom_wait(); 2571 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2572 trm_eeprom_wait(); 2573 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2574 break; 2575 } 2576 /* 2577 * Disable chip select 2578 */ 2579 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2580 } 2581 2582 /* 2583 * read seeprom 128 bytes to struct eeprom 2584 */ 2585 static void 2586 trm_eeprom_read_all(sc, eeprom) 2587 struct trm_softc *sc; 2588 struct trm_nvram *eeprom; 2589 { 2590 bus_space_tag_t iot = sc->sc_iot; 2591 bus_space_handle_t ioh = sc->sc_ioh; 2592 u_int8_t *buf = (u_int8_t *)eeprom; 2593 u_int8_t addr; 2594 2595 /* 2596 * Enable SEEPROM 2597 */ 2598 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2599 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2600 2601 for (addr = 0; addr < 128; addr++) 2602 *buf++ = trm_eeprom_get_data(sc, addr); 2603 2604 /* 2605 * Disable SEEPROM 2606 */ 2607 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2608 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2609 } 2610 2611 /* 2612 * read one byte from seeprom 2613 */ 2614 static u_int8_t 2615 trm_eeprom_get_data(sc, addr) 2616 struct trm_softc *sc; 2617 u_int8_t addr; 2618 { 2619 bus_space_tag_t iot = sc->sc_iot; 2620 bus_space_handle_t ioh = sc->sc_ioh; 2621 int i; 2622 u_int8_t read, data = 0; 2623 2624 /* 2625 * Send read command & address 2626 */ 2627 trm_eeprom_write_cmd(sc, 0x06, addr); 2628 2629 for (i = 0; i < 8; i++) { /* Read data */ 2630 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2631 NVR_SELECT | NVR_CLOCK); 2632 trm_eeprom_wait(); 2633 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2634 /* 2635 * Get data bit while falling edge 2636 */ 2637 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2638 data <<= 1; 2639 if (read & NVR_BITIN) 2640 data |= 1; 2641 2642 trm_eeprom_wait(); 2643 } 2644 /* 2645 * Disable chip select 2646 */ 2647 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2648 return (data); 2649 } 2650 2651 /* 2652 * write SB and Op Code into seeprom 2653 */ 2654 static void 2655 trm_eeprom_write_cmd(sc, cmd, addr) 2656 struct trm_softc *sc; 2657 u_int8_t cmd; 2658 u_int8_t addr; 2659 { 2660 bus_space_tag_t iot = sc->sc_iot; 2661 bus_space_handle_t ioh = sc->sc_ioh; 2662 int i; 2663 u_int8_t send; 2664 2665 /* Program SB+OP code */ 2666 for (i = 0; i < 3; i++, cmd <<= 1) { 2667 send = NVR_SELECT; 2668 if (cmd & 0x04) /* Start from bit 2 */ 2669 send |= NVR_BITOUT; 2670 2671 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2672 trm_eeprom_wait(); 2673 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2674 trm_eeprom_wait(); 2675 } 2676 2677 /* Program address */ 2678 for (i = 0; i < 7; i++, addr <<= 1) { 2679 send = NVR_SELECT; 2680 if (addr & 0x40) /* Start from bit 6 */ 2681 send |= NVR_BITOUT; 2682 2683 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2684 trm_eeprom_wait(); 2685 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2686 trm_eeprom_wait(); 2687 } 2688 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2689 trm_eeprom_wait(); 2690 }
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