Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/pci/viaide.c
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1 /* $NetBSD: viaide.c,v 1.11 2004/03/10 22:16:04 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_apollo_reg.h> 41 42 static int via_pcib_match(struct pci_attach_args *); 43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 44 static void via_sata_chip_map(struct pciide_softc *, 45 struct pci_attach_args *); 46 static void via_setup_channel(struct wdc_channel *); 47 48 static int viaide_match(struct device *, struct cfdata *, void *); 49 static void viaide_attach(struct device *, struct device *, void *); 50 static const struct pciide_product_desc * 51 viaide_lookup(pcireg_t); 52 53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 54 viaide_match, viaide_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_amd_products[] = { 57 { PCI_PRODUCT_AMD_PBC756_IDE, 58 0, 59 "Advanced Micro Devices AMD756 IDE Controller", 60 via_chip_map 61 }, 62 { PCI_PRODUCT_AMD_PBC766_IDE, 63 0, 64 "Advanced Micro Devices AMD766 IDE Controller", 65 via_chip_map 66 }, 67 { PCI_PRODUCT_AMD_PBC768_IDE, 68 0, 69 "Advanced Micro Devices AMD768 IDE Controller", 70 via_chip_map 71 }, 72 { PCI_PRODUCT_AMD_PBC8111_IDE, 73 0, 74 "Advanced Micro Devices AMD8111 IDE Controller", 75 via_chip_map 76 }, 77 { 0, 78 0, 79 NULL, 80 NULL 81 } 82 }; 83 84 static const struct pciide_product_desc pciide_nvidia_products[] = { 85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 86 0, 87 "NVIDIA nForce IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 91 0, 92 "NVIDIA nForce2 IDE Controller", 93 via_chip_map 94 }, 95 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 96 0, 97 "NVIDIA nForce3 IDE Controller", 98 via_chip_map 99 }, 100 { 0, 101 0, 102 NULL, 103 NULL 104 } 105 }; 106 107 static const struct pciide_product_desc pciide_via_products[] = { 108 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 109 0, 110 NULL, 111 via_chip_map, 112 }, 113 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 114 0, 115 NULL, 116 via_chip_map, 117 }, 118 { PCI_PRODUCT_VIATECH_VT8237_SATA, 119 0, 120 "VIA Technologies VT8237 SATA Controller", 121 via_sata_chip_map, 122 }, 123 { 0, 124 0, 125 NULL, 126 NULL 127 } 128 }; 129 130 static const struct pciide_product_desc * 131 viaide_lookup(pcireg_t id) 132 { 133 134 switch (PCI_VENDOR(id)) { 135 case PCI_VENDOR_VIATECH: 136 return (pciide_lookup_product(id, pciide_via_products)); 137 138 case PCI_VENDOR_AMD: 139 return (pciide_lookup_product(id, pciide_amd_products)); 140 141 case PCI_VENDOR_NVIDIA: 142 return (pciide_lookup_product(id, pciide_nvidia_products)); 143 } 144 return (NULL); 145 } 146 147 static int 148 viaide_match(struct device *parent, struct cfdata *match, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 152 if (viaide_lookup(pa->pa_id) != NULL) 153 return (2); 154 return (0); 155 } 156 157 static void 158 viaide_attach(struct device *parent, struct device *self, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct pciide_softc *sc = (struct pciide_softc *)self; 162 const struct pciide_product_desc *pp; 163 164 pp = viaide_lookup(pa->pa_id); 165 if (pp == NULL) 166 panic("viaide_attach"); 167 pciide_common_attach(sc, pa, pp); 168 } 169 170 static int 171 via_pcib_match(struct pci_attach_args *pa) 172 { 173 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 174 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 175 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 176 return (1); 177 return 0; 178 } 179 180 static void 181 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 182 { 183 struct pciide_channel *cp; 184 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 185 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 186 int channel; 187 u_int32_t ideconf; 188 bus_size_t cmdsize, ctlsize; 189 pcireg_t pcib_id, pcib_class; 190 struct pci_attach_args pcib_pa; 191 192 if (pciide_chipen(sc, pa) == 0) 193 return; 194 195 switch (vendor) { 196 case PCI_VENDOR_VIATECH: 197 /* 198 * get a PCI tag for the ISA bridge. 199 */ 200 if (pci_enumerate_bus( 201 (struct pci_softc *)sc->sc_wdcdev.sc_dev.dv_parent, 202 via_pcib_match, &pcib_pa) == 0) 203 goto unknown; 204 pcib_id = pcib_pa.pa_id; 205 pcib_class = pcib_pa.pa_class; 206 aprint_normal("%s: VIA Technologies ", 207 sc->sc_wdcdev.sc_dev.dv_xname); 208 switch (PCI_PRODUCT(pcib_id)) { 209 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 210 aprint_normal("VT82C586 (Apollo VP) "); 211 if(PCI_REVISION(pcib_class) >= 0x02) { 212 aprint_normal("ATA33 controller\n"); 213 sc->sc_wdcdev.UDMA_cap = 2; 214 } else { 215 aprint_normal("controller\n"); 216 sc->sc_wdcdev.UDMA_cap = 0; 217 } 218 break; 219 case PCI_PRODUCT_VIATECH_VT82C596A: 220 aprint_normal("VT82C596A (Apollo Pro) "); 221 if (PCI_REVISION(pcib_class) >= 0x12) { 222 aprint_normal("ATA66 controller\n"); 223 sc->sc_wdcdev.UDMA_cap = 4; 224 } else { 225 aprint_normal("ATA33 controller\n"); 226 sc->sc_wdcdev.UDMA_cap = 2; 227 } 228 break; 229 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 230 aprint_normal("VT82C686A (Apollo KX133) "); 231 if (PCI_REVISION(pcib_class) >= 0x40) { 232 aprint_normal("ATA100 controller\n"); 233 sc->sc_wdcdev.UDMA_cap = 5; 234 } else { 235 aprint_normal("ATA66 controller\n"); 236 sc->sc_wdcdev.UDMA_cap = 4; 237 } 238 break; 239 case PCI_PRODUCT_VIATECH_VT8231: 240 aprint_normal("VT8231 ATA100 controller\n"); 241 sc->sc_wdcdev.UDMA_cap = 5; 242 break; 243 case PCI_PRODUCT_VIATECH_VT8233: 244 aprint_normal("VT8233 ATA100 controller\n"); 245 sc->sc_wdcdev.UDMA_cap = 5; 246 break; 247 case PCI_PRODUCT_VIATECH_VT8233A: 248 aprint_normal("VT8233A ATA133 controller\n"); 249 sc->sc_wdcdev.UDMA_cap = 6; 250 break; 251 case PCI_PRODUCT_VIATECH_VT8235: 252 aprint_normal("VT8235 ATA133 controller\n"); 253 sc->sc_wdcdev.UDMA_cap = 6; 254 break; 255 case PCI_PRODUCT_VIATECH_VT8237: 256 aprint_normal("VT8237 ATA133 controller\n"); 257 sc->sc_wdcdev.UDMA_cap = 6; 258 break; 259 default: 260 unknown: 261 aprint_normal("unknown VIA ATA controller\n"); 262 sc->sc_wdcdev.UDMA_cap = 0; 263 } 264 sc->sc_apo_regbase = APO_VIA_REGBASE; 265 break; 266 case PCI_VENDOR_AMD: 267 switch (sc->sc_pp->ide_product) { 268 case PCI_PRODUCT_AMD_PBC8111_IDE: 269 sc->sc_wdcdev.UDMA_cap = 6; 270 break; 271 case PCI_PRODUCT_AMD_PBC766_IDE: 272 case PCI_PRODUCT_AMD_PBC768_IDE: 273 sc->sc_wdcdev.UDMA_cap = 5; 274 break; 275 default: 276 sc->sc_wdcdev.UDMA_cap = 4; 277 } 278 sc->sc_apo_regbase = APO_AMD_REGBASE; 279 break; 280 case PCI_VENDOR_NVIDIA: 281 switch (sc->sc_pp->ide_product) { 282 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 283 sc->sc_wdcdev.UDMA_cap = 5; 284 break; 285 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 286 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 287 sc->sc_wdcdev.UDMA_cap = 6; 288 break; 289 } 290 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 291 break; 292 default: 293 panic("via_chip_map: unknown vendor"); 294 } 295 296 aprint_normal("%s: bus-master DMA support present", 297 sc->sc_wdcdev.sc_dev.dv_xname); 298 pciide_mapreg_dma(sc, pa); 299 aprint_normal("\n"); 300 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 301 WDC_CAPABILITY_MODE; 302 if (sc->sc_dma_ok) { 303 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 304 sc->sc_wdcdev.irqack = pciide_irqack; 305 if (sc->sc_wdcdev.UDMA_cap > 0) 306 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 307 } 308 sc->sc_wdcdev.PIO_cap = 4; 309 sc->sc_wdcdev.DMA_cap = 2; 310 sc->sc_wdcdev.set_modes = via_setup_channel; 311 sc->sc_wdcdev.channels = sc->wdc_chanarray; 312 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 313 314 WDCDEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 315 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 316 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 317 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 318 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 319 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 320 DEBUG_PROBE); 321 322 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 323 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 324 cp = &sc->pciide_channels[channel]; 325 if (pciide_chansetup(sc, channel, interface) == 0) 326 continue; 327 328 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 329 aprint_normal("%s: %s channel ignored (disabled)\n", 330 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 331 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 332 continue; 333 } 334 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 335 pciide_pci_intr); 336 } 337 } 338 339 static void 340 via_setup_channel(struct wdc_channel *chp) 341 { 342 u_int32_t udmatim_reg, datatim_reg; 343 u_int8_t idedma_ctl; 344 int mode, drive; 345 struct ata_drive_datas *drvp; 346 struct pciide_channel *cp = (struct pciide_channel*)chp; 347 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 348 struct wdc_softc *wdc = &sc->sc_wdcdev; 349 #ifndef PCIIDE_AMD756_ENABLEDMA 350 int rev = PCI_REVISION( 351 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 352 #endif 353 354 idedma_ctl = 0; 355 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 356 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 357 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 358 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 359 360 /* setup DMA if needed */ 361 pciide_channel_dma_setup(cp); 362 363 for (drive = 0; drive < 2; drive++) { 364 drvp = &chp->ch_drive[drive]; 365 /* If no drive, skip */ 366 if ((drvp->drive_flags & DRIVE) == 0) 367 continue; 368 /* add timing values, setup DMA if needed */ 369 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 370 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 371 mode = drvp->PIO_mode; 372 goto pio; 373 } 374 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 375 (drvp->drive_flags & DRIVE_UDMA)) { 376 /* use Ultra/DMA */ 377 drvp->drive_flags &= ~DRIVE_DMA; 378 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 379 APO_UDMA_EN_MTH(chp->ch_channel, drive); 380 switch (PCI_VENDOR(sc->sc_pci_id)) { 381 case PCI_VENDOR_VIATECH: 382 if (sc->sc_wdcdev.UDMA_cap == 6) { 383 /* 8233a */ 384 udmatim_reg |= APO_UDMA_TIME( 385 chp->ch_channel, 386 drive, 387 via_udma133_tim[drvp->UDMA_mode]); 388 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 389 /* 686b */ 390 udmatim_reg |= APO_UDMA_TIME( 391 chp->ch_channel, 392 drive, 393 via_udma100_tim[drvp->UDMA_mode]); 394 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 395 /* 596b or 686a */ 396 udmatim_reg |= APO_UDMA_CLK66( 397 chp->ch_channel); 398 udmatim_reg |= APO_UDMA_TIME( 399 chp->ch_channel, 400 drive, 401 via_udma66_tim[drvp->UDMA_mode]); 402 } else { 403 /* 596a or 586b */ 404 udmatim_reg |= APO_UDMA_TIME( 405 chp->ch_channel, 406 drive, 407 via_udma33_tim[drvp->UDMA_mode]); 408 } 409 break; 410 case PCI_VENDOR_AMD: 411 case PCI_VENDOR_NVIDIA: 412 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 413 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 414 break; 415 } 416 /* can use PIO timings, MW DMA unused */ 417 mode = drvp->PIO_mode; 418 } else { 419 /* use Multiword DMA, but only if revision is OK */ 420 drvp->drive_flags &= ~DRIVE_UDMA; 421 #ifndef PCIIDE_AMD756_ENABLEDMA 422 /* 423 * The workaround doesn't seem to be necessary 424 * with all drives, so it can be disabled by 425 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 426 * triggered. 427 */ 428 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 429 sc->sc_pp->ide_product == 430 PCI_PRODUCT_AMD_PBC756_IDE && 431 AMD756_CHIPREV_DISABLEDMA(rev)) { 432 aprint_normal( 433 "%s:%d:%d: multi-word DMA disabled due " 434 "to chip revision\n", 435 sc->sc_wdcdev.sc_dev.dv_xname, 436 chp->ch_channel, drive); 437 mode = drvp->PIO_mode; 438 drvp->drive_flags &= ~DRIVE_DMA; 439 goto pio; 440 } 441 #endif 442 /* mode = min(pio, dma+2) */ 443 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 444 mode = drvp->PIO_mode; 445 else 446 mode = drvp->DMA_mode + 2; 447 } 448 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 449 450 pio: /* setup PIO mode */ 451 if (mode <= 2) { 452 drvp->DMA_mode = 0; 453 drvp->PIO_mode = 0; 454 mode = 0; 455 } else { 456 drvp->PIO_mode = mode; 457 drvp->DMA_mode = mode - 2; 458 } 459 datatim_reg |= 460 APO_DATATIM_PULSE(chp->ch_channel, drive, 461 apollo_pio_set[mode]) | 462 APO_DATATIM_RECOV(chp->ch_channel, drive, 463 apollo_pio_rec[mode]); 464 } 465 if (idedma_ctl != 0) { 466 /* Add software bits in status register */ 467 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 468 idedma_ctl); 469 } 470 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 471 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 472 WDCDEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 473 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 474 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 475 } 476 477 static void 478 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 479 { 480 struct pciide_channel *cp; 481 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 482 int channel; 483 bus_size_t cmdsize, ctlsize; 484 485 if (pciide_chipen(sc, pa) == 0) 486 return; 487 488 if (interface == 0) { 489 WDCDEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 490 DEBUG_PROBE); 491 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 492 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 493 } 494 495 aprint_normal("%s: bus-master DMA support present", 496 sc->sc_wdcdev.sc_dev.dv_xname); 497 pciide_mapreg_dma(sc, pa); 498 aprint_normal("\n"); 499 500 if (sc->sc_dma_ok) { 501 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA | 502 WDC_CAPABILITY_IRQACK; 503 sc->sc_wdcdev.irqack = pciide_irqack; 504 } 505 sc->sc_wdcdev.PIO_cap = 4; 506 sc->sc_wdcdev.DMA_cap = 2; 507 sc->sc_wdcdev.UDMA_cap = 6; 508 509 sc->sc_wdcdev.channels = sc->wdc_chanarray; 510 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 511 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 512 WDC_CAPABILITY_MODE; 513 sc->sc_wdcdev.set_modes = sata_setup_channel; 514 515 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 516 cp = &sc->pciide_channels[channel]; 517 if (pciide_chansetup(sc, channel, interface) == 0) 518 continue; 519 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 520 pciide_pci_intr); 521 } 522 }
Cache object: 14a38b8c6845d5c88da03e3f6e77ef81
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