Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/pcmcia/if_xi.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: if_xi.c,v 1.33 2003/10/28 23:26:28 mycroft Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * XXX THIS DRIVER IS BROKEN WRT. MULTICAST LISTS AND PROMISC/ALLMULTI 6 * XXX FLAGS! 7 */ 8 9 /* 10 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Niklas Hallqvist, 24 * Brandon Creighton and Job de Haas. 25 * 4. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 42 */ 43 44 /* 45 * Known Bugs: 46 * 47 * 1) Promiscuous mode doesn't work on at least the CE2. 48 * 2) Slow. ~450KB/s. Memory access would be better. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.33 2003/10/28 23:26:28 mycroft Exp $"); 53 54 #include "opt_inet.h" 55 #include "opt_ipx.h" 56 #include "bpfilter.h" 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 #include <sys/ioctl.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/socket.h> 65 66 #include "rnd.h" 67 #if NRND > 0 68 #include <sys/rnd.h> 69 #endif 70 71 #include <net/if.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_ether.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #include <netinet/if_inarp.h> 83 #endif 84 85 #ifdef IPX 86 #include <netipx/ipx.h> 87 #include <netipx/ipx_if.h> 88 #endif 89 90 #ifdef NS 91 #include <netns/ns.h> 92 #include <netns/ns_if.h> 93 #endif 94 95 #if NBPFILTER > 0 96 #include <net/bpf.h> 97 #include <net/bpfdesc.h> 98 #endif 99 100 /* 101 * Maximum number of bytes to read per interrupt. Linux recommends 102 * somewhere between 2000-22000. 103 * XXX This is currently a hard maximum. 104 */ 105 #define MAX_BYTES_INTR 12000 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/pcmcia/pcmciareg.h> 111 #include <dev/pcmcia/pcmciavar.h> 112 #include <dev/pcmcia/pcmciadevs.h> 113 114 #include <dev/pcmcia/if_xireg.h> 115 116 #ifdef __GNUC__ 117 #define INLINE __inline 118 #else 119 #define INLINE 120 #endif /* __GNUC__ */ 121 122 #ifdef XIDEBUG 123 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 124 125 #define XID_CONFIG 0x1 126 #define XID_MII 0x2 127 #define XID_INTR 0x4 128 #define XID_FIFO 0x8 129 130 #ifdef XIDEBUG_VALUE 131 int xidebug = XIDEBUG_VALUE; 132 #else 133 int xidebug = 0; 134 #endif 135 #else 136 #define DPRINTF(cat, x) (void)0 137 #endif 138 139 int xi_pcmcia_match __P((struct device *, struct cfdata *, void *)); 140 void xi_pcmcia_attach __P((struct device *, struct device *, void *)); 141 int xi_pcmcia_detach __P((struct device *, int)); 142 int xi_pcmcia_activate __P((struct device *, enum devact)); 143 144 /* 145 * In case this chipset ever turns up out of pcmcia attachments (very 146 * unlikely) do the driver splitup. 147 */ 148 struct xi_softc { 149 struct device sc_dev; /* Generic device info */ 150 struct ethercom sc_ethercom; /* Ethernet common part */ 151 152 struct mii_data sc_mii; /* MII media information */ 153 154 bus_space_tag_t sc_bst; /* Bus cookie */ 155 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 156 bus_size_t sc_offset; /* Offset of registers */ 157 158 u_int8_t sc_rev; /* Chip revision */ 159 u_int32_t sc_flags; /* Misc. flags */ 160 int sc_all_mcasts; /* Receive all multicasts */ 161 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; 162 #if NRND > 0 163 rndsource_element_t sc_rnd_source; 164 #endif 165 }; 166 167 struct xi_pcmcia_softc { 168 struct xi_softc sc_xi; /* Generic device info */ 169 170 /* PCMCIA-specific goo */ 171 struct pcmcia_function *sc_pf; /* PCMCIA function */ 172 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 173 int sc_io_window; /* io window info */ 174 void *sc_ih; /* Interrupt handler */ 175 void *sc_powerhook; /* power hook descriptor */ 176 int sc_resource; /* resource allocated */ 177 #define XI_RES_PCIC 1 178 #define XI_RES_IO_ALLOC 2 179 #define XI_RES_IO_MAP 4 180 #define XI_RES_MI 8 181 }; 182 183 CFATTACH_DECL(xi_pcmcia, sizeof(struct xi_pcmcia_softc), 184 xi_pcmcia_match, xi_pcmcia_attach, xi_pcmcia_detach, xi_pcmcia_activate); 185 186 static int xi_pcmcia_cis_quirks __P((struct pcmcia_function *)); 187 static void xi_cycle_power __P((struct xi_softc *)); 188 static int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 189 static void xi_full_reset __P((struct xi_softc *)); 190 static void xi_init __P((struct xi_softc *)); 191 static int xi_intr __P((void *)); 192 static int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 193 static int xi_mdi_read __P((struct device *, int, int)); 194 static void xi_mdi_write __P((struct device *, int, int, int)); 195 static int xi_mediachange __P((struct ifnet *)); 196 static void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 197 static int xi_pcmcia_funce_enaddr __P((struct device *, u_int8_t *)); 198 static int xi_pcmcia_lan_nid_ciscallback __P((struct pcmcia_tuple *, void *)); 199 static int xi_pcmcia_manfid_ciscallback __P((struct pcmcia_tuple *, void *)); 200 static u_int16_t xi_get __P((struct xi_softc *)); 201 static void xi_reset __P((struct xi_softc *)); 202 static void xi_set_address __P((struct xi_softc *)); 203 static void xi_start __P((struct ifnet *)); 204 static void xi_statchg __P((struct device *)); 205 static void xi_stop __P((struct xi_softc *)); 206 static void xi_watchdog __P((struct ifnet *)); 207 const struct xi_pcmcia_product *xi_pcmcia_identify __P((struct device *, 208 struct pcmcia_attach_args *)); 209 static int xi_pcmcia_enable __P((struct xi_pcmcia_softc *)); 210 static void xi_pcmcia_disable __P((struct xi_pcmcia_softc *)); 211 static void xi_pcmcia_power __P((int, void *)); 212 213 /* flags */ 214 #define XIFLAGS_MOHAWK 0x001 /* 100Mb capabilities (has phy) */ 215 #define XIFLAGS_DINGO 0x002 /* realport cards ??? */ 216 #define XIFLAGS_MODEM 0x004 /* modem also present */ 217 218 const struct xi_pcmcia_product { 219 u_int32_t xpp_vendor; /* vendor ID */ 220 u_int32_t xpp_product; /* product ID */ 221 int xpp_expfunc; /* expected function number */ 222 int xpp_flags; /* initial softc flags */ 223 const char *xpp_name; /* device name */ 224 } xi_pcmcia_products[] = { 225 #ifdef NOT_SUPPORTED 226 { PCMCIA_VENDOR_XIRCOM, 0x0141, 227 0, 0, 228 PCMCIA_STR_XIRCOM_CE }, 229 #endif 230 { PCMCIA_VENDOR_XIRCOM, 0x0141, 231 0, 0, 232 PCMCIA_STR_XIRCOM_CE2 }, 233 { PCMCIA_VENDOR_XIRCOM, 0x0142, 234 0, 0, 235 PCMCIA_STR_XIRCOM_CE2 }, 236 { PCMCIA_VENDOR_XIRCOM, 0x0143, 237 0, XIFLAGS_MOHAWK, 238 PCMCIA_STR_XIRCOM_CE3 }, 239 { PCMCIA_VENDOR_COMPAQ2, 0x0143, 240 0, XIFLAGS_MOHAWK, 241 PCMCIA_STR_COMPAQ2_CPQ_10_100 }, 242 { PCMCIA_VENDOR_INTEL, 0x0143, 243 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 244 PCMCIA_STR_INTEL_EEPRO100 }, 245 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_XE2000, 246 0, XIFLAGS_MOHAWK, 247 PCMCIA_STR_XIRCOM_XE2000 }, 248 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_REM56, 249 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 250 PCMCIA_STR_XIRCOM_REM56 }, 251 #ifdef NOT_SUPPORTED 252 { PCMCIA_VENDOR_XIRCOM, 0x1141, 253 0, XIFLAGS_MODEM, 254 PCMCIA_STR_XIRCOM_CEM }, 255 #endif 256 { PCMCIA_VENDOR_XIRCOM, 0x1142, 257 0, XIFLAGS_MODEM, 258 PCMCIA_STR_XIRCOM_CEM }, 259 { PCMCIA_VENDOR_XIRCOM, 0x1143, 260 0, XIFLAGS_MODEM, 261 PCMCIA_STR_XIRCOM_CEM }, 262 { PCMCIA_VENDOR_XIRCOM, 0x1144, 263 0, XIFLAGS_MODEM, 264 PCMCIA_STR_XIRCOM_CEM33 }, 265 { PCMCIA_VENDOR_XIRCOM, 0x1145, 266 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 267 PCMCIA_STR_XIRCOM_CEM56 }, 268 { PCMCIA_VENDOR_XIRCOM, 0x1146, 269 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 270 PCMCIA_STR_XIRCOM_REM56 }, 271 { PCMCIA_VENDOR_XIRCOM, 0x1147, 272 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 273 PCMCIA_STR_XIRCOM_REM56 }, 274 { 0, 0, 275 0, 0, 276 NULL }, 277 }; 278 279 280 const struct xi_pcmcia_product * 281 xi_pcmcia_identify(dev, pa) 282 struct device *dev; 283 struct pcmcia_attach_args *pa; 284 { 285 const struct xi_pcmcia_product *xpp; 286 u_int8_t id; 287 u_int32_t prod; 288 289 /* 290 * The Xircom ethernet cards swap the revision and product fields 291 * inside the CIS, which makes identification just a little 292 * bit different. 293 */ 294 295 pcmcia_scan_cis(dev, xi_pcmcia_manfid_ciscallback, &id); 296 297 prod = (pa->product & ~0xff) | id; 298 299 DPRINTF(XID_CONFIG, ("product=0x%x\n", prod)); 300 301 for (xpp = xi_pcmcia_products; xpp->xpp_name != NULL; xpp++) 302 if (pa->manufacturer == xpp->xpp_vendor && 303 prod == xpp->xpp_product && 304 pa->pf->number == xpp->xpp_expfunc) 305 return (xpp); 306 return (NULL); 307 } 308 309 /* 310 * The quirks are done here instead of the traditional framework because 311 * of the difficulty in identifying the devices. 312 */ 313 static int 314 xi_pcmcia_cis_quirks(pf) 315 struct pcmcia_function *pf; 316 { 317 struct pcmcia_config_entry *cfe; 318 319 /* Tell the pcmcia framework where the CCR is. */ 320 pf->ccr_base = 0x800; 321 pf->ccr_mask = 0x67; 322 323 /* Fake a cfe. */ 324 SIMPLEQ_FIRST(&pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 325 malloc(sizeof(*cfe), M_DEVBUF, M_NOWAIT|M_ZERO); 326 327 if (cfe == NULL) 328 return -1; 329 330 /* 331 * XXX Use preprocessor symbols instead. 332 * Enable ethernet & its interrupts, wiring them to -INT 333 * No I/O base. 334 */ 335 cfe->number = 0x5; 336 cfe->flags = 0; /* XXX Check! */ 337 cfe->iftype = PCMCIA_IFTYPE_IO; 338 cfe->num_iospace = 0; 339 cfe->num_memspace = 0; 340 cfe->irqmask = 0x8eb0; 341 342 return 0; 343 } 344 345 int 346 xi_pcmcia_match(parent, match, aux) 347 struct device *parent; 348 struct cfdata *match; 349 void *aux; 350 { 351 struct pcmcia_attach_args *pa = aux; 352 353 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 354 pa->product == 0x110a) 355 return (2); /* prevent attach to com_pcmcia */ 356 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 357 return (0); 358 359 if (pa->manufacturer == PCMCIA_VENDOR_COMPAQ2 && 360 pa->product == PCMCIA_PRODUCT_COMPAQ2_CPQ_10_100) 361 return (1); 362 363 if (pa->manufacturer == PCMCIA_VENDOR_INTEL && 364 pa->product == PCMCIA_PRODUCT_INTEL_EEPRO100) 365 return (1); 366 367 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 368 ((pa->product >> 8) == XIMEDIA_ETHER || 369 (pa->product >> 8) == (XIMEDIA_ETHER | XIMEDIA_MODEM))) 370 return (1); 371 372 return (0); 373 } 374 375 void 376 xi_pcmcia_attach(parent, self, aux) 377 struct device *parent, *self; 378 void *aux; 379 { 380 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 381 struct xi_softc *sc = &psc->sc_xi; 382 struct pcmcia_attach_args *pa = aux; 383 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 384 const struct xi_pcmcia_product *xpp; 385 386 if (xi_pcmcia_cis_quirks(pa->pf) < 0) { 387 printf(": function enable failed\n"); 388 return; 389 } 390 391 /* Enable the card */ 392 psc->sc_pf = pa->pf; 393 pcmcia_function_init(psc->sc_pf, SIMPLEQ_FIRST(&psc->sc_pf->cfe_head)); 394 if (pcmcia_function_enable(psc->sc_pf)) { 395 printf(": function enable failed\n"); 396 goto fail; 397 } 398 psc->sc_resource |= XI_RES_PCIC; 399 400 /* allocate/map ISA I/O space */ 401 if (pcmcia_io_alloc(psc->sc_pf, 0, XI_IOSIZE, XI_IOSIZE, 402 &psc->sc_pcioh) != 0) { 403 printf(": I/O allocation failed\n"); 404 goto fail; 405 } 406 psc->sc_resource |= XI_RES_IO_ALLOC; 407 408 sc->sc_bst = psc->sc_pcioh.iot; 409 sc->sc_bsh = psc->sc_pcioh.ioh; 410 sc->sc_offset = 0; 411 412 if (pcmcia_io_map(psc->sc_pf, PCMCIA_WIDTH_AUTO, 0, XI_IOSIZE, 413 &psc->sc_pcioh, &psc->sc_io_window)) { 414 printf(": can't map I/O space\n"); 415 goto fail; 416 } 417 psc->sc_resource |= XI_RES_IO_MAP; 418 419 xpp = xi_pcmcia_identify(parent,pa); 420 if (xpp == NULL) { 421 printf(": unrecognised model\n"); 422 return; 423 } 424 sc->sc_flags = xpp->xpp_flags; 425 426 printf(": %s\n", xpp->xpp_name); 427 428 /* 429 * Configuration as advised by DINGO documentation. 430 * Dingo has some extra configuration registers in the CCR space. 431 */ 432 if (sc->sc_flags & XIFLAGS_DINGO) { 433 struct pcmcia_mem_handle pcmh; 434 int ccr_window; 435 bus_size_t ccr_offset; 436 437 /* get access to the DINGO CCR space */ 438 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 439 &pcmh)) { 440 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 441 goto fail; 442 } 443 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 444 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 445 &pcmh, &ccr_offset, &ccr_window)) { 446 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 447 pcmcia_mem_free(psc->sc_pf, &pcmh); 448 goto fail; 449 } 450 451 /* enable the second function - usually modem */ 452 bus_space_write_1(pcmh.memt, pcmh.memh, 453 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 454 bus_space_write_1(pcmh.memt, pcmh.memh, 455 ccr_offset + PCMCIA_CCR_DCOR1, 456 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 457 bus_space_write_1(pcmh.memt, pcmh.memh, 458 ccr_offset + PCMCIA_CCR_DCOR2, 0); 459 bus_space_write_1(pcmh.memt, pcmh.memh, 460 ccr_offset + PCMCIA_CCR_DCOR3, 0); 461 bus_space_write_1(pcmh.memt, pcmh.memh, 462 ccr_offset + PCMCIA_CCR_DCOR4, 0); 463 464 /* We don't need them anymore and can free them (I think). */ 465 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 466 pcmcia_mem_free(psc->sc_pf, &pcmh); 467 } 468 469 /* 470 * Get the ethernet address from FUNCE/LAN_NID tuple. 471 */ 472 xi_pcmcia_funce_enaddr(parent, sc->sc_enaddr); 473 if (!sc->sc_enaddr) { 474 printf("%s: unable to get ethernet address\n", 475 sc->sc_dev.dv_xname); 476 goto fail; 477 } 478 479 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 480 ether_sprintf(sc->sc_enaddr)); 481 482 ifp = &sc->sc_ethercom.ec_if; 483 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 484 ifp->if_softc = sc; 485 ifp->if_start = xi_start; 486 ifp->if_ioctl = xi_ioctl; 487 ifp->if_watchdog = xi_watchdog; 488 ifp->if_flags = 489 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 490 IFQ_SET_READY(&ifp->if_snd); 491 492 /* Reset and initialize the card. */ 493 xi_full_reset(sc); 494 495 /* 496 * Initialize our media structures and probe the MII. 497 */ 498 sc->sc_mii.mii_ifp = ifp; 499 sc->sc_mii.mii_readreg = xi_mdi_read; 500 sc->sc_mii.mii_writereg = xi_mdi_write; 501 sc->sc_mii.mii_statchg = xi_statchg; 502 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 503 xi_mediastatus); 504 DPRINTF(XID_MII | XID_CONFIG, 505 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 506 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 507 MII_OFFSET_ANY, 0); 508 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 509 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 510 NULL); 511 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 512 513 /* 802.1q capability */ 514 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 515 /* Attach the interface. */ 516 if_attach(ifp); 517 ether_ifattach(ifp, sc->sc_enaddr); 518 psc->sc_resource |= XI_RES_MI; 519 520 #if NRND > 0 521 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 522 RND_TYPE_NET, 0); 523 #endif 524 525 /* 526 * Reset and initialize the card again for DINGO (as found in Linux 527 * driver). Without this Dingo will get a watchdog timeout the first 528 * time. The ugly media tickling seems to be necessary for getting 529 * autonegotiation to work too. 530 */ 531 if (sc->sc_flags & XIFLAGS_DINGO) { 532 xi_full_reset(sc); 533 xi_init(sc); 534 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 535 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 536 xi_stop(sc); 537 } 538 539 psc->sc_powerhook = powerhook_establish(xi_pcmcia_power, sc); 540 541 pcmcia_function_disable(psc->sc_pf); 542 psc->sc_resource &= ~XI_RES_PCIC; 543 544 return; 545 546 fail: 547 if ((psc->sc_resource & XI_RES_IO_MAP) != 0) { 548 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 549 psc->sc_resource &= ~XI_RES_IO_MAP; 550 } 551 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 552 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 553 psc->sc_resource &= ~XI_RES_IO_ALLOC; 554 } 555 if (psc->sc_resource & XI_RES_PCIC) { 556 pcmcia_function_disable(pa->pf); 557 psc->sc_resource &= ~XI_RES_PCIC; 558 } 559 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 560 } 561 562 int 563 xi_pcmcia_detach(self, flags) 564 struct device *self; 565 int flags; 566 { 567 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 568 struct xi_softc *sc = &psc->sc_xi; 569 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 570 571 DPRINTF(XID_CONFIG, ("xi_pcmcia_detach()\n")); 572 573 if (psc->sc_powerhook != NULL) 574 powerhook_disestablish(psc->sc_powerhook); 575 576 #if NRND > 0 577 rnd_detach_source(&sc->sc_rnd_source); 578 #endif 579 580 if ((psc->sc_resource & XI_RES_MI) != 0) { 581 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 582 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 583 ether_ifdetach(ifp); 584 if_detach(ifp); 585 psc->sc_resource &= ~XI_RES_MI; 586 } 587 if (psc->sc_resource & XI_RES_IO_MAP) { 588 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 589 psc->sc_resource &= ~XI_RES_IO_MAP; 590 } 591 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 592 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 593 psc->sc_resource &= ~XI_RES_IO_ALLOC; 594 } 595 596 xi_pcmcia_disable(psc); 597 598 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 599 600 return 0; 601 } 602 603 int 604 xi_pcmcia_activate(self, act) 605 struct device *self; 606 enum devact act; 607 { 608 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 609 struct xi_softc *sc = &psc->sc_xi; 610 int s, rv=0; 611 612 DPRINTF(XID_CONFIG, ("xi_pcmcia_activate()\n")); 613 614 s = splnet(); 615 switch (act) { 616 case DVACT_ACTIVATE: 617 rv = EOPNOTSUPP; 618 break; 619 620 case DVACT_DEACTIVATE: 621 if_deactivate(&sc->sc_ethercom.ec_if); 622 break; 623 } 624 splx(s); 625 return (rv); 626 } 627 628 static int 629 xi_pcmcia_enable(psc) 630 struct xi_pcmcia_softc *psc; 631 { 632 struct xi_softc *sc = &psc->sc_xi; 633 634 DPRINTF(XID_CONFIG,("xi_pcmcia_enable()\n")); 635 636 if (pcmcia_function_enable(psc->sc_pf)) 637 return (1); 638 psc->sc_resource |= XI_RES_PCIC; 639 640 /* establish the interrupt. */ 641 psc->sc_ih = pcmcia_intr_establish(psc->sc_pf, IPL_NET, xi_intr, sc); 642 if (psc->sc_ih == NULL) { 643 printf("%s: couldn't establish interrupt\n", 644 sc->sc_dev.dv_xname); 645 pcmcia_function_disable(psc->sc_pf); 646 psc->sc_resource &= ~XI_RES_PCIC; 647 return (1); 648 } 649 650 xi_full_reset(sc); 651 652 return (0); 653 } 654 655 656 static void 657 xi_pcmcia_disable(psc) 658 struct xi_pcmcia_softc *psc; 659 { 660 DPRINTF(XID_CONFIG,("xi_pcmcia_disable()\n")); 661 662 if (psc->sc_resource & XI_RES_PCIC) { 663 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 664 pcmcia_function_disable(psc->sc_pf); 665 psc->sc_resource &= ~XI_RES_PCIC; 666 } 667 } 668 669 670 static void 671 xi_pcmcia_power(why, arg) 672 int why; 673 void *arg; 674 { 675 struct xi_pcmcia_softc *psc = arg; 676 struct xi_softc *sc = &psc->sc_xi; 677 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 678 int s; 679 680 DPRINTF(XID_CONFIG,("xi_pcmcia_power()\n")); 681 682 s = splnet(); 683 684 switch (why) { 685 case PWR_SUSPEND: 686 case PWR_STANDBY: 687 if (ifp->if_flags & IFF_RUNNING) { 688 xi_stop(sc); 689 } 690 ifp->if_flags &= ~IFF_RUNNING; 691 ifp->if_timer = 0; 692 break; 693 case PWR_RESUME: 694 if ((ifp->if_flags & IFF_RUNNING) == 0) { 695 xi_init(sc); 696 } 697 ifp->if_flags |= IFF_RUNNING; 698 break; 699 case PWR_SOFTSUSPEND: 700 case PWR_SOFTSTANDBY: 701 case PWR_SOFTRESUME: 702 break; 703 } 704 splx(s); 705 } 706 707 /* 708 * XXX These two functions might be OK to factor out into pcmcia.c since 709 * if_sm_pcmcia.c uses similar ones. 710 */ 711 static int 712 xi_pcmcia_funce_enaddr(parent, myla) 713 struct device *parent; 714 u_int8_t *myla; 715 { 716 /* XXX The Linux driver has more ways to do this in case of failure. */ 717 return (pcmcia_scan_cis(parent, xi_pcmcia_lan_nid_ciscallback, myla)); 718 } 719 720 static int 721 xi_pcmcia_lan_nid_ciscallback(tuple, arg) 722 struct pcmcia_tuple *tuple; 723 void *arg; 724 { 725 u_int8_t *myla = arg; 726 int i; 727 728 DPRINTF(XID_CONFIG, ("xi_pcmcia_lan_nid_ciscallback()\n")); 729 730 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 731 if (tuple->length < 2) 732 return (0); 733 734 switch (pcmcia_tuple_read_1(tuple, 0)) { 735 case PCMCIA_TPLFE_TYPE_LAN_NID: 736 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 737 return (0); 738 break; 739 740 case 0x02: 741 /* 742 * Not sure about this, I don't have a CE2 743 * that puts the ethernet addr here. 744 */ 745 if (pcmcia_tuple_read_1(tuple, 1) != 13) 746 return (0); 747 break; 748 749 default: 750 return (0); 751 } 752 753 for (i = 0; i < ETHER_ADDR_LEN; i++) 754 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 755 return (1); 756 } 757 758 /* Yet another spot where this might be. */ 759 if (tuple->code == 0x89) { 760 pcmcia_tuple_read_1(tuple, 1); 761 for (i = 0; i < ETHER_ADDR_LEN; i++) 762 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 763 return (1); 764 } 765 return (0); 766 } 767 768 int 769 xi_pcmcia_manfid_ciscallback(tuple, arg) 770 struct pcmcia_tuple *tuple; 771 void *arg; 772 { 773 u_int8_t *id = arg; 774 775 DPRINTF(XID_CONFIG, ("xi_pcmcia_manfid_callback()\n")); 776 777 if (tuple->code != PCMCIA_CISTPL_MANFID) 778 return (0); 779 780 if (tuple->length < 2) 781 return (0); 782 783 *id = pcmcia_tuple_read_1(tuple, 4); 784 return (1); 785 } 786 787 static int 788 xi_intr(arg) 789 void *arg; 790 { 791 struct xi_softc *sc = arg; 792 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 793 u_int8_t esr, rsr, isr, rx_status, savedpage; 794 u_int16_t tx_status, recvcount = 0, tempint; 795 796 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 797 798 #if 0 799 if (!(ifp->if_flags & IFF_RUNNING)) 800 return (0); 801 #endif 802 803 ifp->if_timer = 0; /* turn watchdog timer off */ 804 805 if (sc->sc_flags & XIFLAGS_MOHAWK) { 806 /* Disable interrupt (Linux does it). */ 807 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 808 0); 809 } 810 811 savedpage = 812 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 813 814 PAGE(sc, 0); 815 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 816 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 817 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 818 819 /* Check to see if card has been ejected. */ 820 if (isr == 0xff) { 821 #ifdef DIAGNOSTIC 822 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 823 #endif 824 goto end; 825 } 826 827 PAGE(sc, 40); 828 rx_status = 829 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 830 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0, 831 ~rx_status & 0xff); 832 tx_status = 833 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 834 tx_status |= 835 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST1) << 8; 836 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0,0); 837 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST1,0); 838 839 PAGE(sc, 0); 840 while (esr & FULL_PKT_RCV) { 841 if (!(rsr & RSR_RX_OK)) 842 break; 843 844 /* Compare bytes read this interrupt to hard maximum. */ 845 if (recvcount > MAX_BYTES_INTR) { 846 DPRINTF(XID_INTR, 847 ("xi: too many bytes this interrupt\n")); 848 ifp->if_iqdrops++; 849 /* Drop packet. */ 850 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 851 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 852 } 853 tempint = xi_get(sc); /* XXX doesn't check the error! */ 854 recvcount += tempint; 855 ifp->if_ibytes += tempint; 856 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 857 sc->sc_offset + ESR); 858 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 859 sc->sc_offset + RSR); 860 } 861 862 /* Packet too long? */ 863 if (rsr & RSR_TOO_LONG) { 864 ifp->if_ierrors++; 865 DPRINTF(XID_INTR, ("xi: packet too long\n")); 866 } 867 868 /* CRC error? */ 869 if (rsr & RSR_CRCERR) { 870 ifp->if_ierrors++; 871 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 872 } 873 874 /* Alignment error? */ 875 if (rsr & RSR_ALIGNERR) { 876 ifp->if_ierrors++; 877 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 878 } 879 880 /* Check for rx overrun. */ 881 if (rx_status & RX_OVERRUN) { 882 ifp->if_ierrors++; 883 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 884 CLR_RX_OVERRUN); 885 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 886 } 887 888 /* Try to start more packets transmitting. */ 889 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 890 xi_start(ifp); 891 892 /* Detected excessive collisions? */ 893 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 894 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 895 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 896 RESTART_TX); 897 ifp->if_oerrors++; 898 } 899 900 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 901 ifp->if_oerrors++; 902 903 /* have handled the interrupt */ 904 #if NRND > 0 905 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 906 #endif 907 908 end: 909 /* Reenable interrupts. */ 910 PAGE(sc, savedpage); 911 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 912 ENABLE_INT); 913 914 return (1); 915 } 916 917 /* 918 * Pull a packet from the card into an mbuf chain. 919 */ 920 static u_int16_t 921 xi_get(sc) 922 struct xi_softc *sc; 923 { 924 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 925 struct mbuf *top, **mp, *m; 926 u_int16_t pktlen, len, recvcount = 0; 927 u_int8_t *data; 928 u_int8_t rsr; 929 930 DPRINTF(XID_CONFIG, ("xi_get()\n")); 931 932 PAGE(sc, 0); 933 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 934 935 pktlen = 936 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 937 RBC_COUNT_MASK; 938 939 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 940 941 if (pktlen == 0) { 942 /* 943 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 944 * when MPE is set. It is not known why. 945 */ 946 return (0); 947 } 948 949 /* XXX should this be incremented now ? */ 950 recvcount += pktlen; 951 952 MGETHDR(m, M_DONTWAIT, MT_DATA); 953 if (m == 0) 954 return (recvcount); 955 m->m_pkthdr.rcvif = ifp; 956 m->m_pkthdr.len = pktlen; 957 m->m_flags |= M_HASFCS; 958 len = MHLEN; 959 top = 0; 960 mp = ⊤ 961 962 while (pktlen > 0) { 963 if (top) { 964 MGET(m, M_DONTWAIT, MT_DATA); 965 if (m == 0) { 966 m_freem(top); 967 return (recvcount); 968 } 969 len = MLEN; 970 } 971 if (pktlen >= MINCLSIZE) { 972 MCLGET(m, M_DONTWAIT); 973 if (!(m->m_flags & M_EXT)) { 974 m_freem(m); 975 m_freem(top); 976 return (recvcount); 977 } 978 len = MCLBYTES; 979 } 980 if (!top) { 981 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 982 sizeof(struct ether_header)) - 983 sizeof(struct ether_header); 984 len -= newdata - m->m_data; 985 m->m_data = newdata; 986 } 987 len = min(pktlen, len); 988 data = mtod(m, u_int8_t *); 989 if (len > 1) { 990 len &= ~1; 991 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 992 sc->sc_offset + EDP, (u_int16_t *)data, len>>1); 993 } else 994 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 995 sc->sc_offset + EDP); 996 m->m_len = len; 997 pktlen -= len; 998 *mp = m; 999 mp = &m->m_next; 1000 } 1001 1002 /* Skip Rx packet. */ 1003 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 1004 DO_SKIP_RX_PKT); 1005 1006 ifp->if_ipackets++; 1007 1008 #if NBPFILTER > 0 1009 if (ifp->if_bpf) 1010 bpf_mtap(ifp->if_bpf, top); 1011 #endif 1012 1013 (*ifp->if_input)(ifp, top); 1014 return (recvcount); 1015 } 1016 1017 /* 1018 * Serial management for the MII. 1019 * The DELAY's below stem from the fact that the maximum frequency 1020 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 1021 * go much faster than that. 1022 */ 1023 1024 /* Let the MII serial management be idle for one period. */ 1025 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 1026 static INLINE void 1027 xi_mdi_idle(sc) 1028 struct xi_softc *sc; 1029 { 1030 bus_space_tag_t bst = sc->sc_bst; 1031 bus_space_handle_t bsh = sc->sc_bsh; 1032 bus_size_t offset = sc->sc_offset; 1033 1034 /* Drive MDC low... */ 1035 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1036 DELAY(1); 1037 1038 /* and high again. */ 1039 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1040 DELAY(1); 1041 } 1042 1043 /* Pulse out one bit of data. */ 1044 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 1045 static INLINE void 1046 xi_mdi_pulse(sc, data) 1047 struct xi_softc *sc; 1048 int data; 1049 { 1050 bus_space_tag_t bst = sc->sc_bst; 1051 bus_space_handle_t bsh = sc->sc_bsh; 1052 bus_size_t offset = sc->sc_offset; 1053 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 1054 1055 /* First latch the data bit MDIO with clock bit MDC low...*/ 1056 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 1057 DELAY(1); 1058 1059 /* then raise the clock again, preserving the data bit. */ 1060 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 1061 DELAY(1); 1062 } 1063 1064 /* Probe one bit of data. */ 1065 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 1066 static INLINE int 1067 xi_mdi_probe(sc) 1068 struct xi_softc *sc; 1069 { 1070 bus_space_tag_t bst = sc->sc_bst; 1071 bus_space_handle_t bsh = sc->sc_bsh; 1072 bus_size_t offset = sc->sc_offset; 1073 u_int8_t x; 1074 1075 /* Pull clock bit MDCK low... */ 1076 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1077 DELAY(1); 1078 1079 /* Read data and drive clock high again. */ 1080 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 1081 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1082 DELAY(1); 1083 1084 return (x); 1085 } 1086 1087 /* Pulse out a sequence of data bits. */ 1088 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 1089 static INLINE void 1090 xi_mdi_pulse_bits(sc, data, len) 1091 struct xi_softc *sc; 1092 u_int32_t data; 1093 int len; 1094 { 1095 u_int32_t mask; 1096 1097 for (mask = 1 << (len - 1); mask; mask >>= 1) 1098 xi_mdi_pulse(sc, data & mask); 1099 } 1100 1101 /* Read a PHY register. */ 1102 static int 1103 xi_mdi_read(self, phy, reg) 1104 struct device *self; 1105 int phy; 1106 int reg; 1107 { 1108 struct xi_softc *sc = (struct xi_softc *)self; 1109 int i; 1110 u_int32_t mask; 1111 u_int32_t data = 0; 1112 1113 PAGE(sc, 2); 1114 for (i = 0; i < 32; i++) /* Synchronize. */ 1115 xi_mdi_pulse(sc, 1); 1116 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 1117 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1118 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1119 xi_mdi_idle(sc); /* Turn around. */ 1120 xi_mdi_probe(sc); /* Drop initial zero bit. */ 1121 1122 for (mask = 1 << 15; mask; mask >>= 1) { 1123 if (xi_mdi_probe(sc)) 1124 data |= mask; 1125 } 1126 xi_mdi_idle(sc); 1127 1128 DPRINTF(XID_MII, 1129 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 1130 1131 return (data); 1132 } 1133 1134 /* Write a PHY register. */ 1135 static void 1136 xi_mdi_write(self, phy, reg, value) 1137 struct device *self; 1138 int phy; 1139 int reg; 1140 int value; 1141 { 1142 struct xi_softc *sc = (struct xi_softc *)self; 1143 int i; 1144 1145 PAGE(sc, 2); 1146 for (i = 0; i < 32; i++) /* Synchronize. */ 1147 xi_mdi_pulse(sc, 1); 1148 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 1149 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1150 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1151 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 1152 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 1153 xi_mdi_idle(sc); /* Idle away. */ 1154 1155 DPRINTF(XID_MII, 1156 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 1157 } 1158 1159 static void 1160 xi_statchg(self) 1161 struct device *self; 1162 { 1163 /* XXX Update ifp->if_baudrate */ 1164 } 1165 1166 /* 1167 * Change media according to request. 1168 */ 1169 static int 1170 xi_mediachange(ifp) 1171 struct ifnet *ifp; 1172 { 1173 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 1174 1175 if (ifp->if_flags & IFF_UP) 1176 xi_init(ifp->if_softc); 1177 return (0); 1178 } 1179 1180 /* 1181 * Notify the world which media we're using. 1182 */ 1183 static void 1184 xi_mediastatus(ifp, ifmr) 1185 struct ifnet *ifp; 1186 struct ifmediareq *ifmr; 1187 { 1188 struct xi_softc *sc = ifp->if_softc; 1189 1190 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 1191 1192 mii_pollstat(&sc->sc_mii); 1193 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1194 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1195 } 1196 1197 static void 1198 xi_reset(sc) 1199 struct xi_softc *sc; 1200 { 1201 int s; 1202 1203 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 1204 1205 s = splnet(); 1206 xi_stop(sc); 1207 xi_full_reset(sc); 1208 xi_init(sc); 1209 splx(s); 1210 } 1211 1212 static void 1213 xi_watchdog(ifp) 1214 struct ifnet *ifp; 1215 { 1216 struct xi_softc *sc = ifp->if_softc; 1217 1218 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1219 ++ifp->if_oerrors; 1220 1221 xi_reset(sc); 1222 } 1223 1224 static void 1225 xi_stop(sc) 1226 register struct xi_softc *sc; 1227 { 1228 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 1229 1230 /* Disable interrupts. */ 1231 PAGE(sc, 0); 1232 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1233 1234 PAGE(sc, 1); 1235 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1236 1237 /* Power down, wait. */ 1238 PAGE(sc, 4); 1239 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1240 DELAY(40000); 1241 1242 /* Cancel watchdog timer. */ 1243 sc->sc_ethercom.ec_if.if_timer = 0; 1244 } 1245 1246 static void 1247 xi_init(sc) 1248 struct xi_softc *sc; 1249 { 1250 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)sc; 1251 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1252 int s; 1253 1254 DPRINTF(XID_CONFIG, ("xi_init()\n")); 1255 1256 if ((psc->sc_resource & XI_RES_PCIC) == 0) 1257 xi_pcmcia_enable(psc); 1258 1259 s = splnet(); 1260 1261 xi_set_address(sc); 1262 1263 /* Set current media. */ 1264 mii_mediachg(&sc->sc_mii); 1265 1266 ifp->if_flags |= IFF_RUNNING; 1267 ifp->if_flags &= ~IFF_OACTIVE; 1268 splx(s); 1269 } 1270 1271 /* 1272 * Start outputting on the interface. 1273 * Always called as splnet(). 1274 */ 1275 static void 1276 xi_start(ifp) 1277 struct ifnet *ifp; 1278 { 1279 struct xi_softc *sc = ifp->if_softc; 1280 bus_space_tag_t bst = sc->sc_bst; 1281 bus_space_handle_t bsh = sc->sc_bsh; 1282 bus_size_t offset = sc->sc_offset; 1283 unsigned int s, len, pad = 0; 1284 struct mbuf *m0, *m; 1285 u_int16_t space; 1286 1287 DPRINTF(XID_CONFIG, ("xi_start()\n")); 1288 1289 /* Don't transmit if interface is busy or not running. */ 1290 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1291 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 1292 return; 1293 } 1294 1295 /* Peek at the next packet. */ 1296 IFQ_POLL(&ifp->if_snd, m0); 1297 if (m0 == 0) 1298 return; 1299 1300 /* We need to use m->m_pkthdr.len, so require the header. */ 1301 if (!(m0->m_flags & M_PKTHDR)) 1302 panic("xi_start: no header mbuf"); 1303 1304 len = m0->m_pkthdr.len; 1305 1306 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1307 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1308 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1309 1310 PAGE(sc, 0); 1311 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1312 if (len + pad + 2 > space) { 1313 DPRINTF(XID_FIFO, 1314 ("xi: not enough space in output FIFO (%d > %d)\n", 1315 len + pad + 2, space)); 1316 return; 1317 } 1318 1319 IFQ_DEQUEUE(&ifp->if_snd, m0); 1320 1321 #if NBPFILTER > 0 1322 if (ifp->if_bpf) 1323 bpf_mtap(ifp->if_bpf, m0); 1324 #endif 1325 1326 /* 1327 * Do the output at splhigh() so that an interrupt from another device 1328 * won't cause a FIFO underrun. 1329 */ 1330 s = splhigh(); 1331 1332 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1333 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1334 for (m = m0; m; ) { 1335 if (m->m_len > 1) 1336 bus_space_write_multi_2(bst, bsh, offset + EDP, 1337 mtod(m, u_int16_t *), m->m_len>>1); 1338 if (m->m_len & 1) 1339 bus_space_write_1(bst, bsh, offset + EDP, 1340 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1341 MFREE(m, m0); 1342 m = m0; 1343 } 1344 if (sc->sc_flags & XIFLAGS_MOHAWK) 1345 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1346 else { 1347 for (; pad > 1; pad -= 2) 1348 bus_space_write_2(bst, bsh, offset + EDP, 0); 1349 if (pad == 1) 1350 bus_space_write_1(bst, bsh, offset + EDP, 0); 1351 } 1352 1353 splx(s); 1354 1355 ifp->if_timer = 5; 1356 ++ifp->if_opackets; 1357 } 1358 1359 static int 1360 xi_ether_ioctl(ifp, cmd, data) 1361 struct ifnet *ifp; 1362 u_long cmd; 1363 caddr_t data; 1364 { 1365 struct ifaddr *ifa = (struct ifaddr *)data; 1366 struct xi_softc *sc = ifp->if_softc; 1367 1368 1369 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 1370 1371 switch (cmd) { 1372 case SIOCSIFADDR: 1373 ifp->if_flags |= IFF_UP; 1374 1375 switch (ifa->ifa_addr->sa_family) { 1376 #ifdef INET 1377 case AF_INET: 1378 xi_init(sc); 1379 arp_ifinit(ifp, ifa); 1380 break; 1381 #endif /* INET */ 1382 1383 #ifdef NS 1384 case AF_NS: 1385 { 1386 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1387 1388 if (ns_nullhost(*ina)) 1389 ina->x_host = *(union ns_host *) 1390 LLADDR(ifp->if_sadl); 1391 else 1392 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1393 ifp->if_addrlen); 1394 /* Set new address. */ 1395 xi_init(sc); 1396 break; 1397 } 1398 #endif /* NS */ 1399 1400 default: 1401 xi_init(sc); 1402 break; 1403 } 1404 break; 1405 1406 default: 1407 return (EINVAL); 1408 } 1409 1410 return (0); 1411 } 1412 1413 static int 1414 xi_ioctl(ifp, command, data) 1415 struct ifnet *ifp; 1416 u_long command; 1417 caddr_t data; 1418 { 1419 struct xi_pcmcia_softc *psc = ifp->if_softc; 1420 struct xi_softc *sc = &psc->sc_xi; 1421 struct ifreq *ifr = (struct ifreq *)data; 1422 int s, error = 0; 1423 1424 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1425 1426 s = splnet(); 1427 1428 switch (command) { 1429 case SIOCSIFADDR: 1430 error = xi_ether_ioctl(ifp, command, data); 1431 break; 1432 1433 case SIOCSIFFLAGS: 1434 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1435 1436 PAGE(sc, 0x42); 1437 if ((ifp->if_flags & IFF_PROMISC) || 1438 (ifp->if_flags & IFF_ALLMULTI)) 1439 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1440 sc->sc_offset + SWC1, 1441 SWC1_PROMISC | SWC1_MCAST_PROM); 1442 else 1443 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1444 sc->sc_offset + SWC1, 0); 1445 1446 /* 1447 * If interface is marked up and not running, then start it. 1448 * If it is marked down and running, stop it. 1449 * XXX If it's up then re-initialize it. This is so flags 1450 * such as IFF_PROMISC are handled. 1451 */ 1452 if (ifp->if_flags & IFF_UP) { 1453 xi_init(sc); 1454 } else { 1455 if (ifp->if_flags & IFF_RUNNING) { 1456 xi_pcmcia_disable(psc); 1457 xi_stop(sc); 1458 ifp->if_flags &= ~IFF_RUNNING; 1459 } 1460 } 1461 break; 1462 1463 case SIOCADDMULTI: 1464 case SIOCDELMULTI: 1465 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1466 error = (command == SIOCADDMULTI) ? 1467 ether_addmulti(ifr, &sc->sc_ethercom) : 1468 ether_delmulti(ifr, &sc->sc_ethercom); 1469 1470 if (error == ENETRESET) { 1471 /* 1472 * Multicast list has changed; set the hardware 1473 * filter accordingly. 1474 */ 1475 if (!sc->sc_all_mcasts && 1476 !(ifp->if_flags & IFF_PROMISC)) 1477 xi_set_address(sc); 1478 1479 /* 1480 * xi_set_address() can turn on all_mcasts if we run 1481 * out of space, so check it again rather than else {}. 1482 */ 1483 if (sc->sc_all_mcasts) 1484 xi_init(sc); 1485 error = 0; 1486 } 1487 break; 1488 1489 case SIOCSIFMEDIA: 1490 case SIOCGIFMEDIA: 1491 error = 1492 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1493 break; 1494 1495 default: 1496 error = EINVAL; 1497 } 1498 splx(s); 1499 return (error); 1500 } 1501 1502 static void 1503 xi_set_address(sc) 1504 struct xi_softc *sc; 1505 { 1506 bus_space_tag_t bst = sc->sc_bst; 1507 bus_space_handle_t bsh = sc->sc_bsh; 1508 bus_size_t offset = sc->sc_offset; 1509 struct ethercom *ether = &sc->sc_ethercom; 1510 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1511 #if WORKING_MULTICAST 1512 struct ether_multistep step; 1513 struct ether_multi *enm; 1514 int page, pos, num; 1515 #endif 1516 int i; 1517 1518 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1519 1520 PAGE(sc, 0x50); 1521 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1522 bus_space_write_1(bst, bsh, offset + IA + i, 1523 sc->sc_enaddr[(sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1524 } 1525 1526 if (ether->ec_multicnt > 0) { 1527 #ifdef WORKING_MULTICAST 1528 if (ether->ec_multicnt > 9) { 1529 #else 1530 { 1531 #endif 1532 PAGE(sc, 0x42); 1533 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1534 sc->sc_offset + SWC1, 1535 SWC1_PROMISC | SWC1_MCAST_PROM); 1536 ifp->if_flags |= IFF_PROMISC; 1537 return; 1538 } 1539 1540 #ifdef WORKING_MULTICAST 1541 1542 ETHER_FIRST_MULTI(step, ether, enm); 1543 1544 pos = IA + 6; 1545 for (page = 0x50, num = ether->ec_multicnt; num > 0 && enm; 1546 num--) { 1547 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1548 sizeof(enm->enm_addrlo)) != 0) { 1549 /* 1550 * The multicast address is really a range; 1551 * it's easier just to accept all multicasts. 1552 * XXX should we be setting IFF_ALLMULTI here? 1553 */ 1554 #if 0 1555 ifp->if_flags |= IFF_ALLMULTI; 1556 #endif 1557 sc->sc_all_mcasts=1; 1558 break; 1559 } 1560 1561 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1562 printf("%x:", enm->enm_addrlo[i]); 1563 bus_space_write_1(bst, bsh, offset + pos, 1564 enm->enm_addrlo[ 1565 (sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1566 1567 if (++pos > 15) { 1568 pos = IA; 1569 page++; 1570 PAGE(sc, page); 1571 } 1572 } 1573 printf("\n"); 1574 ETHER_NEXT_MULTI(step, enm); 1575 } 1576 #endif 1577 } 1578 } 1579 1580 static void 1581 xi_cycle_power(sc) 1582 struct xi_softc *sc; 1583 { 1584 bus_space_tag_t bst = sc->sc_bst; 1585 bus_space_handle_t bsh = sc->sc_bsh; 1586 bus_size_t offset = sc->sc_offset; 1587 1588 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1589 1590 PAGE(sc, 4); 1591 DELAY(1); 1592 bus_space_write_1(bst, bsh, offset + GP1, 0); 1593 DELAY(40000); 1594 if (sc->sc_flags & XIFLAGS_MOHAWK) 1595 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1596 else 1597 /* XXX What is bit 2 (aka AIC)? */ 1598 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1599 DELAY(20000); 1600 } 1601 1602 static void 1603 xi_full_reset(sc) 1604 struct xi_softc *sc; 1605 { 1606 bus_space_tag_t bst = sc->sc_bst; 1607 bus_space_handle_t bsh = sc->sc_bsh; 1608 bus_size_t offset = sc->sc_offset; 1609 1610 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1611 1612 /* Do an as extensive reset as possible on all functions. */ 1613 xi_cycle_power(sc); 1614 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1615 DELAY(20000); 1616 bus_space_write_1(bst, bsh, offset + CR, 0); 1617 DELAY(20000); 1618 if (sc->sc_flags & XIFLAGS_MOHAWK) { 1619 PAGE(sc, 4); 1620 /* 1621 * Drive GP1 low to power up ML6692 and GP2 high to power up 1622 * the 10MHz chip. XXX What chip is that? The phy? 1623 */ 1624 bus_space_write_1(bst, bsh, offset + GP0, 1625 GP1_OUT | GP2_OUT | GP2_WR); 1626 } 1627 DELAY(500000); 1628 1629 /* Get revision information. XXX Symbolic constants. */ 1630 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1631 ((sc->sc_flags & XIFLAGS_MOHAWK) ? 0x70 : 0x30) >> 4; 1632 1633 /* Media selection. XXX Maybe manual overriding too? */ 1634 if (!(sc->sc_flags & XIFLAGS_MOHAWK)) { 1635 PAGE(sc, 4); 1636 /* 1637 * XXX I have no idea what this really does, it is from the 1638 * Linux driver. 1639 */ 1640 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1641 } 1642 DELAY(40000); 1643 1644 /* Setup the ethernet interrupt mask. */ 1645 PAGE(sc, 1); 1646 #if 1 1647 bus_space_write_1(bst, bsh, offset + IMR0, 1648 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1649 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1650 #else 1651 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1652 #endif 1653 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1654 /* XXX What is this? Not for Dingo at least. */ 1655 /* Unmask TX underrun detection */ 1656 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1657 } 1658 1659 /* 1660 * Disable source insertion. 1661 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1662 */ 1663 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1664 PAGE(sc, 0x42); 1665 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1666 } 1667 1668 /* Set the local memory dividing line. */ 1669 if (sc->sc_rev != 1) { 1670 PAGE(sc, 2); 1671 /* XXX Symbolic constant preferrable. */ 1672 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1673 } 1674 1675 xi_set_address(sc); 1676 1677 /* 1678 * Apparently the receive byte pointer can be bad after a reset, so 1679 * we hardwire it correctly. 1680 */ 1681 PAGE(sc, 0); 1682 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1683 1684 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1685 PAGE(sc, 0x40); 1686 bus_space_write_1(bst, bsh, offset + RX0MSK, 1687 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1688 bus_space_write_1(bst, bsh, offset + TX0MSK, 1689 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1690 SQE | TX_ABORT | TX_OK); 1691 if (!(sc->sc_flags & XIFLAGS_DINGO)) 1692 /* XXX From Linux, dunno what 0xb0 means. */ 1693 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1694 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1695 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1696 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1697 1698 /* Enable MII function if available. */ 1699 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1700 PAGE(sc, 2); 1701 bus_space_write_1(bst, bsh, offset + MSR, 1702 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1703 DELAY(20000); 1704 } else { 1705 PAGE(sc, 0); 1706 1707 /* XXX Do we need to do this? */ 1708 PAGE(sc, 0x42); 1709 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1710 DELAY(50000); 1711 1712 /* XXX Linux probes the media here. */ 1713 } 1714 1715 /* Configure the LED registers. */ 1716 PAGE(sc, 2); 1717 1718 /* XXX This is not good for 10base2. */ 1719 bus_space_write_1(bst, bsh, offset + LED, 1720 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1721 if (sc->sc_flags & XIFLAGS_DINGO) 1722 bus_space_write_1(bst, bsh, offset + LED3, 1723 LED_100MB_LINK << LED3_SHIFT); 1724 1725 /* Enable receiver and go online. */ 1726 PAGE(sc, 0x40); 1727 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1728 1729 #if 0 1730 /* XXX Linux does this here - is it necessary? */ 1731 PAGE(sc, 1); 1732 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1733 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1734 /* XXX What is this? Not for Dingo at least. */ 1735 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1736 } 1737 #endif 1738 1739 /* Enable interrupts. */ 1740 PAGE(sc, 0); 1741 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1742 1743 /* XXX This is pure magic for me, found in the Linux driver. */ 1744 if ((sc->sc_flags & (XIFLAGS_DINGO | XIFLAGS_MODEM)) == XIFLAGS_MODEM) { 1745 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1746 /* Unmask the master interrupt bit. */ 1747 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1748 } 1749 1750 /* 1751 * The Linux driver says this: 1752 * We should switch back to page 0 to avoid a bug in revision 0 1753 * where regs with offset below 8 can't be read after an access 1754 * to the MAC registers. 1755 */ 1756 PAGE(sc, 0); 1757 }
Cache object: e50012ed9dbc83c1942e46645e90aaa7
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]