Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pcmcia/isic_pcmcia_sbspeedstar2.c
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1 /*- 2 * Copyright (c) 2002 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Martin Husemann <martin@NetBSD.org>. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: isic_pcmcia_sbspeedstar2.c,v 1.6 2003/12/04 13:57:31 keihan Exp $"); 39 40 #include "opt_isicpcmcia.h" 41 #ifdef ISICPCMCIA_SBSPEEDSTAR2 42 43 /* 44 * Card format: 45 * 46 * iobase + 0 : reset on (0x03), off (0x0) 47 * iobase + 1 : isac read/write 48 * iobase + 2 : hscx read/write ( offset 0-0x3f hscx0 , 49 * offset 0x40-0x7f hscx1 ) 50 * iobase + 4 : address register 51 * 52 */ 53 54 #define SBSS_RESET 0 /* reset on / off */ 55 #define SBSS_ISAC 1 /* ISAC */ 56 #define SBSS_HSCX 2 /* HSCX0 */ 57 #define SBSS_RW 4 /* indirect access register */ 58 59 #define SBSS_REGS 8 /* we use an area of 8 bytes for io */ 60 61 #include <sys/param.h> 62 #include <sys/callout.h> 63 #include <sys/kernel.h> 64 #include <sys/systm.h> 65 #include <sys/mbuf.h> 66 #include <sys/device.h> 67 #include <machine/bus.h> 68 #include <sys/socket.h> 69 #include <net/if.h> 70 #include <netisdn/i4b_debug.h> 71 #include <netisdn/i4b_ioctl.h> 72 #include <netisdn/i4b_l2.h> 73 #include <netisdn/i4b_l1l2.h> 74 75 #include <dev/ic/isic_l1.h> 76 #include <dev/ic/isac.h> 77 #include <dev/ic/hscx.h> 78 79 #include <netisdn/i4b_global.h> 80 #include <netisdn/i4b_l1l2.h> 81 #include <netisdn/i4b_mbuf.h> 82 #include <dev/pcmcia/pcmciareg.h> 83 #include <dev/pcmcia/pcmciavar.h> 84 85 #include <dev/pcmcia/isic_pcmcia.h> 86 87 /*---------------------------------------------------------------------------* 88 * Sedlbauer SpeedStar ISAC get fifo routine 89 *---------------------------------------------------------------------------*/ 90 91 static void 92 sws_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size) 93 { 94 bus_space_tag_t t = sc->sc_maps[0].t; 95 bus_space_handle_t h = sc->sc_maps[0].h; 96 switch (what) { 97 case ISIC_WHAT_ISAC: 98 bus_space_write_1(t, h, SBSS_RW, 0); 99 bus_space_read_multi_1(t, h, SBSS_ISAC, buf, size); 100 break; 101 case ISIC_WHAT_HSCXA: 102 bus_space_write_1(t, h, SBSS_RW, 0); 103 bus_space_read_multi_1(t, h, SBSS_HSCX, buf, size); 104 break; 105 case ISIC_WHAT_HSCXB: 106 bus_space_write_1(t, h, SBSS_RW, 0x40); 107 bus_space_read_multi_1(t, h, SBSS_HSCX, buf, size); 108 break; 109 } 110 } 111 112 /*---------------------------------------------------------------------------* 113 * Sedlbauer SpeedStar ISAC put fifo routine 114 *---------------------------------------------------------------------------*/ 115 116 static void 117 sws_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size) 118 { 119 bus_space_tag_t t = sc->sc_maps[0].t; 120 bus_space_handle_t h = sc->sc_maps[0].h; 121 switch (what) { 122 case ISIC_WHAT_ISAC: 123 bus_space_write_1(t, h, SBSS_RW, 0); 124 bus_space_write_multi_1(t, h, SBSS_ISAC, (u_int8_t*)buf, size); 125 break; 126 case ISIC_WHAT_HSCXA: 127 bus_space_write_1(t, h, SBSS_RW, 0); 128 bus_space_write_multi_1(t, h, SBSS_HSCX, (u_int8_t*)buf, size); 129 break; 130 case ISIC_WHAT_HSCXB: 131 bus_space_write_1(t, h, SBSS_RW, 0x40); 132 bus_space_write_multi_1(t, h, SBSS_HSCX, (u_int8_t*)buf, size); 133 break; 134 } 135 } 136 137 /*---------------------------------------------------------------------------* 138 * Sedlbauer SpeedStar ISAC put register routine 139 *---------------------------------------------------------------------------*/ 140 141 static void 142 sws_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data) 143 { 144 bus_space_tag_t t = sc->sc_maps[0].t; 145 bus_space_handle_t h = sc->sc_maps[0].h; 146 switch (what) { 147 case ISIC_WHAT_ISAC: 148 bus_space_write_1(t, h, SBSS_RW, offs); 149 bus_space_write_1(t, h, SBSS_ISAC, data); 150 break; 151 case ISIC_WHAT_HSCXA: 152 bus_space_write_1(t, h, SBSS_RW, offs); 153 bus_space_write_1(t, h, SBSS_HSCX, data); 154 break; 155 case ISIC_WHAT_HSCXB: 156 bus_space_write_1(t, h, SBSS_RW, 0x40+offs); 157 bus_space_write_1(t, h, SBSS_HSCX, data); 158 break; 159 } 160 } 161 162 /*---------------------------------------------------------------------------* 163 * Sedlbauer SpeedStar ISAC get register routine 164 *---------------------------------------------------------------------------*/ 165 166 static u_int8_t 167 sws_read_reg(struct isic_softc *sc, int what, bus_size_t offs) 168 { 169 bus_space_tag_t t = sc->sc_maps[0].t; 170 bus_space_handle_t h = sc->sc_maps[0].h; 171 switch (what) { 172 case ISIC_WHAT_ISAC: 173 bus_space_write_1(t, h, SBSS_RW, offs); 174 return bus_space_read_1(t, h, SBSS_ISAC); 175 case ISIC_WHAT_HSCXA: 176 bus_space_write_1(t, h, SBSS_RW, offs); 177 return bus_space_read_1(t, h, SBSS_HSCX); 178 case ISIC_WHAT_HSCXB: 179 bus_space_write_1(t, h, SBSS_RW, 0x40+offs); 180 return bus_space_read_1(t, h, SBSS_HSCX); 181 } 182 return 0; 183 } 184 185 /* 186 * XXX - one time only! Some of this has to go into an enable 187 * function, with apropriate counterpart in disable, so a card 188 * could be removed an inserted again. 189 */ 190 int 191 isic_attach_sbspeedstar2(struct pcmcia_isic_softc *psc, struct pcmcia_config_entry *cfe, struct pcmcia_attach_args *pa) 192 { 193 struct isic_softc * sc = &psc->sc_isic; 194 bus_space_tag_t t; 195 bus_space_handle_t h; 196 197 /* Validate config info */ 198 if (cfe->num_memspace != 0) 199 printf(": unexpected number of memory spaces %d should be 0\n", 200 cfe->num_memspace); 201 if (cfe->num_iospace != 1) 202 printf(": unexpected number of memory spaces %d should be 1\n", 203 cfe->num_iospace); 204 205 /* Allocate pcmcia space */ 206 if (pcmcia_io_alloc(pa->pf, 0, cfe->iospace[0].length, 207 cfe->iospace[0].length, &psc->sc_pcioh)) 208 printf(": can't allocate i/o space\n"); 209 210 /* map them */ 211 if (pcmcia_io_map(pa->pf, ((cfe->flags & PCMCIA_CFE_IO16) ? 212 PCMCIA_WIDTH_IO16 : PCMCIA_WIDTH_IO8), 0, 213 cfe->iospace[0].length, &psc->sc_pcioh, &psc->sc_io_window)) { 214 printf(": can't map i/o space\n"); 215 return 0; 216 } 217 218 /* Setup bus space maps */ 219 sc->sc_num_mappings = 1; 220 MALLOC_MAPS(sc); 221 222 /* Copy our handles/tags to the MI maps */ 223 sc->sc_maps[0].t = psc->sc_pcioh.iot; 224 sc->sc_maps[0].h = psc->sc_pcioh.ioh; 225 sc->sc_maps[0].offset = 0; 226 sc->sc_maps[0].size = 0; /* not our mapping */ 227 228 t = sc->sc_maps[0].t; 229 h = sc->sc_maps[0].h; 230 231 /* setup access routines */ 232 233 sc->readreg = sws_read_reg; 234 sc->writereg = sws_write_reg; 235 236 sc->readfifo = sws_read_fifo; 237 sc->writefifo = sws_write_fifo; 238 239 /* setup IOM bus type */ 240 241 sc->sc_bustyp = BUS_TYPE_IOM2; 242 243 sc->sc_ipac = 0; 244 sc->sc_bfifolen = HSCX_FIFO_LEN; 245 246 /* reset card */ 247 { 248 bus_space_tag_t t = sc->sc_maps[0].t; 249 bus_space_handle_t h = sc->sc_maps[0].h; 250 bus_space_write_1(t, h, SBSS_RESET, 0x3); 251 DELAY(SEC_DELAY / 5); 252 bus_space_write_1(t, h, SBSS_RESET, 0); 253 DELAY(SEC_DELAY / 5); 254 } 255 256 return 1; 257 } 258 259 #endif /* ISICPCMCIA_SBSPEEDSTAR2 */
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