FreeBSD/Linux Kernel Cross Reference
sys/dev/pdq/pdqreg.h
1 /*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * $FreeBSD$
25 *
26 */
27
28 /*
29 * DEC PDQ FDDI Controller; PDQ port driver definitions
30 *
31 */
32
33 #ifndef _PDQREG_H
34 #define _PDQREG_H
35
36 #include <stddef.h>
37 #if defined(PDQTEST) && !defined(PDQ_NDEBUG)
38 #include <assert.h>
39 #define PDQ_ASSERT assert
40 #else
41 #define PDQ_ASSERT(x) do { } while(0)
42 #endif
43
44 #define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0])))
45 #define PDQ_ARRAY_SIZE(array) ((sizeof(array) / sizeof(array[0])))
46 #define PDQ_RING_MASK(array) (PDQ_RING_SIZE(array) - 1)
47 #define PDQ_BITMASK(n) (1L << (pdq_uint32_t) (n))
48
49 #define PDQ_FDDI_MAX 4495
50 #define PDQ_FDDI_LLC_MIN 20
51 #define PDQ_FDDI_SMT_MIN 37
52
53 #define PDQ_FDDI_SMT 0x40
54 #define PDQ_FDDI_LLC_ASYNC 0x50
55 #define PDQ_FDDI_LLC_SYNC 0xD0
56 #define PDQ_FDDI_IMP_ASYNC 0x60
57 #define PDQ_FDDI_IMP_SYNC 0xE0
58
59 #define PDQ_FDDIFC_C 0x80
60 #define PDQ_FDDIFC_L 0x40
61 #define PDQ_FDDIFC_F 0x30
62 #define PDQ_FDDIFC_Z 0x0F
63
64 #define PDQ_FDDI_PH0 0x20
65 #define PDQ_FDDI_PH1 0x38
66 #define PDQ_FDDI_PH2 0x00
67
68 typedef pdq_uint32_t pdq_physaddr_t;
69
70 struct _pdq_lanaddr_t {
71 pdq_uint8_t lanaddr_bytes[8];
72 };
73
74 typedef struct {
75 pdq_uint8_t fwrev_bytes[4];
76 } pdq_fwrev_t;
77
78 enum _pdq_state_t {
79 PDQS_RESET=0,
80 PDQS_UPGRADE=1,
81 PDQS_DMA_UNAVAILABLE=2,
82 PDQS_DMA_AVAILABLE=3,
83 PDQS_LINK_AVAILABLE=4,
84 PDQS_LINK_UNAVAILABLE=5,
85 PDQS_HALTED=6,
86 PDQS_RING_MEMBER=7
87 };
88
89 struct _pdq_csrs_t {
90 pdq_bus_memoffset_t csr_port_reset; /* 0x00 [RW] */
91 pdq_bus_memoffset_t csr_host_data; /* 0x04 [R] */
92 pdq_bus_memoffset_t csr_port_control; /* 0x08 [RW] */
93 pdq_bus_memoffset_t csr_port_data_a; /* 0x0C [RW] */
94 pdq_bus_memoffset_t csr_port_data_b; /* 0x10 [RW] */
95 pdq_bus_memoffset_t csr_port_status; /* 0x14 [R] */
96 pdq_bus_memoffset_t csr_host_int_type_0; /* 0x18 [RW] */
97 pdq_bus_memoffset_t csr_host_int_enable; /* 0x1C [RW] */
98 pdq_bus_memoffset_t csr_type_2_producer; /* 0x20 [RW] */
99 pdq_bus_memoffset_t csr_cmd_response_producer; /* 0x28 [RW] */
100 pdq_bus_memoffset_t csr_cmd_request_producer; /* 0x2C [RW] */
101 pdq_bus_memoffset_t csr_host_smt_producer; /* 0x30 [RW] */
102 pdq_bus_memoffset_t csr_unsolicited_producer; /* 0x34 [RW] */
103 pdq_bus_t csr_bus;
104 pdq_bus_memaddr_t csr_base;
105 };
106
107 struct _pdq_pci_csrs_t {
108 pdq_bus_memoffset_t csr_pfi_mode_control; /* 0x40 [RW] */
109 pdq_bus_memoffset_t csr_pfi_status; /* 0x44 [RW] */
110 pdq_bus_memoffset_t csr_fifo_write; /* 0x48 [RW] */
111 pdq_bus_memoffset_t csr_fifo_read; /* 0x4C [RW] */
112 pdq_bus_t csr_bus;
113 pdq_bus_memaddr_t csr_base;
114 };
115
116 #define PDQ_PFI_MODE_DMA_ENABLE 0x01 /* DMA Enable */
117 #define PDQ_PFI_MODE_PFI_PCI_INTR 0x02 /* PFI-to-PCI Int Enable */
118 #define PDQ_PFI_MODE_PDQ_PCI_INTR 0x04 /* PDQ-to-PCI Int Enable */
119
120 #define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */
121 #define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */
122
123 #define PDQ_EISA_BURST_HOLDOFF 0x0040
124 #define PDQ_EISA_SLOT_ID 0x0C80
125 #define PDQ_EISA_SLOT_CTRL 0x0C84
126 #define PDQ_EISA_MEM_ADD_CMP_0 0x0C85
127 #define PDQ_EISA_MEM_ADD_CMP_1 0x0C86
128 #define PDQ_EISA_MEM_ADD_CMP_2 0x0C87
129 #define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88
130 #define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89
131 #define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A
132 #define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B
133 #define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C
134 #define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D
135 #define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E
136 #define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F
137 #define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90
138 #define PDQ_EISA_IO_CMP_0_0 0x0C91
139 #define PDQ_EISA_IO_CMP_0_1 0x0C92
140 #define PDQ_EISA_IO_CMP_1_0 0x0C93
141 #define PDQ_EISA_IO_CMP_1_1 0x0C94
142 #define PDQ_EISA_IO_CMP_2_0 0x0C95
143 #define PDQ_EISA_IO_CMP_2_1 0x0C96
144 #define PDQ_EISA_IO_CMP_3_0 0x0C97
145 #define PDQ_EISA_IO_CMP_3_1 0x0C98
146 #define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99
147 #define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A
148 #define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B
149 #define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C
150 #define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D
151 #define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E
152 #define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F
153 #define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0
154 #define PDQ_EISA_MOD_CONFIG_1 0x0CA1
155 #define PDQ_EISA_MOD_CONFIG_2 0x0CA2
156 #define PDQ_EISA_MOD_CONFIG_3 0x0CA3
157 #define PDQ_EISA_MOD_CONFIG_4 0x0CA4
158 #define PDQ_EISA_MOD_CONFIG_5 0x0CA5
159 #define PDQ_EISA_MOD_CONFIG_6 0x0CA6
160 #define PDQ_EISA_MOD_CONFIG_7 0x0CA7
161 #define PDQ_EISA_DIP_SWITCH 0x0CA8
162 #define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9
163 #define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA
164 #define PDQ_EISA_DMA_CONFIG 0x0CAB
165 #define PDQ_EISA_INPUT_PORT 0x0CAC
166 #define PDQ_EISA_OUTPUT_PORT 0x0CAD
167 #define PDQ_EISA_FUNCTION_CTRL 0x0CAE
168
169 #define PDQ_TC_CSR_OFFSET 0x00100000
170 #define PDQ_TC_CSR_SPACE 0x0040
171 #define PDQ_FBUS_CSR_OFFSET 0x00200000
172 #define PDQ_FBUS_CSR_SPACE 0x0080
173
174 /*
175 * Port Reset Data A Definitions
176 */
177 #define PDQ_PRESET_SKIP_SELFTEST 0x0004
178 #define PDQ_PRESET_SOFT_RESET 0x0002
179 #define PDQ_PRESET_UPGRADE 0x0001
180 /*
181 * Port Control Register Definitions
182 */
183 #define PDQ_PCTL_CMD_ERROR 0x8000
184 #define PDQ_PCTL_FLASH_BLAST 0x4000
185 #define PDQ_PCTL_HALT 0x2000
186 #define PDQ_PCTL_COPY_DATA 0x1000
187 #define PDQ_PCTL_ERROR_LOG_START 0x0800
188 #define PDQ_PCTL_ERROR_LOG_READ 0x0400
189 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE 0x0200
190 #define PDQ_PCTL_DMA_INIT 0x0100
191 #define PDQ_DMA_INIT_LW_BSWAP_DATA 0x02
192 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL 0x01
193 #define PDQ_PCTL_INIT_START 0x0080
194 #define PDQ_PCTL_CONSUMER_BLOCK 0x0040
195 #define PDQ_PCTL_DMA_UNINIT 0x0020
196 #define PDQ_PCTL_RING_MEMBER 0x0010
197 #define PDQ_PCTL_MLA_READ 0x0008
198 #define PDQ_PCTL_FW_REV_READ 0x0004
199 #define PDQ_PCTL_DEVICE_SPECIFIC 0x0002
200 #define PDQ_PCTL_SUB_CMD 0x0001
201
202 typedef enum {
203 PDQ_SUB_CMD_LINK_UNINIT=1,
204 PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
205 PDQ_SUB_CMD_PDQ_REV_GET=4
206 } pdq_sub_cmd_t;
207
208 typedef enum {
209 PDQ_DMA_BURST_4LW=0,
210 PDQ_DMA_BURST_8LW=1,
211 PDQ_DMA_BURST_16LW=2,
212 PDQ_DMA_BURST_32LW=3
213 } pdq_dma_burst_size_t;
214
215 typedef enum {
216 PDQ_CHIP_REV_A_B_OR_C=0,
217 PDQ_CHIP_REV_D=2,
218 PDQ_CHIP_REV_E=4
219 } pdq_chip_rev_t;
220 /*
221 * Port Status Register Definitions
222 */
223 #define PDQ_PSTS_RCV_DATA_PENDING 0x80000000ul
224 #define PDQ_PSTS_XMT_DATA_PENDING 0x40000000ul
225 #define PDQ_PSTS_HOST_SMT_PENDING 0x20000000ul
226 #define PDQ_PSTS_UNSOL_PENDING 0x10000000ul
227 #define PDQ_PSTS_CMD_RSP_PENDING 0x08000000ul
228 #define PDQ_PSTS_CMD_REQ_PENDING 0x04000000ul
229 #define PDQ_PSTS_TYPE_0_PENDING 0x02000000ul
230 #define PDQ_PSTS_INTR_PENDING 0xFE000000ul
231 #define PDQ_PSTS_ADAPTER_STATE(sts) ((pdq_state_t) (((sts) >> 8) & 0x07))
232 #define PDQ_PSTS_HALT_ID(sts) ((pdq_halt_code_t) ((sts) & 0xFF))
233 /*
234 * Host Interrupt Register Definitions
235 */
236 #define PDQ_HOST_INT_TX_ENABLE 0x80000000ul
237 #define PDQ_HOST_INT_RX_ENABLE 0x40000000ul
238 #define PDQ_HOST_INT_UNSOL_ENABLE 0x20000000ul
239 #define PDQ_HOST_INT_HOST_SMT_ENABLE 0x10000000ul
240 #define PDQ_HOST_INT_CMD_RSP_ENABLE 0x08000000ul
241 #define PDQ_HOST_INT_CMD_RQST_ENABLE 0x04000000ul
242
243 #define PDQ_HOST_INT_1MS 0x80
244 #define PDQ_HOST_INT_20MS 0x40
245 #define PDQ_HOST_INT_CSR_CMD_DONE 0x20
246 #define PDQ_HOST_INT_STATE_CHANGE 0x10
247 #define PDQ_HOST_INT_XMT_DATA_FLUSH 0x08
248 #define PDQ_HOST_INT_NXM 0x04
249 #define PDQ_HOST_INT_PM_PARITY_ERROR 0x02
250 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR 0x01
251 #define PDQ_HOST_INT_FATAL_ERROR 0x07
252
253 typedef enum {
254 PDQH_SELFTEST_TIMEOUT=0,
255 PDQH_HOST_BUS_PARITY_ERROR=1,
256 PDQH_HOST_DIRECTED_HALT=2,
257 PDQH_SOFTWARE_FAULT=3,
258 PDQH_HARDWARE_FAULT=4,
259 PDQH_PC_TRACE_PATH_TEST=5,
260 PDQH_DMA_ERROR=6,
261 PDQH_IMAGE_CRC_ERROR=7,
262 PDQH_ADAPTER_PROCESSOR_ERROR=8,
263 PDQH_MAX=9
264 } pdq_halt_code_t;
265
266 typedef struct {
267 pdq_uint16_t pdqcb_receives;
268 pdq_uint16_t pdqcb_transmits;
269 pdq_uint32_t pdqcb__filler1;
270 pdq_uint32_t pdqcb_host_smt;
271 pdq_uint32_t pdqcb__filler2;
272 pdq_uint32_t pdqcb_unsolicited_event;
273 pdq_uint32_t pdqcb__filler3;
274 pdq_uint32_t pdqcb_command_response;
275 pdq_uint32_t pdqcb__filler4;
276 pdq_uint32_t pdqcb_command_request;
277 pdq_uint32_t pdqcb__filler5[7];
278 } pdq_consumer_block_t;
279
280 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
281 #define PDQ_BITFIELD2(a, b) b, a
282 #define PDQ_BITFIELD3(a, b, c) c, b, a
283 #define PDQ_BITFIELD4(a, b, c, d) d, c, b, a
284 #define PDQ_BITFIELD5(a, b, c, d, e) e, d, c, b, a
285 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
286 l, k, j, i, h, g, f, e, d, c, b, a
287 #else
288 #define PDQ_BITFIELD2(a, b) a, b
289 #define PDQ_BITFIELD3(a, b, c) a, b, c
290 #define PDQ_BITFIELD4(a, b, c, d) a, b, c, d
291 #define PDQ_BITFIELD5(a, b, c, d, e) a, b, c, d, e
292 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
293 a, b, c, d, e, f, g, h, i, j, k, l
294 #endif
295
296 typedef struct {
297 pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
298 rxd_seg_cnt : 4,
299 rxd_seg_len_hi : 9,
300 rxd_seg_len_lo : 2,
301 rxd_sop : 1);
302 pdq_uint32_t rxd_pa_lo;
303 } pdq_rxdesc_t;
304
305 typedef union {
306 pdq_uint32_t rxs_status;
307 pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13,
308 rxs_rcc_ss : 2,
309 rxs_rcc_dd : 2,
310 rxs_rcc_reason : 3,
311 rxs_rcc_badcrc : 1,
312 rxs_rcc_badpdu : 1,
313 rxs_fsb__reserved : 2,
314 rxs_fsb_c : 1,
315 rxs_fsb_a : 1,
316 rxs_fsb_e : 1,
317 rxs_fsc : 3,
318 rxs__reserved : 2);
319 } pdq_rxstatus_t;
320
321 typedef struct {
322 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
323 txd_seg_len : 13,
324 txd_mbz : 1,
325 txd_eop : 1,
326 txd_sop : 1);
327 pdq_uint32_t txd_pa_lo;
328 } pdq_txdesc_t;
329
330 typedef struct {
331 pdq_rxdesc_t pdqdb_receives[256]; /* 2048; 0x0000..0x07FF */
332 pdq_txdesc_t pdqdb_transmits[256]; /* 2048; 0x0800..0x0FFF */
333 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */
334 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */
335 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */
336 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */
337 /*
338 * The rest of the descriptor block is unused.
339 * As such we could use it for other things.
340 */
341 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x1380..0x13BF */
342 void *pdqdb_receive_buffers[256]; /* 1024/2048; 0x13C0..0x17BF 0x13C0..0x1BBF */
343 void *pdqdb_host_smt_buffers[64]; /* 256/ 512; 0x17C0..0x18BF 0x1BC0..0x1DBF */
344 /*
345 * The maximum command size is 512 so as long as thes
346 * command is at least that long all will be fine.
347 */
348 #if defined(__alpha) || defined(__alpha__)
349 pdq_uint32_t pdqdb_command_pool[144];
350 #else
351 pdq_uint32_t pdqdb_command_pool[464];
352 #endif
353 } pdq_descriptor_block_t;
354
355 typedef struct {
356 /*
357 * These value manage the available space in command/response
358 * buffer area.
359 */
360 pdq_physaddr_t ci_pa_bufstart;
361 pdq_uint8_t *ci_bufstart;
362 /*
363 * Bitmask of commands to sent to the PDQ
364 */
365 pdq_uint32_t ci_pending_commands;
366 /*
367 * Variables to maintain the PDQ queues.
368 */
369 pdq_uint32_t ci_command_active;
370 pdq_uint32_t ci_request_producer;
371 pdq_uint32_t ci_response_producer;
372 pdq_uint32_t ci_request_completion;
373 pdq_uint32_t ci_response_completion;
374 } pdq_command_info_t;
375
376 #define PDQ_SIZE_UNSOLICITED_EVENT 512
377 #define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
378
379 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
380
381 typedef struct {
382 pdq_physaddr_t ui_pa_bufstart;
383 pdq_unsolicited_event_t *ui_events;
384
385 pdq_uint32_t ui_free;
386 pdq_uint32_t ui_producer;
387 pdq_uint32_t ui_completion;
388 } pdq_unsolicited_info_t;
389
390 #define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3)
391 #define PDQ_RX_SEGCNT ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE)
392 #define PDQ_DO_TYPE2_PRODUCER(pdq) \
393 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \
394 ((pdq)->pdq_rx_info.rx_producer << 0) \
395 | ((pdq)->pdq_tx_info.tx_producer << 8) \
396 | ((pdq)->pdq_rx_info.rx_completion << 16) \
397 | ((pdq)->pdq_tx_info.tx_completion << 24))
398
399 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \
400 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \
401 ((pdq)->pdq_host_smt_info.rx_producer << 0) \
402 | ((pdq)->pdq_host_smt_info.rx_completion << 8))\
403
404 #define PDQ_ADVANCE(n, a, m) ((n) = ((n) + (a)) & (m))
405
406 typedef struct {
407 void *q_head;
408 void *q_tail;
409 } pdq_databuf_queue_t;
410
411 typedef struct {
412 void *rx_buffers;
413
414 pdq_uint32_t rx_target;
415 pdq_uint32_t rx_free;
416 pdq_uint32_t rx_producer;
417 pdq_uint32_t rx_completion;
418 } pdq_rx_info_t;
419
420 typedef struct {
421 pdq_databuf_queue_t tx_txq;
422 pdq_txdesc_t tx_hdrdesc;
423 pdq_uint8_t tx_descriptor_count[256];
424
425 pdq_uint32_t tx_free;
426 pdq_uint32_t tx_producer;
427 pdq_uint32_t tx_completion;
428 } pdq_tx_info_t;
429
430 struct _pdq_t {
431 pdq_csrs_t pdq_csrs;
432 pdq_pci_csrs_t pdq_pci_csrs;
433 pdq_type_t pdq_type;
434 pdq_chip_rev_t pdq_chip_rev;
435 pdq_lanaddr_t pdq_hwaddr;
436 pdq_fwrev_t pdq_fwrev;
437 pdq_descriptor_block_t *pdq_dbp;
438 volatile pdq_consumer_block_t *pdq_cbp;
439 pdq_uint32_t pdq_flags;
440 #define PDQ_PROMISC 0x0001
441 #define PDQ_ALLMULTI 0x0002
442 #define PDQ_PASS_SMT 0x0004
443 #define PDQ_RUNNING 0x0008
444 #define PDQ_PRINTCHARS 0x0010
445 #define PDQ_TXOK 0x0020
446 const char *pdq_os_name;
447 void *pdq_os_ctx;
448 pdq_uint32_t pdq_unit;
449 pdq_command_info_t pdq_command_info;
450 pdq_unsolicited_info_t pdq_unsolicited_info;
451 pdq_tx_info_t pdq_tx_info;
452 pdq_rx_info_t pdq_rx_info;
453 pdq_rx_info_t pdq_host_smt_info;
454 pdq_uint8_t pdq_tx_hdr[3];
455 };
456
457 typedef enum {
458 PDQC_START=0,
459 PDQC_FILTER_SET=1,
460 PDQC_FILTER_GET=2,
461 PDQC_CHARS_SET=3,
462 PDQC_STATUS_CHARS_GET=4,
463 PDQC_COUNTERS_GET=5,
464 PDQC_COUNTERS_SET=6,
465 PDQC_ADDR_FILTER_SET=7,
466 PDQC_ADDR_FILTER_GET=8,
467 PDQC_ERROR_LOG_CLEAR=9,
468 PDQC_ERROR_LOG_GET=10,
469 PDQC_FDDI_MIB_GET=11,
470 PDQC_DEC_EXT_MIB_GET=12,
471 PDQC_DEV_SPECIFIC_GET=13,
472 PDQC_SNMP_SET=14,
473 PDQC_SMT_MIB_GET=16,
474 PDQC_SMT_MIB_SET=17
475 } pdq_cmd_code_t;
476
477 typedef enum {
478 PDQR_SUCCESS=0,
479 PDQR_FAILURE=1,
480 PDQR_WARNING=2,
481 PDQR_LOOP_MODE_BAD=3,
482 PDQR_ITEM_CODE_BAD=4,
483 PDQR_TVX_BAD=5,
484 PDQR_TREQ_BAD=6,
485 PDQR_RESTRICTED_TOKEN_BAD=7,
486 PDQR_NO_EOL=12,
487 PDQR_FILTER_STATE_BAD=13,
488 PDQR_CMD_TYPE_BAD=14,
489 PDQR_ADAPTER_STATE_BAD=15,
490 PDQR_RING_PURGER_BAD=16,
491 PDQR_LEM_THRESHOLD_BAD=17,
492 PDQR_LOOP_NOT_SUPPORTED=18,
493 PDQR_FLUSH_TIME_BAD=19,
494 PDQR_NOT_YET_IMPLEMENTED=20,
495 PDQR_CONFIG_POLICY_BAD=21,
496 PDQR_STATION_ACTION_BAD=22,
497 PDQR_MAC_ACTION_BAD=23,
498 PDQR_CON_POLICIES_BAD=24,
499 PDQR_MAC_LOOP_TIME_BAD=25,
500 PDQR_TB_MAX_BAD=26,
501 PDQR_LER_CUTOFF_BAD=27,
502 PDQR_LER_ALARM_BAD=28,
503 PDQR_MAC_PATHS_REQ_BAD=29,
504 PDQR_MAC_T_REQ_BAD=30,
505 PDQR_EMAC_RING_PURGER_BAD=31,
506 PDQR_EMAC_RTOKEN_TIMOUT_AD=32,
507 PDQR_NO_SUCH_ENTRY=33,
508 PDQR_T_NOTIFY_BAD=34,
509 PDQR_TR_MAX_EXP_BAD=35,
510 PDQR_FRAME_ERR_THRESHOLD_BAD=36,
511 PDQR_MAX_TREQ_BAD=37,
512 PDQR_FULL_DUPLEX_ENABLE_BAD=38,
513 PDQR_ITEM_INDEX_BAD=39
514 } pdq_response_code_t;
515
516 typedef enum {
517 PDQI_EOL=0,
518 PDQI_T_REQ=1,
519 PDQI_TVX=2,
520 PDQI_RESTRICTED_TOKEN=3,
521 PDQI_LEM_THRESHOLD=4,
522 PDQI_RING_PURGER=5,
523 PDQI_COUNTER_INTERVAL=6,
524 PDQI_IND_GROUP_PROM=7,
525 PDQI_GROUP_PROM=8,
526 PDQI_BROADCAST=9,
527 PDQI_SMT_PROM=10,
528 PDQI_SMT_USER=11,
529 PDQI_RESERVED=12,
530 PDQI_IMPLEMENTOR=13,
531 PDQI_LOOPBACK_MODE=14,
532 PDQI_SMT_CONFIG_POLICY=16,
533 PDQI_SMT_CONNECTION_POLICY=17,
534 PDQI_SMT_T_NOTIFY=18,
535 PDQI_SMT_STATION_ACTION=19,
536 PDQI_MAC_PATHS_REQUESTED=21,
537 PDQI_MAC_ACTION=23,
538 PDQI_PORT_CONNECTION_POLICIES=24,
539 PDQI_PORT_PATHS_REQUESTED=25,
540 PDQI_PORT_MAC_LOOP_TIME=26,
541 PDQI_PORT_TB_MAX=27,
542 PDQI_PORT_LER_CUTOFF=28,
543 PDQI_PORT_LER_ALARM=29,
544 PDQI_PORT_ACTION=30,
545 PDQI_FLUSH_TIME=32,
546 PDQI_SMT_USER_DATA=33,
547 PDQI_SMT_STATUS_REPORT_POLICY=34,
548 PDQI_SMT_TRACE_MAX_EXPIRATION=35,
549 PDQI_MAC_FRAME_ERR_THRESHOLD=36,
550 PDQI_MAC_UNIT_DATA_ENABLE=37,
551 PDQI_PATH_TVX_LOWER_BOUND=38,
552 PDQI_PATH_TMAX_LOWER_BOUND=39,
553 PDQI_PATH_MAX_TREQ=40,
554 PDQI_MAC_TREQ=41,
555 PDQI_EMAC_RING_PURGER=42,
556 PDQI_EMAC_RTOKEN_TIMEOUT=43,
557 PDQI_FULL_DUPLEX_ENABLE=44
558 } pdq_item_code_t;
559
560 enum _pdq_boolean_t {
561 PDQ_FALSE=0,
562 PDQ_TRUE=1
563 };
564
565 typedef enum {
566 PDQ_FILTER_BLOCK=0,
567 PDQ_FILTER_PASS=1
568 } pdq_filter_state_t;
569
570 typedef enum {
571 PDQ_STATION_TYPE_SAS=0,
572 PDQ_STATION_TYPE_DAC=1,
573 PDQ_STATION_TYPE_SAC=2,
574 PDQ_STATION_TYPE_NAC=3,
575 PDQ_STATION_TYPE_DAS=4
576 } pdq_station_type_t;
577
578 typedef enum {
579 PDQ_STATION_STATE_OFF=0,
580 PDQ_STATION_STATE_ON=1,
581 PDQ_STATION_STATE_LOOPBACK=2
582 } pdq_station_state_t;
583
584 typedef enum {
585 PDQ_LINK_STATE_OFF_READY=1,
586 PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2,
587 PDQ_LINK_STATE_ON_RING_INIT=3,
588 PDQ_LINK_STATE_ON_RING_RUN=4,
589 PDQ_LINK_STATE_BROKEN=5
590 } pdq_link_state_t;
591
592 typedef enum {
593 PDQ_DA_TEST_STATE_UNKNOWN=0,
594 PDQ_DA_TEST_STATE_SUCCESS=1,
595 PDQ_DA_TEST_STATE_DUPLICATE=2
596 } pdq_da_test_state_t;
597
598 typedef enum {
599 PDQ_RING_PURGER_STATE_OFF=0,
600 PDQ_RING_PURGER_STATE_CANDIDATE=1,
601 PDQ_RING_PURGER_STATE_NON_PURGER=2,
602 PDQ_RING_PURGER_STATE_PURGER=3
603 } pdq_ring_purger_state_t;
604
605 typedef enum {
606 PDQ_FRAME_STRING_MODE_SA_MATCH=0,
607 PDQ_FRAME_STRING_MODE_FCI_STRIP=1
608 } pdq_frame_strip_mode_t;
609
610 typedef enum {
611 PDQ_RING_ERROR_REASON_NO_ERROR=0,
612 PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5,
613 PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6,
614 PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7,
615 PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8,
616 PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9,
617 PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10,
618 PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11,
619 PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12,
620 PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13,
621 PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14,
622 PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15
623 } pdq_ring_error_reason_t;
624
625 typedef enum {
626 PDQ_STATION_MODE_NORMAL=0,
627 PDQ_STATION_MODE_INTERNAL_LOOPBACK=1
628 } pdq_station_mode_t;
629
630 typedef enum {
631 PDQ_PHY_TYPE_A=0,
632 PDQ_PHY_TYPE_B=1,
633 PDQ_PHY_TYPE_S=2,
634 PDQ_PHY_TYPE_M=3,
635 PDQ_PHY_TYPE_UNKNOWN=4
636 } pdq_phy_type_t;
637
638 typedef enum {
639 PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0,
640 PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1,
641 PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2,
642 PDQ_PMD_TYPE_ANSI_SONET=3,
643 PDQ_PMD_TYPE_LOW_POWER=100,
644 PDQ_PMD_TYPE_THINWIRE=101,
645 PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102,
646 PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103
647 } pdq_pmd_type_t;
648
649 typedef enum {
650 PDQ_PMD_CLASS_ANSI_MULTI_MODE=0,
651 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1,
652 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2,
653 PDQ_PMD_CLASS_SONET=3,
654 PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4,
655 PDQ_PMD_CLASS_TWISTED_PAIR=5,
656 PDQ_PMD_CLASS_UNKNOWN=6,
657 PDQ_PMD_CLASS_UNSPECIFIED=7
658 } pdq_pmd_class_t;
659
660 typedef enum {
661 PDQ_PHY_STATE_INTERNAL_LOOPBACK=0,
662 PDQ_PHY_STATE_BROKEN=1,
663 PDQ_PHY_STATE_OFF_READY=2,
664 PDQ_PHY_STATE_WAITING=3,
665 PDQ_PHY_STATE_STARTING=4,
666 PDQ_PHY_STATE_FAILED=5,
667 PDQ_PHY_STATE_WATCH=6,
668 PDQ_PHY_STATE_INUSE=7
669 } pdq_phy_state_t;
670
671 typedef enum {
672 PDQ_REJECT_REASON_NONE=0,
673 PDQ_REJECT_REASON_LOCAL_LCT=1,
674 PDQ_REJECT_REASON_REMOTE_LCT=2,
675 PDQ_REJECT_REASON_LCT_BOTH_SIDES=3,
676 PDQ_REJECT_REASON_LEM_REJECT=4,
677 PDQ_REJECT_REASON_TOPOLOGY_ERROR=5,
678 PDQ_REJECT_REASON_NOISE_REJECT=6,
679 PDQ_REJECT_REASON_REMOTE_REJECT=7,
680 PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8,
681 PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9,
682 PDQ_REJECT_REASON_STANDBY=10,
683 PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11
684 } pdq_reject_reason_t;
685
686 typedef enum {
687 PDQ_BROKEN_REASON_NONE=0
688 } pdq_broken_reason_t;
689
690 typedef enum {
691 PDQ_RI_REASON_TVX_EXPIRED=0,
692 PDQ_RI_REASON_TRT_EXPIRED=1,
693 PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2,
694 PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3,
695 PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4
696 } pdq_ri_reason_t;
697
698 typedef enum {
699 PDQ_LCT_DIRECTION_LOCAL_LCT=0,
700 PDQ_LCT_DIRECTION_REMOTE_LCT=1,
701 PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2
702 } pdq_lct_direction_t;
703
704 typedef enum {
705 PDQ_PORT_A=0,
706 PDQ_PORT_B=1
707 } pdq_port_type_t;
708
709 typedef struct {
710 pdq_uint8_t station_id_bytes[8];
711 } pdq_station_id_t;
712
713 typedef pdq_uint32_t pdq_fdditimer_t;
714 /*
715 * Command format for Start, Filter_Get, ... commands
716 */
717 typedef struct {
718 pdq_cmd_code_t generic_op;
719 } pdq_cmd_generic_t;
720
721 /*
722 * Response format for Start, Filter_Set, ... commands
723 */
724 typedef struct {
725 pdq_uint32_t generic_reserved;
726 pdq_cmd_code_t generic_op;
727 pdq_response_code_t generic_status;
728 } pdq_response_generic_t;
729
730 /*
731 * Command format for Filter_Set command
732 */
733 typedef struct {
734 pdq_cmd_code_t filter_set_op;
735 struct {
736 pdq_item_code_t item_code;
737 pdq_filter_state_t filter_state;
738 } filter_set_items[7];
739 pdq_item_code_t filter_set_eol_item_code;
740 } pdq_cmd_filter_set_t;
741
742 /*
743 * Response format for Filter_Get command.
744 */
745 typedef struct {
746 pdq_uint32_t filter_get_reserved;
747 pdq_cmd_code_t filter_get_op;
748 pdq_response_code_t filter_get_status;
749 pdq_filter_state_t filter_get_ind_group_prom;
750 pdq_filter_state_t filter_get_group_prom;
751 pdq_filter_state_t filter_get_broadcast_all;
752 pdq_filter_state_t filter_get_smt_prom;
753 pdq_filter_state_t filter_get_smt_user;
754 pdq_filter_state_t filter_get_reserved_all;
755 pdq_filter_state_t filter_get_implementor_all;
756 } pdq_response_filter_get_t;
757
758 #define PDQ_SIZE_RESPONSE_FILTER_GET 0x28
759
760 typedef struct {
761 pdq_cmd_code_t chars_set_op;
762 struct {
763 pdq_item_code_t item_code;
764 pdq_uint32_t item_value;
765 pdq_port_type_t item_port;
766 } chars_set_items[1];
767 pdq_item_code_t chars_set_eol_item_code;
768 } pdq_cmd_chars_set_t;
769
770 typedef struct {
771 pdq_cmd_code_t addr_filter_set_op;
772 pdq_lanaddr_t addr_filter_set_addresses[62];
773 } pdq_cmd_addr_filter_set_t;
774
775 #define PDQ_SIZE_CMD_ADDR_FILTER_SET 0x1F4
776
777 typedef struct {
778 pdq_uint32_t addr_filter_get_reserved;
779 pdq_cmd_code_t addr_filter_get_op;
780 pdq_response_code_t addr_filter_get_status;
781 pdq_lanaddr_t addr_filter_get_addresses[62];
782 } pdq_response_addr_filter_get_t;
783
784 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET 0x1FC
785
786 typedef struct {
787 pdq_uint32_t status_chars_get_reserved;
788 pdq_cmd_code_t status_chars_get_op;
789 pdq_response_code_t status_chars_get_status;
790 struct {
791 /* Station Characteristic Attributes */
792 pdq_station_id_t station_id;
793 pdq_station_type_t station_type;
794 pdq_uint32_t smt_version_id;
795 pdq_uint32_t smt_max_version_id;
796 pdq_uint32_t smt_min_version_id;
797 /* Station Status Attributes */
798 pdq_station_state_t station_state;
799 /* Link Characteristic Attributes */
800 pdq_lanaddr_t link_address;
801 pdq_fdditimer_t t_req;
802 pdq_fdditimer_t tvx;
803 pdq_fdditimer_t restricted_token_timeout;
804 pdq_boolean_t ring_purger_enable;
805 pdq_link_state_t link_state;
806 pdq_fdditimer_t negotiated_trt;
807 pdq_da_test_state_t dup_addr_flag;
808 /* Link Status Attributes */
809 pdq_lanaddr_t upstream_neighbor;
810 pdq_lanaddr_t old_upstream_neighbor;
811 pdq_boolean_t upstream_neighbor_dup_addr_flag;
812 pdq_lanaddr_t downstream_neighbor;
813 pdq_lanaddr_t old_downstream_neighbor;
814 pdq_ring_purger_state_t ring_purger_state;
815 pdq_frame_strip_mode_t frame_strip_mode;
816 pdq_ring_error_reason_t ring_error_reason;
817 pdq_boolean_t loopback;
818 pdq_fdditimer_t ring_latency;
819 pdq_lanaddr_t last_dir_beacon_sa;
820 pdq_lanaddr_t last_dir_beacon_una;
821 /* Phy Characteristic Attributes */
822 pdq_phy_type_t phy_type[2];
823 pdq_pmd_type_t pmd_type[2];
824 pdq_uint32_t lem_threshold[2];
825 /* Phy Status Attributes */
826 pdq_phy_state_t phy_state[2];
827 pdq_phy_type_t neighbor_phy_type[2];
828 pdq_uint32_t link_error_estimate[2];
829 pdq_broken_reason_t broken_reason[2];
830 pdq_reject_reason_t reject_reason[2];
831 /* Miscellaneous */
832 pdq_uint32_t counter_interval;
833 pdq_fwrev_t module_rev;
834 pdq_fwrev_t firmware_rev;
835 pdq_uint32_t mop_device_type;
836 pdq_uint32_t fddi_led[2];
837 pdq_uint32_t flush;
838 } status_chars_get;
839 } pdq_response_status_chars_get_t;
840
841 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET 0xF0
842
843 typedef struct {
844 pdq_uint32_t fddi_mib_get_reserved;
845 pdq_cmd_code_t fddi_mib_get_op;
846 pdq_response_code_t fddi_mib_get_status;
847 struct {
848 /* SMT Objects */
849 pdq_station_id_t smt_station_id;
850 pdq_uint32_t smt_op_version_id;
851 pdq_uint32_t smt_hi_version_id;
852 pdq_uint32_t smt_lo_version_id;
853 pdq_uint32_t smt_mac_ct;
854 pdq_uint32_t smt_non_master_ct;
855 pdq_uint32_t smt_master_ct;
856 pdq_uint32_t smt_paths_available;
857 pdq_uint32_t smt_config_capabilities;
858 pdq_uint32_t smt_config_policy;
859 pdq_uint32_t smt_connection_policy;
860 pdq_uint32_t smt_t_notify;
861 pdq_uint32_t smt_status_reporting;
862 pdq_uint32_t smt_ecm_state;
863 pdq_uint32_t smt_cf_state;
864 pdq_uint32_t smt_hold_state;
865 pdq_uint32_t smt_remote_disconnect_flag;
866 pdq_uint32_t smt_station_action;
867 /* MAC Objects */
868 pdq_uint32_t mac_frame_status_capabilities;
869 pdq_uint32_t mac_t_max_greatest_lower_bound;
870 pdq_uint32_t mac_tvx_greatest_lower_bound;
871 pdq_uint32_t mac_paths_available;
872 pdq_uint32_t mac_current_path;
873 pdq_lanaddr_t mac_upstream_neighbor;
874 pdq_lanaddr_t mac_old_upstream_neighbor;
875 pdq_uint32_t mac_dup_addr_test;
876 pdq_uint32_t mac_paths_requested;
877 pdq_uint32_t mac_downstream_port_type;
878 pdq_lanaddr_t mac_smt_address;
879 pdq_uint32_t mac_t_req;
880 pdq_uint32_t mac_t_neg;
881 pdq_uint32_t mac_t_max;
882 pdq_uint32_t mac_tvx_value;
883 pdq_uint32_t mac_t_min;
884 pdq_uint32_t mac_current_frame_status;
885 pdq_uint32_t mac_frame_error_threshold;
886 pdq_uint32_t mac_frame_error_ratio;
887 pdq_uint32_t mac_rmt_state;
888 pdq_uint32_t mac_da_flag;
889 pdq_uint32_t mac_una_da_flag;
890 pdq_uint32_t mac_frame_condition;
891 pdq_uint32_t mac_chip_set;
892 pdq_uint32_t mac_action;
893 /* Port Objects */
894 pdq_uint32_t port_pc_type[2];
895 pdq_uint32_t port_pc_neighbor[2];
896 pdq_uint32_t port_connection_policies[2];
897 pdq_uint32_t port_remote_mac_indicated[2];
898 pdq_uint32_t port_ce_state[2];
899 pdq_uint32_t port_paths_requested[2];
900 pdq_uint32_t port_mac_placement[2];
901 pdq_uint32_t port_available_paths[2];
902 pdq_uint32_t port_mac_loop_time[2];
903 pdq_uint32_t port_tb_max[2];
904 pdq_uint32_t port_bs_flag[2];
905 pdq_uint32_t port_ler_estimate[2];
906 pdq_uint32_t port_ler_cutoff[2];
907 pdq_uint32_t port_ler_alarm[2];
908 pdq_uint32_t port_connect_state[2];
909 pdq_uint32_t port_pcm_state[2];
910 pdq_uint32_t port_pc_withhold[2];
911 pdq_uint32_t port_ler_condition[2];
912 pdq_uint32_t port_chip_set[2];
913 pdq_uint32_t port_action[2];
914 /* Attachment Objects */
915 pdq_uint32_t attachment_class;
916 pdq_uint32_t attachment_optical_bypass_present;
917 pdq_uint32_t attachment_imax_expiration;
918 pdq_uint32_t attachment_inserted_status;
919 pdq_uint32_t attachment_insert_policy;
920 } fddi_mib_get;
921 } pdq_response_fddi_mib_get_t;
922
923 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET 0x17C
924
925 typedef enum {
926 PDQ_FDX_STATE_IDLE=0,
927 PDQ_FDX_STATE_REQUEST=1,
928 PDQ_FDX_STATE_CONFIRM=2,
929 PDQ_FDX_STATE_OPERATION=3
930 } pdq_fdx_state_t;
931
932 typedef struct {
933 pdq_uint32_t dec_ext_mib_get_reserved;
934 pdq_cmd_code_t dec_ext_mib_get_op;
935 pdq_response_code_t dec_ext_mib_get_response;
936 struct {
937 /* SMT Objects */
938 pdq_uint32_t esmt_station_type;
939 /* MAC Objects */
940 pdq_uint32_t emac_link_state;
941 pdq_uint32_t emac_ring_purger_state;
942 pdq_uint32_t emac_ring_purger_enable;
943 pdq_uint32_t emac_frame_strip_mode;
944 pdq_uint32_t emac_ring_error_reason;
945 pdq_uint32_t emac_upstream_nbr_dupl_address_flag;
946 pdq_uint32_t emac_restricted_token_timeout;
947 /* Port Objects */
948 pdq_uint32_t eport_pmd_type[2];
949 pdq_uint32_t eport_phy_state[2];
950 pdq_uint32_t eport_reject_reason[2];
951 /* Full Duplex Objects */
952 pdq_boolean_t fdx_enable;
953 pdq_boolean_t fdx_operational;
954 pdq_fdx_state_t fdx_state;
955 } dec_ext_mib_get;
956 } pdq_response_dec_ext_mib_get_t;
957
958 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50
959
960 typedef enum {
961 PDQ_CALLER_ID_NONE=0,
962 PDQ_CALLER_ID_SELFTEST=1,
963 PDQ_CALLER_ID_MFG=2,
964 PDQ_CALLER_ID_FIRMWARE=5,
965 PDQ_CALLER_ID_CONSOLE=8
966 } pdq_caller_id_t;
967
968 typedef struct {
969 pdq_uint32_t error_log_get__reserved;
970 pdq_cmd_code_t error_log_get_op;
971 pdq_response_code_t error_log_get_status;
972 /* Error Header */
973 pdq_uint32_t error_log_get_event_status;
974 /* Event Information Block */
975 pdq_caller_id_t error_log_get_caller_id;
976 pdq_uint32_t error_log_get_timestamp[2];
977 pdq_uint32_t error_log_get_write_count;
978 /* Diagnostic Information */
979 pdq_uint32_t error_log_get_fru_implication_mask;
980 pdq_uint32_t error_log_get_test_id;
981 pdq_uint32_t error_log_get_diag_reserved[6];
982 /* Firmware Information */
983 pdq_uint32_t error_log_get_fw_reserved[112];
984 } pdq_response_error_log_get_t;
985
986
987 /*
988 * Definitions for the Unsolicited Event Queue.
989 */
990 typedef enum {
991 PDQ_UNSOLICITED_EVENT=0,
992 PDQ_UNSOLICITED_COUNTERS=1
993 } pdq_event_t;
994
995 typedef enum {
996 PDQ_ENTITY_STATION=0,
997 PDQ_ENTITY_LINK=1,
998 PDQ_ENTITY_PHY_PORT=2
999 } pdq_entity_t;
1000
1001 typedef enum {
1002 PDQ_STATION_EVENT_TRACE_RECEIVED=1
1003 } pdq_station_event_t;
1004
1005 typedef enum {
1006 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */
1007 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1008 } pdq_station_event_argument_t;
1009
1010 typedef enum {
1011 PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0,
1012 PDQ_LINK_EVENT_TRANSMIT_FAILED=1,
1013 PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2,
1014 PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3,
1015 PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4,
1016 PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7,
1017 PDQ_LINK_EVENT_NO_USER_BUFFER=9,
1018 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1019 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1020 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1021 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1022 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1023 PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1024 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1025 PDQ_LINK_EVENT_TRACE_INITIATED=17,
1026 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18
1027 } pdq_link_event_t;
1028
1029 typedef enum {
1030 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */
1031 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1032 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */
1033 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1034 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1035 } pdq_link_event_argument_t;
1036
1037 typedef enum {
1038 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1039 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1040 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2
1041 } pdq_phy_event_t;
1042
1043 typedef enum {
1044 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */
1045 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1046 } pdq_phy_event_arguments;
1047
1048 struct _pdq_unsolicited_event_t {
1049 pdq_uint32_t rvent_reserved;
1050 pdq_event_t event_type;
1051 pdq_entity_t event_entity;
1052 pdq_uint32_t event_index;
1053 union {
1054 pdq_station_event_t station_event;
1055 pdq_link_event_t link_event;
1056 pdq_phy_event_t phy_event;
1057 pdq_uint32_t value;
1058 } event_code;
1059 /*
1060 * The remainder of this event is an argument list.
1061 */
1062 pdq_uint32_t event__filler[123];
1063 };
1064
1065 #endif /* _PDQREG_H */
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