Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pms/RefTisa/sallsdk/api/sa_err.h
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1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * $FreeBSD$ 22 * 23 ********************************************************************************/ 24 /*******************************************************************************/ 25 /*! \file sa_err.h 26 * \brief The file defines the error code constants, defined by LL API 27 * 28 * 29 */ 30 /******************************************************************************/ 31 32 #ifndef __SA_ERR_H__ 33 #define __SA_ERR_H__ 34 35 /************************************************************************************ 36 * * 37 * Error Code Constants defined for LL Layer starts * 38 * * 39 ************************************************************************************/ 40 41 /*********************************************************************************** 42 * SSP/SMP/SATA IO Completion Status values 43 ***********************************************************************************/ 44 45 #define OSSA_IO_SUCCESS 0x00 /**< IO completes successfully */ 46 #define OSSA_IO_ABORTED 0x01 /**< IO aborted */ 47 #define OSSA_IO_OVERFLOW 0x02 /**< IO overflowed (SSP) */ 48 #define OSSA_IO_UNDERFLOW 0x03 /**< IO underflowed (SSP) */ 49 #define OSSA_IO_FAILED 0x04 /**< IO failed */ 50 #define OSSA_IO_ABORT_RESET 0x05 /**< IO abort because of reset */ 51 #define OSSA_IO_NOT_VALID 0x06 /**< IO not valid */ 52 #define OSSA_IO_NO_DEVICE 0x07 /**< IO is for non-existing device */ 53 #define OSSA_IO_ILLEGAL_PARAMETER 0x08 /**< IO is not supported (SSP) */ 54 /* The following two error codes 0x09 and 0x0A are not using */ 55 #define OSSA_IO_LINK_FAILURE 0x09 /**< IO failed because of link failure (SMP) */ 56 #define OSSA_IO_PROG_ERROR 0x0A /**< IO failed because of program error (SMP) */ 57 58 #define OSSA_IO_DIF_IN_ERROR 0x0B /**< IO failed inbound DIF error (SSP) */ 59 #define OSSA_IO_DIF_OUT_ERROR 0x0C /**< IO failed outbound DIF error (SSP) */ 60 #define OSSA_IO_ERROR_HW_TIMEOUT 0x0D /**< SMP request/response failed due to HW timeout (SMP) */ 61 #define OSSA_IO_XFER_ERROR_BREAK 0x0E /**< IO aborted due to BREAK during connection */ 62 #define OSSA_IO_XFER_ERROR_PHY_NOT_READY 0x0F /**< IO aborted due to PHY NOT READY during connection*/ 63 #define OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10 /**< Open connection error */ 64 #define OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11 /**< Open connection error */ 65 #define OSSA_IO_OPEN_CNX_ERROR_BREAK 0x12 /**< Open connection error */ 66 #define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13 /**< Open connection error */ 67 #define OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14 /**< Open connection error */ 68 #define OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15 /**< Open connection error */ 69 #define OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16 /**< Open connection error */ 70 #define OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17 /**< Open connection error */ 71 /* This error code 0x18 is not used on SPCv */ 72 #define OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18 /**< Open connection error */ 73 #define OSSA_IO_XFER_ERROR_NAK_RECEIVED 0x19 /**< IO aborted due to transfer error with data NAK received*/ 74 #define OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A /**< IO aborted due to transfer error with data ACK/NAK timeout*/ 75 #define OSSA_IO_XFER_ERROR_PEER_ABORTED 0x1B 76 #define OSSA_IO_XFER_ERROR_RX_FRAME 0x1C 77 #define OSSA_IO_XFER_ERROR_DMA 0x1D 78 #define OSSA_IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E /**< IO aborted due to CREDIT TIMEOUT during data transfer*/ 79 #define OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F 80 #define OSSA_IO_XFER_ERROR_SATA 0x20 81 82 /* This error code 0x22 is not used on SPCv */ 83 #define OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22 84 #define OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21 85 #define OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23 86 #define OSSA_IO_XFER_OPEN_RETRY_TIMEOUT 0x24 /**< IO OPEN_RETRY_TIMEOUT */ 87 /* This error code 0x25 is not used on SPCv */ 88 #define OSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25 89 #define OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE 0x26 90 #define OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27 91 #define OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28 92 93 #define OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30 94 /* The following error code 0x31 and 0x32 are not using (obsolete) */ 95 #define OSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31 96 #define OSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32 97 98 #define OSSA_IO_XFER_ERROR_OFFSET_MISMATCH 0x34 99 #define OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35 100 #define OSSA_IO_XFER_CMD_FRAME_ISSUED 0x36 101 #define OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE 0x37 102 #define OSSA_IO_PORT_IN_RESET 0x38 103 #define OSSA_IO_DS_NON_OPERATIONAL 0x39 104 #define OSSA_IO_DS_IN_RECOVERY 0x3A 105 #define OSSA_IO_TM_TAG_NOT_FOUND 0x3B 106 #define OSSA_IO_XFER_PIO_SETUP_ERROR 0x3C 107 #define OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D 108 #define OSSA_IO_DS_IN_ERROR 0x3E 109 #define OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F 110 #define OSSA_IO_ABORT_IN_PROGRESS 0x40 111 #define OSSA_IO_ABORT_DELAYED 0x41 112 #define OSSA_IO_INVALID_LENGTH 0x42 113 #define OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43 114 #define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44 115 #define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45 116 #define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46 117 #define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47 118 #define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48 119 #define OSSA_IO_DS_INVALID 0x49 120 121 #define OSSA_IO_XFER_READ_COMPL_ERR 0x0050 122 /* WARNING: the value is not contiguous from here */ 123 #define OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x0052 124 #define OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT 0x0053 125 #define OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR 0x0054 126 #define OSSA_MPI_IO_RQE_BUSY_FULL 0x0055 127 #define OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN 0x0056 /* This status is only for Hitach FW */ 128 #define OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME 0x0057 129 #define OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x0058 130 131 #define OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 132 133 /*encrypt saSetOperator() response status */ 134 #define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005 135 #define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B 136 137 #ifdef SA_TESTBASE_EXTRA 138 /* TestBase */ 139 #define OSSA_IO_HOST_BST_INVALID 0x1005 140 #endif /* SA_TESTBASE_EXTRA */ 141 142 143 #define OSSA_MPI_ERR_OFFLOAD_RESOURCE_UNAVAILABLE 0x1012 144 #define OSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED 0x1013 145 #define OSSA_MPI_ERR_ATAPI_DEVICE_BUSY 0x1024 146 147 /* Specifies the status of the PHY_START command */ 148 #define OSSA_MPI_IO_SUCCESS 0x00000000 /* PhyStart operation completed successfully */ 149 /* Specifies the status of the PHY_STOP command */ 150 #define OSSA_MPI_ERR_DEVICES_ATTACHED 0x00001046 /* All the devices in a port need to be deregistered if the PHY_STOP is for the last phy. */ 151 #define OSSA_MPI_ERR_INVALID_PHY_ID 0x00001061 /* identifier specified in the PHY_START command is invalid i.e out of supported range for this product. */ 152 #define OSSA_MPI_ERR_PHY_ALREADY_STARTED 0x00001063 /* An attempt to start a phy which is already started. */ 153 #define OSSA_MPI_ERR_PHY_NOT_STARTED 0x00001064 /* An attempt to stop a phy which is not started */ 154 #define OSSA_MPI_ERR_PHY_SUBOP_NOT_SUPPORTED 0x00001065 /* An attempt to use a sub operation that is not supported */ 155 156 #define OSSA_MPI_ERR_INVALID_ANALOG_TBL_IDX 0x00001067 /* The Analog Setup Table Index used in the PHY_START command in invalid. */ 157 #define OSSA_MPI_ERR_PHY_PROFILE_PAGE_NOT_SUPPORTED 0x00001068 /* Unsupported profile page code specified in the GET_PHY_PROFILE Command */ 158 #define OSSA_MPI_ERR_PHY_PROFILE_PAGE_NOT_FOUND 0x00001069 /* Unsupported profile page code specified in the GET_PHY_PROFILE Command */ 159 160 #define OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040 161 /* 162 An encryption IO request failed due to DEK Key Tag mismatch. 163 The key tag supplied in the encryption IOMB does not match with the Key Tag in the referenced DEK Entry. 164 */ 165 #define OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041 166 #define OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042 167 /* 168 An encryption I/O request failed 169 because the initial value (IV) in the unwrapped DEK blob didn't match the IV used to unwrap it. 170 */ 171 #define OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043 172 /* An encryption I/O request failed due to an internal RAM ECC or interface error while unwrapping the DEK. */ 173 #define OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044 174 /* An encryption I/O request failed due to an internal RAM ECC or interface error while unwrapping the DEK. */ 175 #define OSSA_IO_XFR_ERROR_INTERNAL_RAM 0x2045 176 /* 177 An encryption I/O request failed 178 because the DEK index specified in the I/O was outside the bounds of thetotal number of entries in the host DEK table. 179 */ 180 #define OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS 0x2046 181 #define OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE 0x2047 182 183 #define OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION 0x2080 184 #define OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE 0x2081 185 186 #define OSSA_MPI_ENC_OPERATOR_AUTH_FAILURE 0x2090 187 #define OSSA_MPI_ENC_OPERATOR_OPERATOR_ALREADY_LOGGED_IN 0x2091 188 #define OSSA_MPI_ENC_OPERATOR_ILLEGAL_PARAMETER 0x2092 189 190 /* define DIF IO response error status code */ 191 #define OSSA_IO_XFR_ERROR_DIF_MISMATCH 0x3000 192 #define OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 193 #define OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 194 #define OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 195 #define OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR 0x3004 196 197 #define OSSA_MPI_ERR_DIF_IS_NOT_ENABLED /* Indicates that saPCIeDiagExecute() is 198 * called with DIF but DIF is not enabled. 199 */ 200 /* define operator management response status and error qualifier code */ 201 #define OPR_MGMT_OP_NOT_SUPPORTED 0x2060 202 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 203 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 204 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 205 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 206 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022 207 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023 208 209 /* When Status is 0x2061 */ 210 #define OPR_MGMT_ERR_QLFR_ILLEGAL_AUTHENTICATIONKEK_INDEX 0x1 211 #define OPR_MGMT_ERR_QLFR_ILLEGAL_OPERATOR 0x2 212 #define OPR_MGMT_ERR_QLFR_ILLEGAL_KEK_FORMAT 0x3 213 #define OPR_MGMT_ERR_QLFR_WRONG_ROLE 0x4 214 215 /* When status is 0x2090 */ 216 /* invalid certificate: the certificate can not be unwrapped successfully by existing operators's KEKs */ 217 #define OPR_SET_ERR_QLFR_INVALID_CERT 0x01 218 /* role mismatch: the role from the certificate doesn't match the one inside the controller. */ 219 #define OPR_SET_ERR_QLFR_ROLE_MISMATCH 0x02 220 /* ID mismatch: the ID string from the certificate doesn't match the one inside the controller. */ 221 #define OPR_SET_ERR_QLFR_ID_MISMATCH 0x03 222 /* When status is 0x2092 */ 223 /* invalid OPRIDX */ 224 #define OPR_SET_ERR_QLFR_INVALID_OPRIDX 0x04 225 /* invalid access type */ 226 #define OPR_SET_ERR_QLFR_INVALID_ACCESS_TYPE 0x05 227 228 /* WARNING: This error code must always be the last number. 229 * If you add error code, modify this code also 230 * It is used as an index 231 */ 232 233 /* SAS Reconfiguration error */ 234 #define OSSA_CONTROLLER_NOT_IDLE 0x1 235 #define OSSA_INVALID_CONFIG_PARAM 0x2 236 237 238 /************************************************************************************ 239 * * 240 * Constants defined for OS Layer ends * 241 * * 242 ************************************************************************************/ 243 244 #endif /*__SA_ERR_H__ */
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