fxr.watson.org: sys/dev/pms/RefTisa/sallsdk/spc/saint.c

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sys/dev/pms/RefTisa/sallsdk/spc/saint.c

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1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 21 ********************************************************************************/ 22 /*******************************************************************************/ 23 /*! \file saint.c 24 * \brief The file implements the functions to handle/enable/disable interrupt 25 * 26 */ 27 /*******************************************************************************/ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 #include <dev/pms/config.h> 31 32 #include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 33 #define SA_CLEAR_ODCR_IN_INTERRUPT 34 35 //#define SA_TEST_FW_SPURIOUS_INT 36 37 #ifdef SA_TEST_FW_SPURIOUS_INT 38 bit32 gOurIntCount = 0; 39 bit32 gSpuriousIntCount = 0; 40 bit32 gSpuriousInt[64]= 41 { 42 0,0,0,0,0,0,0,0, 43 0,0,0,0,0,0,0,0, 44 0,0,0,0,0,0,0,0, 45 0,0,0,0,0,0,0,0, 46 0,0,0,0,0,0,0,0, 47 0,0,0,0,0,0,0,0, 48 0,0,0,0,0,0,0,0, 49 0,0,0,0,0,0,0,0 50 }; 51 bit32 gSpuriousInt1[64]= 52 { 53 0,0,0,0,0,0,0,0, 54 0,0,0,0,0,0,0,0, 55 0,0,0,0,0,0,0,0, 56 0,0,0,0,0,0,0,0, 57 0,0,0,0,0,0,0,0, 58 0,0,0,0,0,0,0,0, 59 0,0,0,0,0,0,0,0, 60 0,0,0,0,0,0,0,0 61 }; 62 #endif /* SA_TEST_FW_SPURIOUS_INT */ 63 64 #ifdef SA_ENABLE_TRACE_FUNCTIONS 65 #ifdef siTraceFileID 66 #undef siTraceFileID 67 #endif /* siTraceFileID */ 68 #define siTraceFileID 'G' 69 #endif /* SA_ENABLE_TRACE_FUNCTIONS */ 70 71 LOCAL FORCEINLINE bit32 siProcessOBMsg( 72 agsaRoot_t *agRoot, 73 bit32 count, 74 bit32 queueNum 75 ); 76 77 LOCAL bit32 siFatalInterruptHandler( 78 agsaRoot_t *agRoot, 79 bit32 interruptVectorIndex 80 ) 81 { 82 agsaLLRoot_t *saRoot = agNULL; 83 agsaFatalErrorInfo_t fatal_error; 84 bit32 value; 85 bit32 ret = AGSA_RC_FAILURE; 86 bit32 Sendfatal = agTRUE; 87 88 SA_ASSERT((agNULL != agRoot), ""); 89 if (agRoot == agNULL) 90 { 91 SA_DBG1(("siFatalInterruptHandler: agRoot == agNULL\n")); 92 return AGSA_RC_FAILURE; 93 } 94 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 95 SA_ASSERT((agNULL != saRoot), ""); 96 if (saRoot == agNULL) 97 { 98 SA_DBG1(("siFatalInterruptHandler: saRoot == agNULL\n")); 99 return AGSA_RC_FAILURE; 100 } 101 102 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 103 if (saRoot->ResetFailed) 104 { 105 SA_DBG1(("siFatalInterruptHandler: ResetFailed\n")); 106 ossaDisableInterrupts(agRoot, interruptVectorIndex); 107 return AGSA_RC_FAILURE; 108 } 109 110 if(SCRATCH_PAD1_V_ERROR_STATE( value ) ) 111 { 112 si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 113 /* read detail fatal errors */ 114 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 115 fatal_error.errorInfo0 = value; 116 SA_DBG1(("siFatalInterruptHandler: ScratchPad0 AAP error 0x%x code 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE( value ), value)); 117 118 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 119 fatal_error.errorInfo1 = value; 120 /* AAP error state */ 121 SA_DBG1(("siFatalInterruptHandler: AAP error state and error code 0x%x\n", value)); 122 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 123 fatal_error.errorInfo2 = value; 124 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2 0x%08x\n", fatal_error.errorInfo2 )); 125 126 #if defined(SALLSDK_DEBUG) 127 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) 128 { 129 SA_DBG1(("siFatalInterruptHandler:SCRATCH_PAD1_V_ERROR_STATE SCRATCH_PAD2_FW_ILA_ERR 0x%08x\n", SCRATCH_PAD2_FW_ILA_ERR)); 130 } 131 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) 132 { 133 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FLM_ERR 0x%08x\n", SCRATCH_PAD2_FW_FLM_ERR)); 134 } 135 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) 136 { 137 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FW_ASRT_ERR 0x%08x\n", SCRATCH_PAD2_FW_FW_ASRT_ERR)); 138 } 139 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) 140 { 141 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_WDG_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_WDG_ERR)); 142 } 143 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) 144 { 145 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x%08x\n", SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR)); 146 } 147 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) 148 { 149 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_UNDTMN_ERR 0x%08x\n",SCRATCH_PAD2_FW_UNDTMN_ERR )); 150 } 151 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) 152 { 153 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_FATAL_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_FATAL_ERR)); 154 } 155 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR ) 156 { 157 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x%08x\n", value)); 158 } 159 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR ) 160 { 161 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x%08x\n", value)); 162 } 163 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR ) 164 { 165 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x%08x\n", value)); 166 } 167 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) ==SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR ) 168 { 169 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x%08x\n", value)); 170 } 171 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR ) 172 { 173 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x%08x\n", value)); 174 } 175 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR ) 176 { 177 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x%08x\n", value)); 178 } 179 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR ) 180 { 181 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x%08x\n", value)); 182 } 183 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR ) 184 { 185 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x%08x\n", value)); 186 } 187 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR ) 188 { 189 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x%08x\n", value)); 190 } 191 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR ) 192 { 193 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x%08x\n", value)); 194 } 195 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR ) 196 { 197 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x%08x\n", value)); 198 } 199 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR ) 200 { 201 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x%08x\n", value)); 202 } 203 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) 204 { 205 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x%08x\n", value)); 206 } 207 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR ) 208 { 209 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x%08x\n", value)); 210 } 211 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED ) 212 { 213 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0x%08x\n", value)); 214 } 215 #endif /* SALLSDK_DEBUG */ 216 217 if( fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_NON_FATAL_ERR && 218 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) && 219 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) && 220 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) && 221 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) && 222 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) && 223 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) && 224 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR) && 225 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR) && 226 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR) && 227 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR) && 228 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR) && 229 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR) && 230 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR) && 231 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR) && 232 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR) && 233 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR) && 234 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR) && 235 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) && 236 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR) && 237 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED) && 238 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) ) 239 { 240 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x%08x\n", value)); 241 Sendfatal = agFALSE; 242 } 243 244 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 245 SA_DBG1(("siFatalInterruptHandler: ScratchPad3 IOP error code 0x%08x\n", value)); 246 fatal_error.errorInfo3 = value; 247 248 if (agNULL != saRoot) 249 { 250 fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 251 fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 252 fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 253 fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 254 fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 255 fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 256 } 257 else 258 { 259 fatal_error.regDumpBusBaseNum0 = 0; 260 fatal_error.regDumpOffset0 = 0; 261 fatal_error.regDumpLen0 = 0; 262 fatal_error.regDumpBusBaseNum1 = 0; 263 fatal_error.regDumpOffset1 = 0; 264 fatal_error.regDumpLen1 = 0; 265 } 266 /* Call Back with error */ 267 SA_DBG1(("siFatalInterruptHandler: Sendfatal %x HostR0 0x%x\n",Sendfatal ,ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ) )); 268 SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 269 ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_2_Register), 270 ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_3_Register) )); 271 272 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); 273 ret = AGSA_RC_SUCCESS; 274 } 275 else 276 { 277 bit32 host_reg0; 278 host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); 279 if( host_reg0 == 0x2) 280 { 281 Sendfatal = agFALSE; 282 283 SA_DBG1(("siFatalInterruptHandler: Non fatal ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); 284 SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 285 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 286 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 287 SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 288 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 289 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 290 291 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); 292 ret = AGSA_RC_SUCCESS; 293 } 294 else if( host_reg0 == HDA_AES_DIF_FUNC) 295 { 296 SA_DBG1(("siFatalInterruptHandler: HDA_AES_DIF_FUNC 0x%x\n", 297 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register))); 298 Sendfatal = agFALSE; 299 ret = AGSA_RC_SUCCESS; 300 } 301 else 302 { 303 SA_DBG1(("siFatalInterruptHandler: No error detected ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); 304 SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 305 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 306 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 307 SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 308 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 309 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 310 311 SA_DBG1(("siFatalInterruptHandler: Doorbell_Set %08X U %08X\n", 312 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 313 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 314 SA_DBG1(("siFatalInterruptHandler: Doorbell_Mask %08X U %08X\n", 315 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 316 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 317 318 ret = AGSA_RC_FAILURE; 319 } 320 } 321 return ret; 322 323 } 324 325 GLOBAL bit32 saFatalInterruptHandler( 326 agsaRoot_t *agRoot, 327 bit32 interruptVectorIndex 328 ) 329 { 330 agsaLLRoot_t *saRoot = agNULL; 331 bit32 ret = AGSA_RC_FAILURE; 332 333 /* sanity check */ 334 SA_ASSERT((agNULL != agRoot), ""); 335 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 336 SA_ASSERT((agNULL != saRoot), ""); 337 338 if (saRoot->ResetFailed) 339 { 340 SA_DBG1(("saFatalInterruptHandler: ResetFailed\n")); 341 ossaDisableInterrupts(agRoot, interruptVectorIndex); 342 return AGSA_RC_FAILURE; 343 } 344 if (saRoot->swConfig.fatalErrorInterruptEnable != 1) 345 { 346 SA_DBG1(("saFatalInterruptHandler: fatalErrorInterrtupt is NOT enabled\n")); 347 ossaDisableInterrupts(agRoot, interruptVectorIndex); 348 return AGSA_RC_FAILURE; 349 } 350 351 if (saRoot->swConfig.fatalErrorInterruptVector != interruptVectorIndex) 352 { 353 SA_DBG1(("saFatalInterruptHandler: interruptVectorIndex does not match 0x%x 0x%x\n", 354 saRoot->swConfig.fatalErrorInterruptVector, interruptVectorIndex)); 355 SA_DBG1(("saFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 356 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 357 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 358 SA_DBG1(("saFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 359 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 360 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 361 ossaDisableInterrupts(agRoot, interruptVectorIndex); 362 return AGSA_RC_FAILURE; 363 } 364 365 ret = siFatalInterruptHandler(agRoot,interruptVectorIndex); 366 367 368 ossaDisableInterrupts(agRoot, interruptVectorIndex); 369 370 return ret; 371 } 372 /******************************************************************************/ 373 /*! \brief Function to process the interrupts 374 * 375 * The saInterruptHandler() function is called after an interrupts has 376 * been received 377 * This function disables interrupts 378 * 379 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 380 * instance of SAS/SATA hardware 381 * \param interruptVectorIndex message that caused MSI message 382 * 383 * \return TRUE if we caused interrupt 384 * 385 */ 386 /*******************************************************************************/ 387 FORCEINLINE bit32 388 saInterruptHandler( 389 agsaRoot_t *agRoot, 390 bit32 interruptVectorIndex 391 ) 392 { 393 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 394 bit32 ToBeProcessedCount = 0; 395 bit32 our_int = 0; 396 #ifdef SA_TEST_FW_SPURIOUS_INT 397 bit8 i; 398 #endif/* SA_TEST_FW_SPURIOUS_INT */ 399 400 if( agNULL == saRoot ) 401 { 402 /* Can be called before initialize is completed in a shared 403 interrupt environment like windows 2003 404 */ 405 return(ToBeProcessedCount); 406 } 407 408 if( (our_int = saRoot->OurInterrupt(agRoot,interruptVectorIndex)) == FALSE ) 409 { 410 #ifdef SA_TEST_FW_SPURIOUS_INT 411 gSpuriousIntCount++; 412 smTrace(hpDBG_REGISTERS,"S1",gSpuriousIntCount); 413 /* TP:S1 gSpuriousIntCount */ 414 #endif /* SA_TEST_FW_SPURIOUS_INT */ 415 return(ToBeProcessedCount); 416 } 417 418 smTraceFuncEnter(hpDBG_TICK_INT, "5q"); 419 420 smTrace(hpDBG_TICK_INT,"VI",interruptVectorIndex); 421 /* TP:Vi interrupt VectorIndex */ 422 423 if ( agFALSE == saRoot->sysIntsActive ) 424 { 425 // SA_ASSERT(0, "saInterruptHandler sysIntsActive not set"); 426 427 #ifdef SA_PRINTOUT_IN_WINDBG 428 #ifndef DBG 429 DbgPrint("saInterruptHandler: sysIntsActive not set Doorbell_Mask_Set %08X U %08X\n", 430 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 431 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU) ); 432 #endif /* DBG */ 433 #endif /* SA_PRINTOUT_IN_WINDBG */ 434 435 436 SA_DBG1(("saInterruptHandler: Doorbell_Mask_Set %08X U %08X\n", 437 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 438 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); 439 ossaDisableInterrupts(agRoot, interruptVectorIndex); 440 return(ToBeProcessedCount); 441 442 } 443 444 /* Allow replacement of disable interrupt */ 445 ossaDisableInterrupts(agRoot, interruptVectorIndex); 446 447 448 #ifdef SA_TEST_FW_SPURIOUS_INT 449 450 /* count for my interrupt */ 451 gOurIntCount++; 452 453 smTrace(hpDBG_REGISTERS,"S4",gOurIntCount); 454 /* TP:S4 gOurIntCount */ 455 #endif /* SA_TEST_FW_SPURIOUS_INT */ 456 457 smTraceFuncExit(hpDBG_TICK_INT, 'a', "5q"); 458 return(TRUE); 459 460 } 461 462 /******************************************************************************/ 463 /*! \brief Function to disable MSIX interrupts 464 * 465 * siDisableMSIXInterrupts disables interrupts 466 * called thru macro ossaDisableInterrupts 467 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 468 * instance of SAS/SATA hardware 469 * \param interruptVectorIndex - vector index for message 470 * 471 */ 472 /*******************************************************************************/ 473 GLOBAL void siDisableMSIXInterrupts( 474 agsaRoot_t *agRoot, 475 bit32 interruptVectorIndex 476 ) 477 { 478 bit32 msi_index; 479 #ifndef SA_CLEAR_ODCR_IN_INTERRUPT 480 bit32 value; 481 #endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 482 msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; 483 msi_index += MSIX_TABLE_BASE; 484 ossaHwRegWrite(agRoot,msi_index , MSIX_INTERRUPT_DISABLE); 485 ossaHwRegRead(agRoot, msi_index); /* Dummy read */ 486 #ifndef SA_CLEAR_ODCR_IN_INTERRUPT 487 value = (1 << interruptVectorIndex); 488 ossaHwRegWrite(agRoot, MSGU_ODCR, value); 489 #endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 490 } 491 492 /******************************************************************************/ 493 /*! \brief Function to disable MSIX V interrupts 494 * 495 * siDisableMSIXInterrupts disables interrupts 496 * called thru macro ossaDisableInterrupts 497 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 498 * instance of SAS/SATA hardware 499 * \param interruptVectorIndex - vector index for message 500 * 501 */ 502 /*******************************************************************************/ 503 void siDisableMSIX_V_Interrupts( 504 agsaRoot_t *agRoot, 505 bit32 interruptVectorIndex 506 ) 507 { 508 bit64 mask; 509 agsabit32bit64 u64; 510 mask =( (bit64)1 << interruptVectorIndex); 511 u64.B64 = mask; 512 if(smIS64bInt(agRoot)) 513 { 514 SA_DBG4(("siDisableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 515 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[1]); 516 } 517 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, u64.S32[0]); 518 519 } 520 /******************************************************************************/ 521 /*! \brief Function to disable MSI interrupts 522 * 523 * siDisableMSIInterrupts disables interrupts 524 * called thru macro ossaDisableInterrupts 525 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 526 * instance of SAS/SATA hardware 527 * \param interruptVectorIndex - vector index for message 528 * 529 */ 530 /*******************************************************************************/ 531 GLOBAL void siDisableMSIInterrupts( 532 agsaRoot_t *agRoot, 533 bit32 interruptVectorIndex 534 ) 535 { 536 bit32 ODMRValue; 537 bit32 mask; 538 mask = 1 << interruptVectorIndex; 539 540 /*Must be protected for interuption */ 541 ODMRValue = ossaHwRegRead(agRoot, MSGU_ODMR); 542 ODMRValue |= mask; 543 544 ossaHwRegWrite(agRoot, MSGU_ODMR, ODMRValue); 545 ossaHwRegWrite(agRoot, MSGU_ODCR, mask); 546 } 547 548 /******************************************************************************/ 549 /*! \brief Function to disable MSI V interrupts 550 * 551 * siDisableMSIInterrupts disables interrupts 552 * called thru macro ossaDisableInterrupts 553 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 554 * instance of SAS/SATA hardware 555 * \param interruptVectorIndex - vector index for message 556 * 557 */ 558 /*******************************************************************************/ 559 GLOBAL void siDisableMSI_V_Interrupts( 560 agsaRoot_t *agRoot, 561 bit32 interruptVectorIndex 562 ) 563 { 564 SA_ASSERT(0, "Should not be called"); 565 SA_DBG4(("siDisableMSI_V_Interrupts:\n")); 566 } 567 568 /******************************************************************************/ 569 /*! \brief Function to process Legacy interrupts 570 * 571 * siDisableLegacyInterrupts disables interrupts 572 * called thru macro ossaDisableInterrupts 573 * 574 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 575 * instance of SAS/SATA hardware 576 * \param interruptVectorIndex not used in legacy case 577 * 578 */ 579 /*******************************************************************************/ 580 GLOBAL void siDisableLegacyInterrupts( 581 agsaRoot_t *agRoot, 582 bit32 interruptVectorIndex 583 ) 584 { 585 ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_MASK_ALL); 586 #ifndef SA_CLEAR_ODCR_IN_INTERRUPT 587 ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 588 #endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 589 } 590 591 /******************************************************************************/ 592 /*! \brief Function to process Legacy V interrupts 593 * 594 * siDisableLegacyInterrupts disables interrupts 595 * called thru macro ossaDisableInterrupts 596 * 597 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 598 * instance of SAS/SATA hardware 599 * \param interruptVectorIndex not used in legacy case 600 * 601 */ 602 /*******************************************************************************/ 603 GLOBAL void siDisableLegacy_V_Interrupts( 604 agsaRoot_t *agRoot, 605 bit32 interruptVectorIndex 606 ) 607 { 608 609 bit64 mask; 610 agsabit32bit64 u64; 611 mask =( (bit64)1 << interruptVectorIndex); 612 u64.B64 = mask; 613 614 SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 615 SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 616 if(smIS64bInt(agRoot)) 617 { 618 SA_DBG4(("siDisableLegacy_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 619 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register,u64.S32[1] ); 620 } 621 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[0]); 622 623 } 624 /******************************************************************************/ 625 /*! \brief Function to process MSIX interrupts 626 * 627 * siOurMSIXInterrupt checks if we generated interrupt 628 * called thru function pointer saRoot->OurInterrupt 629 * 630 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 631 * instance of SAS/SATA hardware 632 * \return always true 633 */ 634 /*******************************************************************************/ 635 GLOBAL bit32 siOurMSIXInterrupt( 636 agsaRoot_t *agRoot, 637 bit32 interruptVectorIndex 638 ) 639 { 640 return(TRUE); 641 } 642 643 /******************************************************************************/ 644 /*! \brief Function to process MSIX V interrupts 645 * 646 * siOurMSIXInterrupt checks if we generated interrupt 647 * called thru function pointer saRoot->OurInterrupt 648 * 649 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 650 * instance of SAS/SATA hardware 651 * \return always true 652 */ 653 /*******************************************************************************/ 654 GLOBAL bit32 siOurMSIX_V_Interrupt( 655 agsaRoot_t *agRoot, 656 bit32 interruptVectorIndex 657 ) 658 { 659 return(TRUE); 660 } 661 /******************************************************************************/ 662 /*! \brief Function to process MSI interrupts 663 * 664 * siOurMSIInterrupt checks if we generated interrupt 665 * called thru function pointer saRoot->OurInterrupt 666 * 667 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 668 * instance of SAS/SATA hardware 669 * \return always true 670 */ 671 /*******************************************************************************/ 672 bit32 siOurMSIInterrupt( 673 agsaRoot_t *agRoot, 674 bit32 interruptVectorIndex 675 ) 676 { 677 return(TRUE); 678 } 679 680 /******************************************************************************/ 681 /*! \brief Function to process MSI V interrupts 682 * 683 * siOurMSIInterrupt checks if we generated interrupt 684 * called thru function pointer saRoot->OurInterrupt 685 * 686 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 687 * instance of SAS/SATA hardware 688 * \return always true 689 */ 690 /*******************************************************************************/ 691 bit32 siOurMSI_V_Interrupt( 692 agsaRoot_t *agRoot, 693 bit32 interruptVectorIndex 694 ) 695 { 696 SA_DBG4((":siOurMSI_V_Interrupt\n")); 697 return(TRUE); 698 } 699 700 /******************************************************************************/ 701 /*! \brief Function to process Legacy interrupts 702 * 703 * siOurLegacyInterrupt checks if we generated interrupt 704 * called thru function pointer saRoot->OurInterrupt 705 * 706 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 707 * instance of SAS/SATA hardware 708 * \return true if we claim interrupt 709 */ 710 /*******************************************************************************/ 711 bit32 siOurLegacyInterrupt( 712 agsaRoot_t *agRoot, 713 bit32 interruptVectorIndex 714 ) 715 { 716 bit32 Int_masked; 717 bit32 Int_active; 718 Int_masked = MSGU_READ_ODMR; 719 Int_active = MSGU_READ_ODR; 720 721 if(Int_masked & 1 ) 722 { 723 return(FALSE); 724 } 725 if(Int_active & 1 ) 726 { 727 728 return(TRUE); 729 } 730 return(FALSE); 731 } 732 733 /******************************************************************************/ 734 /*! \brief Function to process Legacy V interrupts 735 * 736 * siOurLegacyInterrupt checks if we generated interrupt 737 * called thru function pointer saRoot->OurInterrupt 738 * 739 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 740 * instance of SAS/SATA hardware 741 * \return true if we claim interrupt 742 */ 743 /*******************************************************************************/ 744 bit32 siOurLegacy_V_Interrupt( 745 agsaRoot_t *agRoot, 746 bit32 interruptVectorIndex 747 ) 748 { 749 bit32 Int_active; 750 Int_active = siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register ); 751 752 return(Int_active ? TRUE : FALSE); 753 } 754 755 756 /******************************************************************************/ 757 /*! \brief Function to process the cause of interrupt 758 * 759 * The saDelayedInterruptHandler() function is called after an interrupt messages has 760 * been received it may be called by a deferred procedure call 761 * 762 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 763 * instance of SAS/SATA hardware 764 * \param interruptVectorIndex - vector index for message 765 * \param count Number of completion queue entries to consume 766 * 767 * \return number of messages processed 768 * 769 */ 770 /*******************************************************************************/ 771 FORCEINLINE bit32 772 saDelayedInterruptHandler( 773 agsaRoot_t *agRoot, 774 bit32 interruptVectorIndex, 775 bit32 count 776 ) 777 { 778 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 779 bit32 processedMsgCount = 0; 780 bit32 pad1 = 0; 781 bit32 host_reg0 = 0; 782 #if defined(SALLSDK_DEBUG) 783 bit32 host_reg1 = 0; 784 #endif 785 bit8 i = 0; 786 787 OSSA_OUT_ENTER(agRoot); 788 789 smTraceFuncEnter(hpDBG_VERY_LOUD,"5p"); 790 791 smTrace(hpDBG_VERY_LOUD,"Vd",interruptVectorIndex); 792 /* TP:Vd delayed VectorIndex */ 793 smTrace(hpDBG_VERY_LOUD,"Vc",count); 794 /* TP:Vc IOMB count*/ 795 796 if( saRoot->swConfig.fatalErrorInterruptEnable && 797 saRoot->swConfig.fatalErrorInterruptVector == interruptVectorIndex ) 798 { 799 pad1 = siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 800 host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); 801 802 803 if(saRoot->swConfig.hostDirectAccessMode & 2 ) 804 { 805 if( host_reg0 == HDA_AES_DIF_FUNC) 806 { 807 host_reg0 = 0; 808 } 809 } 810 811 812 #if defined(SALLSDK_DEBUG) 813 host_reg1 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_1_Register ); 814 #endif 815 if( (SCRATCH_PAD1_V_ERROR_STATE( pad1 ) != 0 ) && host_reg0 ) 816 { 817 818 SA_DBG1(("saDelayedInterruptHandler: vi %d Error %08X\n",interruptVectorIndex, SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); 819 SA_DBG1(("saDelayedInterruptHandler: Sp 1 %08X Hr0 %08X Hr1 %08X\n",pad1,host_reg0,host_reg1 )); 820 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); 821 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ILA_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ILA_ERROR_STATE( pad1 ))); 822 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_RAAE_ERROR_STATE %08X\n", SCRATCH_PAD1_V_RAAE_ERROR_STATE( pad1 ))); 823 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP0_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP0_ERROR_STATE( pad1 ))); 824 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP1_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP1_ERROR_STATE( pad1 ))); 825 826 siFatalInterruptHandler( agRoot, interruptVectorIndex ); 827 ossaDisableInterrupts(agRoot, interruptVectorIndex); 828 829 } 830 else 831 { 832 SA_DBG2(("saDelayedInterruptHandler: Fatal Check VI %d SCRATCH_PAD1 %08X host_reg0 %08X host_reg1 %08X\n",interruptVectorIndex, pad1,host_reg0,host_reg1)); 833 SA_DBG2(("saDelayedInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 834 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 835 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 836 SA_DBG2(("saDelayedInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 837 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 838 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 839 840 SA_DBG2(("saDelayedInterruptHandler: Doorbell_Set %08X U %08X\n", 841 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 842 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 843 SA_DBG2(("saDelayedInterruptHandler: Doorbell_Mask %08X U %08X\n", 844 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 845 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 846 } 847 848 } 849 850 851 #ifdef SA_LNX_PERF_MODE 852 return siProcessOBMsg(agRoot, count, interruptVectorIndex); 853 #endif 854 855 /* check all the configuration outbound queues within a vector bitmap */ 856 SA_ASSERT((saRoot->QueueConfig.numOutboundQueues < 65), "numOutboundQueue"); 857 858 for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 859 { 860 /* process IOMB in the outbound queue 0 to 31 if bit set in the vector bitmap */ 861 if (i < OQ_NUM_32) 862 { 863 if (saRoot->interruptVecIndexBitMap[interruptVectorIndex] & (1 << i)) 864 { 865 processedMsgCount += siProcessOBMsg(agRoot, count, i); 866 } 867 else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) 868 { 869 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 870 processedMsgCount += siProcessOBMsg(agRoot, count, i); 871 } 872 #ifdef SA_FW_TEST_INTERRUPT_REASSERT 873 else if (saRoot->CheckAll) 874 { 875 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 876 processedMsgCount += siProcessOBMsg(agRoot, count, i); 877 } 878 #endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 879 880 } 881 else 882 { 883 /* process IOMB in the outbound queue 32 to 63 if bit set in the vector bitmap */ 884 if (saRoot->interruptVecIndexBitMap1[interruptVectorIndex] & (1 << (i - OQ_NUM_32))) 885 { 886 processedMsgCount += siProcessOBMsg(agRoot, count, i); 887 } 888 /* check interruptEnable bit for polling mode of OQ */ 889 /* the following code can be removed, we do not care about the bit */ 890 else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) 891 { 892 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 893 processedMsgCount += siProcessOBMsg(agRoot, count, i); 894 } 895 #ifdef SA_FW_TEST_INTERRUPT_REASSERT 896 else if (saRoot->CheckAll) 897 { 898 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 899 processedMsgCount += siProcessOBMsg(agRoot, count, i); 900 } 901 #endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 902 } 903 } 904 905 #ifdef SA_FW_TEST_INTERRUPT_REASSERT 906 saRoot->CheckAll = 0; 907 #endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 908 909 #ifndef SA_RENABLE_IN_OSLAYER 910 if ( agTRUE == saRoot->sysIntsActive ) 911 { 912 /* Allow replacement of enable interrupt */ 913 ossaReenableInterrupts(agRoot, interruptVectorIndex); 914 } 915 #endif /* SA_RENABLE_IN_OSLAYER */ 916 917 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5p"); 918 919 OSSA_OUT_LEAVE(agRoot); 920 return processedMsgCount; 921 } 922 923 /******************************************************************************/ 924 /*! \brief Function to reenable MSIX interrupts 925 * 926 * siReenableMSIXInterrupts reenableinterrupts 927 * called thru macro ossaReenableInterrupts 928 * 929 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 930 * instance of SAS/SATA hardware 931 * \param interruptVectorIndex - vector index for message 932 * 933 */ 934 /*******************************************************************************/ 935 void siReenableMSIXInterrupts( 936 agsaRoot_t *agRoot, 937 bit32 interruptVectorIndex 938 ) 939 { 940 bit32 msi_index; 941 #ifdef SA_CLEAR_ODCR_IN_INTERRUPT 942 bit32 value; 943 #endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 944 msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; 945 msi_index += MSIX_TABLE_BASE; 946 ossaHwRegWriteExt(agRoot, PCIBAR0,msi_index, MSIX_INTERRUPT_ENABLE); 947 948 SA_DBG4(("siReenableMSIXInterrupts:interruptVectorIndex %d\n",interruptVectorIndex)); 949 950 #ifdef SA_CLEAR_ODCR_IN_INTERRUPT 951 value = (1 << interruptVectorIndex); 952 siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, value); 953 #endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 954 } 955 /******************************************************************************/ 956 /*! \brief Function to reenable MSIX interrupts 957 * 958 * siReenableMSIXInterrupts reenableinterrupts 959 * called thru macro ossaReenableInterrupts 960 * 961 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 962 * instance of SAS/SATA hardware 963 * \param interruptVectorIndex - vector index for message 964 * 965 */ 966 /*******************************************************************************/ 967 void siReenableMSIX_V_Interrupts( 968 agsaRoot_t *agRoot, 969 bit32 interruptVectorIndex 970 ) 971 { 972 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 973 bit64 mask; 974 agsabit32bit64 u64; 975 mask =( (bit64)1 << interruptVectorIndex); 976 u64.B64 = mask; 977 978 SA_DBG4(("siReenableMSIX_V_Interrupts:\n")); 979 980 if(saRoot->sysIntsActive) 981 { 982 if(smIS64bInt(agRoot)) 983 { 984 SA_DBG4(("siReenableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 985 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_RegisterU,u64.S32[1] ); 986 } 987 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register,u64.S32[0]); 988 } 989 else 990 { 991 SA_DBG1(("siReenableMSIX_V_Interrupts: VI %d sysIntsActive off\n",interruptVectorIndex)); 992 } 993 994 } 995 996 /******************************************************************************/ 997 /*! \brief Function to reenable MSI interrupts 998 * 999 * siReenableMSIXInterrupts reenableinterrupts 1000 * called thru macro ossaReenableInterrupts 1001 * 1002 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1003 * instance of SAS/SATA hardware 1004 * \param interruptVectorIndex - vector index for message 1005 * 1006 */ 1007 /*******************************************************************************/ 1008 GLOBAL void siReenableMSIInterrupts( 1009 agsaRoot_t *agRoot, 1010 bit32 interruptVectorIndex 1011 ) 1012 { 1013 bit32 ODMRValue; 1014 1015 ODMRValue = siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR); 1016 ODMRValue &= ~(1 << interruptVectorIndex); 1017 1018 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMRValue); 1019 } 1020 1021 /******************************************************************************/ 1022 /*! \brief Function to reenable MSI V interrupts 1023 * 1024 * siReenableMSIXInterrupts reenableinterrupts 1025 * called thru macro ossaReenableInterrupts 1026 * 1027 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1028 * instance of SAS/SATA hardware 1029 * \param interruptVectorIndex - vector index for message 1030 * 1031 */ 1032 /*******************************************************************************/ 1033 GLOBAL void siReenableMSI_V_Interrupts( 1034 agsaRoot_t *agRoot, 1035 bit32 interruptVectorIndex 1036 ) 1037 { 1038 SA_ASSERT(0, "Should not be called"); 1039 1040 SA_DBG4(("siReenableMSI_V_Interrupts:\n")); 1041 1042 } 1043 /******************************************************************************/ 1044 /*! \brief Function to reenable Legacy interrupts 1045 * 1046 * siReenableLegacyInterrupts reenableinterrupts 1047 * called thru macro ossaReenableInterrupts 1048 * 1049 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1050 * instance of SAS/SATA hardware 1051 * \param interruptVectorIndex always zero 1052 * 1053 */ 1054 /*******************************************************************************/ 1055 GLOBAL void siReenableLegacyInterrupts( 1056 agsaRoot_t *agRoot, 1057 bit32 interruptVectorIndex 1058 ) 1059 { 1060 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMR_CLEAR_ALL); 1061 1062 #ifdef SA_CLEAR_ODCR_IN_INTERRUPT 1063 siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, ODCR_CLEAR_ALL); 1064 #endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 1065 } 1066 1067 /******************************************************************************/ 1068 /*! \brief Function to reenable Legacy V interrupts 1069 * 1070 * siReenableLegacyInterrupts reenableinterrupts 1071 * called thru macro ossaReenableInterrupts 1072 * 1073 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1074 * instance of SAS/SATA hardware 1075 * \param interruptVectorIndex always zero 1076 * 1077 */ 1078 /*******************************************************************************/ 1079 GLOBAL void siReenableLegacy_V_Interrupts( 1080 agsaRoot_t *agRoot, 1081 bit32 interruptVectorIndex 1082 ) 1083 { 1084 1085 bit32 mask; 1086 mask = 1 << interruptVectorIndex; 1087 1088 SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 1089 SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1090 1091 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register, mask); 1092 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, mask ); 1093 1094 1095 SA_DBG5(("siReenableLegacy_V_Interrupts:OUT MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1096 1097 } 1098 1099 /******************************************************************************/ 1100 /*! \brief Function to enable a single interrupt vector 1101 * 1102 * 1103 * 1104 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1105 * instance of SAS/SATA hardware 1106 * \param interruptVectorIndex Interrupt vector to enable 1107 * 1108 */ 1109 /*******************************************************************************/ 1110 /******************************************************************************/ 1111 /*! \brief saSystemInterruptsEnable 1112 * Function to enable a single interrupt vector 1113 * 1114 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1115 * instance of SAS/SATA hardware 1116 * \param interruptVectorIndex Interrupt vector to enable 1117 * 1118 */ 1119 /*******************************************************************************/ 1120 GLOBAL FORCEINLINE 1121 void saSystemInterruptsEnable( 1122 agsaRoot_t *agRoot, 1123 bit32 interruptVectorIndex 1124 ) 1125 { 1126 ossaReenableInterrupts(agRoot, interruptVectorIndex); 1127 } 1128 /******************************************************************************/ 1129 /*! \brief Routine to handle Outbound Message 1130 * 1131 * The handle for outbound message 1132 * 1133 * \param agRoot handles for this instance of SAS/SATA hardware 1134 * \param count interrupt message count 1135 * \param queueNum outbound queue 1136 * 1137 * \return 1138 */ 1139 /*******************************************************************************/ 1140 LOCAL FORCEINLINE bit32 1141 siProcessOBMsg( 1142 agsaRoot_t *agRoot, 1143 bit32 count, 1144 bit32 queueNum 1145 ) 1146 { 1147 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1148 mpiOCQueue_t *circularQ = agNULL; 1149 void *pMsg1 = agNULL; 1150 bit32 ret, processedMsgCount = 0; 1151 bit32 ParseOBIombStatus = 0; 1152 #ifdef SA_ENABLE_TRACE_FUNCTIONS 1153 bit32 i = 0; 1154 #endif 1155 bit16 opcode = 0; 1156 mpiMsgCategory_t category; 1157 bit8 bc = 0; 1158 1159 smTraceFuncEnter(hpDBG_VERY_LOUD,"5r"); 1160 1161 1162 SA_DBG3(("siProcessOBMsg: queueNum 0x%x\n", queueNum)); 1163 1164 ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1165 1166 circularQ = &saRoot->outboundQueue[queueNum]; 1167 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1168 1169 if (circularQ->producerIdx == circularQ->consumerIdx) 1170 { 1171 ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1172 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5r"); 1173 return processedMsgCount; 1174 } 1175 1176 ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1177 1178 do 1179 { 1180 /* ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ 1181 ret = mpiMsgConsume(circularQ, &pMsg1, &category, &opcode, &bc); 1182 /* ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ 1183 1184 if (AGSA_RC_SUCCESS == ret) 1185 { 1186 smTrace(hpDBG_IOMB,"M0",queueNum); 1187 /* TP:M0 queueNum */ 1188 smTrace(hpDBG_VERY_LOUD,"MA",opcode); 1189 /* TP:MA opcode */ 1190 smTrace(hpDBG_IOMB,"MB",category); 1191 /* TP:MB category */ 1192 1193 #ifdef SA_ENABLE_TRACE_FUNCTIONS 1194 for (i=0; i<((bit32)bc*(circularQ->elementSize/4)); i++) 1195 { 1196 /* The -sizeof(mpiMsgHeader_t) is to account for mpiMsgConsume incrementing the pointer past the header*/ 1197 smTrace(hpDBG_IOMB,"MC",*( ((bit32*)((bit8 *)pMsg1 - sizeof(mpiMsgHeader_t))) + i)); 1198 /* TP:MC Outbound IOMB Dword */ 1199 } 1200 #endif 1201 1202 MPI_DEBUG_TRACE( circularQ->qNumber,((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),MPI_DEBUG_TRACE_OBQ, (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), circularQ->elementSize); 1203 1204 ossaLogIomb(circularQ->agRoot, 1205 circularQ->qNumber, 1206 FALSE, 1207 (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), 1208 bc*circularQ->elementSize); 1209 1210 ossaQueueProcessed(agRoot, queueNum, circularQ->producerIdx, circularQ->consumerIdx); 1211 /* process the outbound message */ 1212 ParseOBIombStatus = mpiParseOBIomb(agRoot, (bit32 *)pMsg1, category, opcode); 1213 if (ParseOBIombStatus == AGSA_RC_FAILURE) 1214 { 1215 SA_DBG1(("siProcessOBMsg, Failed Q %2d PI 0x%03x CI 0x%03x\n", queueNum, circularQ->producerIdx, circularQ->consumerIdx)); 1216 #if defined(SALLSDK_DEBUG) 1217 /* free the message for debug: this is a hang! */ 1218 1219 mpiMsgFreeSet(circularQ, pMsg1, bc); 1220 processedMsgCount ++; 1221 #endif /**/ 1222 break; 1223 } 1224 1225 /* free the message from the outbound circular buffer */ 1226 mpiMsgFreeSet(circularQ, pMsg1, bc); 1227 processedMsgCount ++; 1228 } 1229 else 1230 //if (AGSA_RC_BUSY == ret) // always (circularQ->producerIdx == circularQ->consumerIdx) 1231 // || (AGSA_RC_FAILURE == ret) 1232 { 1233 break; 1234 } 1235 } 1236 /* end of message processing if hit the count */ 1237 while(count > processedMsgCount); 1238 1239 /* #define SALLSDK_FATAL_ERROR_DETECT 1 */ 1240 /* 1241 this comments are to be removed 1242 fill in 0x1D 0x1e 0x1f 0x20 in MPI table for 1243 bit32 regDumpBusBaseNum0; 1244 bit32 regDumpOffset0; 1245 bit32 regDumpLen0; 1246 bit32 regDumpBusBaseNum1; 1247 bit32 regDumpOffset1; 1248 bit32 regDumpLen1; 1249 in agsaFatalErrorInfo_t 1250 1251 ??? regDumpBusBaseNum0 and regDumpBusBaseNum1 1252 saRoot->mainConfigTable.regDumpPCIBAR = pcibar; 1253 saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; 1254 saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; 1255 saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; 1256 saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; 1257 1258 1259 1260 */ 1261 #if defined(SALLSDK_FATAL_ERROR_DETECT) 1262 1263 if( smIS_SPC(agRoot) ) /* SPC only */ 1264 { 1265 1266 /* any fatal error happened */ 1267 /* executing this code impacts performance by 1% when no error is detected */ 1268 { 1269 agsaFatalErrorInfo_t fatal_error; 1270 bit32 value; 1271 bit32 value1; 1272 1273 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 1274 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 1275 1276 if( (value & SA_FATAL_ERROR_SP1_AAP1_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR || 1277 (value1 & SA_FATAL_ERROR_SP2_IOP_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR ) 1278 { 1279 si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 1280 /* read detail fatal errors */ 1281 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 1282 fatal_error.errorInfo0 = value; 1283 SA_DBG1(("siProcessOBMsg: ScratchPad0 AAP error code 0x%x\n", value)); 1284 1285 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 1286 fatal_error.errorInfo1 = value; 1287 /* AAP error state */ 1288 SA_DBG1(("siProcessOBMsg: AAP error state and error code 0x%x\n", value)); 1289 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 1290 fatal_error.errorInfo2 = value; 1291 /* IOP error state */ 1292 SA_DBG1(("siProcessOBMsg: IOP error state and error code 0x%x\n", value)); 1293 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 1294 SA_DBG1(("siProcessOBMsg: ScratchPad3 IOP error code 0x%x\n", value)); 1295 fatal_error.errorInfo3 = value; 1296 1297 if (agNULL != saRoot) 1298 { 1299 fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 1300 fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 1301 fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 1302 fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 1303 fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 1304 fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 1305 } 1306 else 1307 { 1308 fatal_error.regDumpBusBaseNum0 = 0; 1309 fatal_error.regDumpOffset0 = 0; 1310 fatal_error.regDumpLen0 = 0; 1311 fatal_error.regDumpBusBaseNum1 = 0; 1312 fatal_error.regDumpOffset1 = 0; 1313 fatal_error.regDumpLen1 = 0; 1314 } 1315 /* Call Back with error */ 1316 SA_DBG1(("siProcessOBMsg: SALLSDK_FATAL_ERROR_DETECT \n")); 1317 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); 1318 } 1319 } 1320 } 1321 #endif /* SALLSDK_FATAL_ERROR_DETECT */ 1322 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5r"); 1323 return processedMsgCount; 1324 } 1325 1326 /******************************************************************************/ 1327 /*! \brief Function to enable/disable interrupts 1328 * 1329 * The saSystemInterruptsActive() function is called to indicate to the LL Layer 1330 * whether interrupts are available. The parameter sysIntsActive indicates whether 1331 * interrupts are available at this time. 1332 * 1333 * \param agRoot handles for this instance of SAS/SATA hardware 1334 * \param sysIntsActive flag for enable/disable interrupt 1335 * 1336 * \return -void- 1337 * 1338 */ 1339 /*******************************************************************************/ 1340 GLOBAL void saSystemInterruptsActive( 1341 agsaRoot_t *agRoot, 1342 agBOOLEAN sysIntsActive 1343 ) 1344 { 1345 bit32 x; 1346 agsaLLRoot_t *saRoot; 1347 1348 SA_ASSERT((agNULL != agRoot), ""); 1349 if (agRoot == agNULL) 1350 { 1351 SA_DBG1(("saSystemInterruptsActive: agRoot == agNULL\n")); 1352 return; 1353 } 1354 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1355 SA_ASSERT((agNULL != saRoot), ""); 1356 if (saRoot == agNULL) 1357 { 1358 SA_DBG1(("saSystemInterruptsActive: saRoot == agNULL\n")); 1359 return; 1360 } 1361 1362 smTraceFuncEnter(hpDBG_TICK_INT,"5s"); 1363 SA_DBG1(("saSystemInterruptsActive: now 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1364 SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1365 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1366 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1367 SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", 1368 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1369 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1370 1371 if( saRoot->sysIntsActive && sysIntsActive ) 1372 { 1373 SA_DBG1(("saSystemInterruptsActive: Already active 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1374 smTraceFuncExit(hpDBG_TICK_INT, 'a', "5s"); 1375 return; 1376 } 1377 1378 if( !saRoot->sysIntsActive && !sysIntsActive ) 1379 { 1380 if(smIS_SPC(agRoot)) 1381 { 1382 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); 1383 } 1384 else 1385 { 1386 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1387 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1388 } 1389 SA_DBG1(("saSystemInterruptsActive: Already disabled 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1390 smTraceFuncExit(hpDBG_TICK_INT, 'b', "5s"); 1391 return; 1392 } 1393 1394 /* Set the flag is sdkData */ 1395 saRoot->sysIntsActive = (bit8)sysIntsActive; 1396 1397 1398 smTrace(hpDBG_TICK_INT,"Vq",sysIntsActive); 1399 /* TP:Vq sysIntsActive */ 1400 /* If sysIntsActive is true */ 1401 if ( agTRUE == sysIntsActive ) 1402 { 1403 1404 SA_DBG1(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1405 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1406 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1407 SA_DBG1(("saSystemInterruptsActive: Doorbell_Mask_Set %08X U %08X\n", 1408 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 1409 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); 1410 if(smIS_SPCV(agRoot)) 1411 { 1412 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF); 1413 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_RegisterU, 0xFFFFFFFF); 1414 } 1415 /* enable interrupt */ 1416 for(x=0; x < saRoot->numInterruptVectors; x++) 1417 { 1418 ossaReenableInterrupts(agRoot,x ); 1419 } 1420 1421 if(saRoot->swConfig.fatalErrorInterruptEnable) 1422 { 1423 ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1424 } 1425 1426 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, 0); 1427 } 1428 /* If sysIntsActive is false */ 1429 else 1430 { 1431 /* disable interrupt */ 1432 if(smIS_SPC(agRoot)) 1433 { 1434 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); 1435 } 1436 else 1437 { 1438 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1439 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1440 } 1441 } 1442 1443 SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1444 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1445 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1446 SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", 1447 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1448 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1449 1450 1451 smTraceFuncExit(hpDBG_TICK_INT, 'c', "5s"); 1452 } 1453 1454 /******************************************************************************/ 1455 /*! \brief Routine to handle for received SAS with data payload event 1456 * 1457 * The handle for received SAS with data payload event 1458 * 1459 * \param agRoot handles for this instance of SAS/SATA hardware 1460 * \param pRequest handles for the IOrequest 1461 * \param pRespIU the pointer to the Response IU 1462 * \param param Payload Length 1463 * 1464 * \return -void- 1465 */ 1466 /*******************************************************************************/ 1467 GLOBAL void siEventSSPResponseWtDataRcvd( 1468 agsaRoot_t *agRoot, 1469 agsaIORequestDesc_t *pRequest, 1470 agsaSSPResponseInfoUnit_t *pRespIU, 1471 bit32 param, 1472 bit32 sspTag 1473 ) 1474 { 1475 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1476 agsaDeviceDesc_t *pDevice; 1477 bit32 count = 0; 1478 bit32 padCount; 1479 1480 smTraceFuncEnter(hpDBG_VERY_LOUD,"5g"); 1481 1482 /* get frame handle */ 1483 1484 /* If the request is still valid */ 1485 if ( agTRUE == pRequest->valid ) 1486 { 1487 /* get device */ 1488 pDevice = pRequest->pDevice; 1489 1490 /* Delete the request from the pendingIORequests */ 1491 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1492 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1493 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1494 1495 if (sspTag & SSP_RESCV_BIT) 1496 { 1497 /* get the pad count, bit 17 and 18 of sspTag */ 1498 padCount = (sspTag >> SSP_RESCV_PAD_SHIFT) & 0x3; 1499 /* get Residual Count */ 1500 count = *(bit32 *)((bit8 *)pRespIU + param + padCount); 1501 } 1502 1503 (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1504 pRequest->pIORequestContext, 1505 OSSA_IO_SUCCESS, 1506 param, 1507 (void *)pRespIU, 1508 (bit16)(sspTag & SSPTAG_BITS), 1509 count); 1510 1511 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1512 pRequest->valid = agFALSE; 1513 /* return the request to free pool */ 1514 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1515 { 1516 SA_DBG1(("siEventSSPResponseWtDataRcvd: saving pRequest (%p) for later use\n", pRequest)); 1517 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1518 } 1519 else 1520 { 1521 /* return the request to free pool */ 1522 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1523 } 1524 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1525 1526 } 1527 else 1528 { 1529 SA_DBG1(("siEventSSPResponseWtDataRcvd: pRequest->Valid not TRUE\n")); 1530 } 1531 1532 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5g"); 1533 1534 return; 1535 } 1536 1537 /******************************************************************************/ 1538 /*! \brief Routine to handle successfully completed IO event 1539 * 1540 * Handle successfully completed IO 1541 * 1542 * \param agRoot handles for this instance of SAS/SATA hardware 1543 * \param pRequest Pointer of IO request of the IO 1544 * \param status status of the IO 1545 * 1546 * \return -void- 1547 */ 1548 /*******************************************************************************/ 1549 GLOBAL FORCEINLINE void siIODone( 1550 agsaRoot_t *agRoot, 1551 agsaIORequestDesc_t *pRequest, 1552 bit32 status, 1553 bit32 sspTag 1554 ) 1555 { 1556 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1557 agsaDeviceDesc_t *pDevice = agNULL; 1558 1559 smTraceFuncEnter(hpDBG_VERY_LOUD,"5h"); 1560 1561 SA_ASSERT(NULL != pRequest, "pRequest cannot be null"); 1562 1563 /* If the request is still valid */ 1564 if ( agTRUE == pRequest->valid ) 1565 { 1566 /* get device */ 1567 pDevice = pRequest->pDevice; 1568 1569 /* process different request type */ 1570 switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1571 { 1572 case AGSA_SSP_REQTYPE: 1573 { 1574 SA_ASSERT(pRequest->valid, "pRequest not valid"); 1575 pRequest->completionCB(agRoot, 1576 pRequest->pIORequestContext, 1577 OSSA_IO_SUCCESS, 1578 0, 1579 agNULL, 1580 (bit16)(sspTag & SSPTAG_BITS), 1581 0); 1582 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1583 /* Delete the request from the pendingIORequests */ 1584 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1585 /* return the request to free pool */ 1586 pRequest->valid = agFALSE; 1587 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1588 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1589 1590 1591 break; 1592 } 1593 case AGSA_SATA_REQTYPE: 1594 { 1595 SA_DBG5(("siIODone: SATA complete\n")); 1596 1597 if ( agNULL != pRequest->pIORequestContext ) 1598 { 1599 SA_DBG5(("siIODone: Complete Request\n")); 1600 1601 (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, 1602 pRequest->pIORequestContext, 1603 OSSA_IO_SUCCESS, 1604 agNULL, 1605 0, 1606 agNULL); 1607 } 1608 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1609 /* Delete the request from the pendingIORequests */ 1610 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1611 /* return the request to free pool */ 1612 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1613 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1614 1615 pRequest->valid = agFALSE; 1616 1617 break; 1618 } 1619 case AGSA_SMP_REQTYPE: 1620 { 1621 if ( agNULL != pRequest->pIORequestContext ) 1622 { 1623 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, 1624 pRequest->pIORequestContext, 1625 OSSA_IO_SUCCESS, 1626 0, 1627 agNULL); 1628 } 1629 1630 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1631 /* Delete the request from the pendingSMPRequests */ 1632 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1633 /* return the request to free pool */ 1634 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1635 { 1636 SA_DBG1(("siIODone: saving pRequest (%p) for later use\n", pRequest)); 1637 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1638 } 1639 else 1640 { 1641 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1642 } 1643 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1644 1645 pRequest->valid = agFALSE; 1646 1647 break; 1648 } 1649 default: 1650 { 1651 SA_DBG1(("siIODone: unknown request type (%x) is completed. HTag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1652 break; 1653 } 1654 } 1655 } 1656 else 1657 { 1658 SA_DBG1(("siIODone: The request is not valid any more. HTag=0x%x requestType=0x%x\n", pRequest->HTag, pRequest->requestType)); 1659 } 1660 1661 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5h"); 1662 1663 } 1664 1665 /******************************************************************************/ 1666 /*! \brief Routine to handle abnormal completed IO/SMP event 1667 * 1668 * Handle abnormal completed IO/SMP 1669 * 1670 * \param agRoot handles for this instance of SAS/SATA hardware 1671 * \param pRequest Pointer of IO request of the IO 1672 * \param status status of the IO 1673 * \param param Length 1674 * 1675 * \return -void- 1676 */ 1677 /*******************************************************************************/ 1678 GLOBAL void siAbnormal( 1679 agsaRoot_t *agRoot, 1680 agsaIORequestDesc_t *pRequest, 1681 bit32 status, 1682 bit32 param, 1683 bit32 sspTag 1684 ) 1685 { 1686 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1687 agsaDeviceDesc_t *pDevice; 1688 1689 smTraceFuncEnter(hpDBG_VERY_LOUD,"5i"); 1690 1691 if (agNULL == pRequest) 1692 { 1693 SA_DBG1(("siAbnormal: pRequest is NULL.\n")); 1694 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5i"); 1695 return; 1696 } 1697 1698 /* If the request is still valid */ 1699 if ( agTRUE == pRequest->valid ) 1700 { 1701 /* get device */ 1702 1703 SA_ASSERT((pRequest->pIORequestContext->osData != pRequest->pIORequestContext->sdkData), "pIORequestContext"); 1704 1705 pDevice = pRequest->pDevice; 1706 1707 /* remove the IO request from IOMap */ 1708 saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; 1709 saRoot->IOMap[pRequest->HTag].IORequest = agNULL; 1710 saRoot->IOMap[pRequest->HTag].agContext = agNULL; 1711 1712 smTrace(hpDBG_VERY_LOUD,"P6",status ); 1713 /* TP:P6 siAbnormal status */ 1714 smTrace(hpDBG_VERY_LOUD,"P7",param ); 1715 /* TP:P7 siAbnormal param */ 1716 /* process different request type */ 1717 switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1718 { 1719 case AGSA_SSP_REQTYPE: 1720 { 1721 (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1722 pRequest->pIORequestContext, 1723 status, 1724 param, 1725 agNULL, 1726 (bit16)(sspTag & SSPTAG_BITS), 1727 ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); 1728 1729 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1730 /* Delete the request from the pendingIORequests */ 1731 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1732 pRequest->valid = agFALSE; 1733 /* return the request to free pool */ 1734 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1735 { 1736 SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1737 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1738 } 1739 else 1740 { 1741 /* return the request to free pool */ 1742 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1743 } 1744 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1745 1746 break; 1747 } 1748 case AGSA_SATA_REQTYPE: 1749 { 1750 SA_DBG5(("siAbnormal: SATA \n")); 1751 1752 if ( agNULL != pRequest->pIORequestContext ) 1753 { 1754 SA_DBG5(("siAbnormal: Calling SATACompletedCB\n")); 1755 1756 (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, 1757 pRequest->pIORequestContext, 1758 status, 1759 agNULL, 1760 param, 1761 agNULL); 1762 } 1763 1764 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1765 /* Delete the request from the pendingIORequests */ 1766 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1767 /* return the request to free pool */ 1768 pRequest->valid = agFALSE; 1769 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1770 { 1771 SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1772 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1773 } 1774 else 1775 { 1776 /* return the request to free pool */ 1777 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1778 } 1779 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1780 1781 break; 1782 } 1783 case AGSA_SMP_REQTYPE: 1784 { 1785 if ( agNULL != pRequest->pIORequestContext ) 1786 { 1787 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, 1788 pRequest->pIORequestContext, 1789 status, 1790 param, 1791 agNULL); 1792 } 1793 1794 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1795 /* Delete the request from the pendingSMPRequests */ 1796 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1797 /* return the request to free pool */ 1798 pRequest->valid = agFALSE; 1799 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1800 { 1801 SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1802 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1803 } 1804 else 1805 { 1806 /* return the request to free pool */ 1807 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1808 } 1809 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1810 1811 break; 1812 } 1813 default: 1814 { 1815 SA_DBG1(("siAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1816 break; 1817 } 1818 } 1819 1820 } 1821 else 1822 { 1823 SA_DBG1(("siAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); 1824 } 1825 1826 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5i"); 1827 1828 return; 1829 } 1830 1831 1832 /******************************************************************************/ 1833 /*! \brief Routine to handle abnormal DIF completed IO/SMP event 1834 * 1835 * Handle abnormal completed IO/SMP 1836 * 1837 * \param agRoot handles for this instance of SAS/SATA hardware 1838 * \param pRequest Pointer of IO request of the IO 1839 * \param status status of the IO 1840 * \param param Length 1841 * 1842 * \return -void- 1843 */ 1844 /*******************************************************************************/ 1845 GLOBAL void siDifAbnormal( 1846 agsaRoot_t *agRoot, 1847 agsaIORequestDesc_t *pRequest, 1848 bit32 status, 1849 bit32 param, 1850 bit32 sspTag, 1851 bit32 *pMsg1 1852 ) 1853 { 1854 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1855 agsaDeviceDesc_t *pDevice; 1856 1857 smTraceFuncEnter(hpDBG_VERY_LOUD,"2S"); 1858 1859 if (agNULL == pRequest) 1860 { 1861 SA_DBG1(("siDifAbnormal: pRequest is NULL.\n")); 1862 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2S"); 1863 return; 1864 } 1865 1866 /* If the request is still valid */ 1867 if ( agTRUE == pRequest->valid ) 1868 { 1869 /* get device */ 1870 pDevice = pRequest->pDevice; 1871 1872 /* remove the IO request from IOMap */ 1873 saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; 1874 saRoot->IOMap[pRequest->HTag].IORequest = agNULL; 1875 saRoot->IOMap[pRequest->HTag].agContext = agNULL; 1876 1877 smTrace(hpDBG_VERY_LOUD,"P6",status ); 1878 /* TP:P6 siDifAbnormal status */ 1879 /* process different request type */ 1880 switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1881 { 1882 case AGSA_SSP_REQTYPE: 1883 { 1884 agsaDifDetails_t agDifDetails; 1885 agsaSSPCompletionDifRsp_t *pIomb; 1886 pIomb = (agsaSSPCompletionDifRsp_t *)pMsg1; 1887 si_memset(&agDifDetails, 0, sizeof(agDifDetails)); 1888 1889 OSSA_READ_LE_32(agRoot, &agDifDetails.UpperLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,UpperLBA )); 1890 OSSA_READ_LE_32(agRoot, &agDifDetails.LowerLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,LowerLBA )); 1891 OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressHi, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressHi )); 1892 OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressLo, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressLo)); 1893 OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedCRCUDT01 )); 1894 OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedUDT2345)); 1895 OSSA_READ_LE_32(agRoot, &agDifDetails.ActualCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualCRCUDT01 )); 1896 OSSA_READ_LE_32(agRoot, &agDifDetails.ActualUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualUDT2345)); 1897 OSSA_READ_LE_32(agRoot, &agDifDetails.DIFErrDevID, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,DIFErrDevID )); 1898 OSSA_READ_LE_32(agRoot, &agDifDetails.ErrBoffsetEDataLen, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ErrBoffsetEDataLen )); 1899 agDifDetails.frame = (void *)(bit8*)(pIomb+ OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t, EDATA_FRM)); 1900 1901 (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1902 pRequest->pIORequestContext, 1903 status, 1904 param, 1905 &agDifDetails, 1906 (bit16)(sspTag & SSPTAG_BITS), 1907 ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); 1908 1909 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1910 pRequest->valid = agFALSE; 1911 /* Delete the request from the pendingIORequests */ 1912 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1913 1914 /* return the request to free pool */ 1915 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1916 { 1917 SA_DBG1(("siDifAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1918 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1919 } 1920 else 1921 { 1922 /* return the request to free pool */ 1923 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1924 } 1925 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1926 1927 break; 1928 } 1929 default: 1930 { 1931 SA_DBG1(("siDifAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1932 break; 1933 } 1934 } 1935 1936 } 1937 else 1938 { 1939 SA_DBG1(("siDifAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); 1940 } 1941 1942 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2S"); 1943 1944 return; 1945 } 1946 1947 1948 /******************************************************************************/ 1949 /*! \brief Routine to handle for received SMP response event 1950 * 1951 * The handle for received SMP response event 1952 * 1953 * \param agRoot handles for this instance of SAS/SATA hardware 1954 * \param pIomb Pointer of payload of IOMB 1955 * \param payloadSize size of the payload 1956 * \param tag the tag of the request SMP 1957 * 1958 * \return -void- 1959 */ 1960 /*******************************************************************************/ 1961 GLOBAL void siSMPRespRcvd( 1962 agsaRoot_t *agRoot, 1963 agsaSMPCompletionRsp_t *pIomb, 1964 bit32 payloadSize, 1965 bit32 tag 1966 ) 1967 { 1968 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1969 agsaFrameHandle_t frameHandle; 1970 agsaIORequestDesc_t *pRequest; 1971 agsaDeviceDesc_t *pDevice; 1972 agsaPort_t *pPort; 1973 1974 smTraceFuncEnter(hpDBG_VERY_LOUD,"5j"); 1975 1976 /* get the request */ 1977 pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; 1978 SA_ASSERT(pRequest, "pRequest"); 1979 1980 /* get the port */ 1981 pPort = pRequest->pPort; 1982 SA_ASSERT(pPort, "pPort"); 1983 1984 if (pRequest->IRmode == 0) 1985 { 1986 /* get frame handle - direct response mode */ 1987 frameHandle = (agsaFrameHandle_t)(&(pIomb->SMPrsp[0])); 1988 #if defined(SALLSDK_DEBUG) 1989 SA_DBG3(("saSMPRespRcvd(direct): smpRspPtr=0x%p - len=0x%x\n", 1990 frameHandle, 1991 payloadSize 1992 )); 1993 #endif /* SALLSDK_DEBUG */ 1994 } 1995 else 1996 { 1997 /* indirect response mode */ 1998 frameHandle = agNULL; 1999 } 2000 2001 /* If the request is still valid */ 2002 if ( agTRUE == pRequest->valid ) 2003 { 2004 /* get device */ 2005 pDevice = pRequest->pDevice; 2006 SA_ASSERT(pDevice, "pDevice"); 2007 2008 /* Delete the request from the pendingSMPRequests */ 2009 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2010 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 2011 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2012 2013 /* If the request is from OS layer */ 2014 if ( agNULL != pRequest->pIORequestContext ) 2015 { 2016 if (agNULL == frameHandle) 2017 { 2018 /* indirect mode */ 2019 /* call back with success */ 2020 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); 2021 } 2022 else 2023 { 2024 /* direct mode */ 2025 /* call back with success */ 2026 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); 2027 } 2028 } 2029 2030 /* remove the IO request from IOMap */ 2031 saRoot->IOMap[tag].Tag = MARK_OFF; 2032 saRoot->IOMap[tag].IORequest = agNULL; 2033 saRoot->IOMap[tag].agContext = agNULL; 2034 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2035 pRequest->valid = agFALSE; 2036 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 2037 { 2038 SA_DBG1(("siSMPRespRcvd: saving pRequest (%p) for later use\n", pRequest)); 2039 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 2040 } 2041 else 2042 { 2043 /* return the request to free pool */ 2044 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 2045 } 2046 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2047 } 2048 2049 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5j"); 2050 2051 return; 2052 } 2053 2054 /******************************************************************************/ 2055 /*! \brief Routine to handle for received Phy Up event 2056 * 2057 * The handle for received Phy Up event 2058 * 2059 * \param agRoot handles for this instance of SAS/SATA hardware 2060 * \param phyId for the Phy Up event happened 2061 * \param agSASIdentify is the remote phy Identify 2062 * \param portId is the port context index of the phy up event 2063 * \param deviceId is the device context index 2064 * \param linkRate link up rate from SPC 2065 * 2066 * \return -void- 2067 */ 2068 /*******************************************************************************/ 2069 GLOBAL void siEventPhyUpRcvd( 2070 agsaRoot_t *agRoot, 2071 bit32 phyId, 2072 agsaSASIdentify_t *agSASIdentify, 2073 bit32 portId, 2074 bit32 npipps, 2075 bit8 linkRate 2076 ) 2077 { 2078 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2079 agsaPhy_t *pPhy = &(saRoot->phys[phyId]); 2080 agsaPort_t *pPort; 2081 agsaSASIdentify_t remoteIdentify; 2082 agsaPortContext_t *agPortContext; 2083 2084 smTraceFuncEnter(hpDBG_VERY_LOUD,"5k"); 2085 2086 /* Read remote SAS Identify from response message and save it */ 2087 remoteIdentify = *agSASIdentify; 2088 2089 /* get port context from portMap */ 2090 SA_DBG2(("siEventPhyUpRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); 2091 agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; 2092 2093 SA_DBG2(("siEventPhyUpRcvd: portID %d PortContext %p linkRate 0x%X\n", portId, agPortContext,linkRate)); 2094 if (smIS_SPCV8006(agRoot)) 2095 { 2096 SA_DBG1(("siEventPhyUpRcvd: SAS_PHY_UP received for SATA Controller\n")); 2097 return; 2098 } 2099 2100 if (agNULL != agPortContext) 2101 { 2102 /* existing port */ 2103 pPort = (agsaPort_t *) (agPortContext->sdkData); 2104 pPort->portId = portId; 2105 2106 /* include the phy to the port */ 2107 pPort->phyMap[phyId] = agTRUE; 2108 /* Set the port for the phy */ 2109 saRoot->phys[phyId].pPort = pPort; 2110 2111 /* Update port state */ 2112 if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2113 { 2114 pPort->status &= ~PORT_INVALIDATING; 2115 saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2116 SA_DBG1(("siEventPhyUpRcvd: portID %d PortContext %p, hitting workaround\n", portId, agPortContext)); 2117 } 2118 } 2119 else 2120 { 2121 ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); 2122 /* new port */ 2123 /* Allocate a free port */ 2124 pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); 2125 if (agNULL != pPort) 2126 { 2127 /* Acquire port list lock */ 2128 saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); 2129 2130 /* setup the port data structure */ 2131 pPort->portContext.osData = agNULL; 2132 pPort->portContext.sdkData = pPort; 2133 2134 /* Add to valid port list */ 2135 saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); 2136 /* Release port list lock */ 2137 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2138 2139 /* include the phy to the port */ 2140 pPort->phyMap[phyId] = agTRUE; 2141 /* Set the port for the phy */ 2142 saRoot->phys[phyId].pPort = pPort; 2143 2144 /* Setup portMap based on portId */ 2145 saRoot->PortMap[portId].PortID = portId; 2146 saRoot->PortMap[portId].PortContext = &(pPort->portContext); 2147 pPort->portId = portId; 2148 2149 SA_DBG3(("siEventPhyUpRcvd: NewPort portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2150 } 2151 else 2152 { 2153 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2154 /* pPort is agNULL*/ 2155 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5k"); 2156 return; 2157 } 2158 2159 if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2160 { 2161 pPort->status &= ~PORT_INVALIDATING; 2162 saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2163 } 2164 else 2165 { 2166 SA_DBG1(("siEventPhyUpRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2167 } 2168 } 2169 2170 /* adjust the bit fields before callback */ 2171 phyId = (linkRate << SHIFT8) | phyId; 2172 /* report PhyId, NPIP, PortState */ 2173 phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); 2174 ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SAS_PHY_UP, phyId, agNULL, &remoteIdentify); 2175 2176 /* set PHY_UP status */ 2177 PHY_STATUS_SET(pPhy, PHY_UP); 2178 2179 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5k"); 2180 2181 /* return */ 2182 return; 2183 } 2184 2185 /******************************************************************************/ 2186 /*! \brief Routine to handle for received SATA signature event 2187 * 2188 * The handle for received SATA signature event 2189 * 2190 * \param agRoot handles for this instance of SAS/SATA hardware 2191 * \param phyId the phy id of the phy received the frame 2192 * \param pMsg the pointer to the message payload 2193 * \param portId the port context index of the phy up event 2194 * \param deviceId the device context index 2195 * \param linkRate link up rate from SPC 2196 * 2197 * \return -void- 2198 */ 2199 /*******************************************************************************/ 2200 GLOBAL void siEventSATASignatureRcvd( 2201 agsaRoot_t *agRoot, 2202 bit32 phyId, 2203 void *pMsg, 2204 bit32 portId, 2205 bit32 npipps, 2206 bit8 linkRate 2207 ) 2208 { 2209 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2210 agsaPhy_t *pPhy = &(saRoot->phys[phyId]); 2211 agsaPort_t *pPort = agNULL; 2212 agsaPortContext_t *agPortContext; 2213 #if defined(SALLSDK_DEBUG) 2214 agsaFisRegDeviceToHost_t *fisD2H; 2215 /* Read the D2H FIS */ 2216 fisD2H = (agsaFisRegDeviceToHost_t *)pMsg; 2217 #endif /* SALLSDK_DEBUG */ 2218 2219 smTraceFuncEnter(hpDBG_VERY_LOUD,"5m"); 2220 2221 SA_DBG5(("siEventSATASignatureRcvd: About to read the signatureFIS data\n")); 2222 2223 2224 SA_DBG5(("agsaFisRegDeviceToHost_t:\n")); 2225 SA_DBG5((" fisType = %x\n", fisD2H->h.fisType)); 2226 SA_DBG5((" i_pmPort = %x\n", fisD2H->h.i_pmPort)); 2227 SA_DBG5((" status = %x\n", fisD2H->h.status)); 2228 SA_DBG5((" error = %x\n", fisD2H->h.error)); 2229 2230 SA_DBG5((" lbaLow = %x\n", fisD2H->d.lbaLow)); 2231 SA_DBG5((" lbaMid = %x\n", fisD2H->d.lbaMid)); 2232 SA_DBG5((" lbaHigh = %x\n", fisD2H->d.lbaHigh)); 2233 SA_DBG5((" device = %x\n", fisD2H->d.device)); 2234 2235 SA_DBG5((" lbaLowExp = %x\n", fisD2H->d.lbaLowExp)); 2236 SA_DBG5((" lbaMidExp = %x\n", fisD2H->d.lbaMidExp)); 2237 SA_DBG5((" lbaHighExp = %x\n", fisD2H->d.lbaHighExp)); 2238 SA_DBG5((" reserved4 = %x\n", fisD2H->d.reserved4)); 2239 2240 SA_DBG5((" sectorCount = %x\n", fisD2H->d.sectorCount)); 2241 SA_DBG5((" sectorCountExp = %x\n", fisD2H->d.sectorCountExp)); 2242 SA_DBG5((" reserved5 = %x\n", fisD2H->d.reserved5)); 2243 SA_DBG5((" reserved6 = %x\n", fisD2H->d.reserved6)); 2244 2245 SA_DBG5((" reserved7 (32) = %08X\n", fisD2H->d.reserved7)); 2246 2247 SA_DBG5(("siEventSATASignatureRcvd: GOOD signatureFIS data\n")); 2248 2249 #if defined(SALLSDK_DEBUG) 2250 /* read signature */ 2251 pPhy->remoteSignature[0] = (bit8) fisD2H->d.sectorCount; 2252 pPhy->remoteSignature[1] = (bit8) fisD2H->d.lbaLow; 2253 pPhy->remoteSignature[2] = (bit8) fisD2H->d.lbaMid; 2254 pPhy->remoteSignature[3] = (bit8) fisD2H->d.lbaHigh; 2255 pPhy->remoteSignature[4] = (bit8) fisD2H->d.device; 2256 #endif 2257 2258 /* get port context from portMap */ 2259 SA_DBG2(("siEventSATASignatureRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); 2260 agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; 2261 2262 SA_DBG2(("siEventSATASignatureRcvd: portID %d PortContext %p\n", portId, agPortContext)); 2263 2264 if (agNULL != agPortContext) 2265 { 2266 /* exist port */ 2267 pPort = (agsaPort_t *) (agPortContext->sdkData); 2268 pPort->portId = portId; 2269 2270 /* include the phy to the port */ 2271 pPort->phyMap[phyId] = agTRUE; 2272 /* Set the port for the phy */ 2273 saRoot->phys[phyId].pPort = pPort; 2274 } 2275 else 2276 { 2277 ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); 2278 /* new port */ 2279 /* Allocate a free port */ 2280 pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); 2281 if (agNULL != pPort) 2282 { 2283 /* Acquire port list lock */ 2284 saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); 2285 2286 /* setup the port data structure */ 2287 pPort->portContext.osData = agNULL; 2288 pPort->portContext.sdkData = pPort; 2289 2290 /* Add to valid port list */ 2291 saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); 2292 /* Release port list lock */ 2293 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2294 2295 /* include the phy to the port */ 2296 pPort->phyMap[phyId] = agTRUE; 2297 /* Set the port for the phy */ 2298 saRoot->phys[phyId].pPort = pPort; 2299 2300 /* Setup portMap based on portId */ 2301 saRoot->PortMap[portId].PortID = portId; 2302 saRoot->PortMap[portId].PortContext = &(pPort->portContext); 2303 pPort->portId = portId; 2304 SA_DBG3(("siEventSATASignatureRcvd: NewPort portID %d portContect %p\n", portId, saRoot->PortMap[portId].PortContext)); 2305 } 2306 else 2307 { 2308 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2309 /* pPort is agNULL*/ 2310 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5m"); 2311 return; 2312 } 2313 2314 if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2315 { 2316 pPort->status &= ~PORT_INVALIDATING; 2317 saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2318 } 2319 else 2320 { 2321 SA_DBG1(("siEventSATASignatureRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2322 } 2323 } 2324 2325 /* adjust the bit fields before callback */ 2326 phyId = (linkRate << SHIFT8) | phyId; 2327 /* report PhyId, NPIP, PortState */ 2328 phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); 2329 ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SATA_PHY_UP, phyId, agNULL, pMsg); 2330 2331 /* set PHY_UP status */ 2332 PHY_STATUS_SET(pPhy, PHY_UP); 2333 2334 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5m"); 2335 2336 /* return */ 2337 return; 2338 } 2339 2340 2341 /******************************************************************************/ 2342 /*! \brief Process Outbound IOMB Message 2343 * 2344 * Process Outbound IOMB from SPC 2345 * 2346 * \param agRoot Handles for this instance of SAS/SATA LL Layer 2347 * \param pMsg1 Pointer of Response IOMB message 1 2348 * \param category category of outbpond IOMB header 2349 * \param opcode Opcode of Outbound IOMB header 2350 * \param bc buffer count of IOMB header 2351 * 2352 * \return success or fail 2353 * 2354 */ 2355 /*******************************************************************************/ 2356 GLOBAL bit32 mpiParseOBIomb( 2357 agsaRoot_t *agRoot, 2358 bit32 *pMsg1, 2359 mpiMsgCategory_t category, 2360 bit16 opcode 2361 ) 2362 { 2363 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2364 bit32 ret = AGSA_RC_SUCCESS; 2365 bit32 parserStatus = AGSA_RC_SUCCESS; 2366 2367 smTraceFuncEnter(hpDBG_VERY_LOUD, "2f"); 2368 2369 switch (opcode) 2370 { 2371 case OPC_OUB_COMBINED_SSP_COMP: 2372 { 2373 agsaSSPCoalescedCompletionRsp_t *pIomb = (agsaSSPCoalescedCompletionRsp_t *)pMsg1; 2374 agsaIORequestDesc_t *pRequest = agNULL; 2375 bit32 tag = 0; 2376 bit32 sspTag = 0; 2377 bit32 count = 0; 2378 2379 #ifdef SALL_API_TEST 2380 saRoot->LLCounters.IOCounter.numSSPCompleted++; 2381 SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", 2382 pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2383 #else 2384 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP Response received IOMB=%p\n", pMsg1)); 2385 #endif 2386 /* get Tag */ 2387 for (count = 0; count < pIomb->coalescedCount; count++) 2388 { 2389 tag = pIomb->sspComplCxt[count].tag; 2390 sspTag = pIomb->sspComplCxt[count].SSPTag; 2391 pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 2392 SA_ASSERT((pRequest), "pRequest"); 2393 2394 if(pRequest == agNULL) 2395 { 2396 SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SSP_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); 2397 #ifdef SA_ENABLE_PCI_TRIGGER 2398 if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_IOMB_ERROR ) 2399 { 2400 siPCITriger(agRoot); 2401 } 2402 #endif /* SA_ENABLE_PCI_TRIGGER */ 2403 return(AGSA_RC_FAILURE); 2404 } 2405 SA_ASSERT((pRequest->valid), "pRequest->valid"); 2406 2407 #ifdef SA_ENABLE_PCI_TRIGGER 2408 if(!pRequest->valid) 2409 { 2410 if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_INVALID ) 2411 { 2412 siPCITriger(agRoot); 2413 } 2414 } 2415 #endif /* SA_ENABLE_PCI_TRIGGER */ 2416 2417 2418 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); 2419 2420 /* Completion of SSP without Response Data */ 2421 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); 2422 } 2423 } 2424 break; 2425 2426 case OPC_OUB_SSP_COMP: 2427 { 2428 #ifdef SALL_API_TEST 2429 saRoot->LLCounters.IOCounter.numSSPCompleted++; 2430 SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", 2431 pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2432 #else 2433 SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p\n", pMsg1)); 2434 #endif 2435 /* process the SSP IO Completed response message */ 2436 mpiSSPCompletion(agRoot, pMsg1); 2437 break; 2438 } 2439 case OPC_OUB_COMBINED_SATA_COMP: 2440 { 2441 agsaSATACoalescedCompletionRsp_t *pIomb; 2442 agsaIORequestDesc_t *pRequest; 2443 bit32 tag; 2444 bit32 count; 2445 2446 #ifdef SALL_API_TEST 2447 saRoot->LLCounters.IOCounter.numSSPCompleted++; 2448 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p %d\n", 2449 pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2450 #else 2451 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p\n", pMsg1)); 2452 #endif 2453 2454 pIomb = (agsaSATACoalescedCompletionRsp_t *)pMsg1; 2455 /* get Tag */ 2456 for (count = 0; count < pIomb->coalescedCount; count++) 2457 { 2458 tag = pIomb->stpComplCxt[count].tag; 2459 pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 2460 SA_ASSERT((pRequest), "pRequest"); 2461 2462 if(pRequest == agNULL) 2463 { 2464 SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SATA_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); 2465 return(AGSA_RC_FAILURE); 2466 } 2467 SA_ASSERT((pRequest->valid), "pRequest->valid"); 2468 2469 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); 2470 2471 /* Completion of SATA without Response Data */ 2472 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); 2473 } 2474 break; 2475 } 2476 case OPC_OUB_SATA_COMP: 2477 { 2478 #ifdef SALL_API_TEST 2479 saRoot->LLCounters.IOCounter.numSataCompleted++; 2480 SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p %d\n", 2481 pMsg1, saRoot->LLCounters.IOCounter.numSataCompleted)); 2482 #else 2483 SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p\n", pMsg1)); 2484 #endif 2485 /* process the response message */ 2486 mpiSATACompletion(agRoot, pMsg1); 2487 break; 2488 } 2489 case OPC_OUB_SSP_ABORT_RSP: 2490 { 2491 #ifdef SALL_API_TEST 2492 saRoot->LLCounters.IOCounter.numSSPAbortedCB++; 2493 #else 2494 SA_DBG3(("mpiParseOBIomb, SSP_ABORT Response received IOMB=%p\n", pMsg1)); 2495 #endif 2496 /* process the response message */ 2497 parserStatus = mpiSSPAbortRsp(agRoot, (agsaSSPAbortRsp_t *)pMsg1); 2498 if(parserStatus != AGSA_RC_SUCCESS) 2499 { 2500 SA_DBG3(("mpiParseOBIomb, mpiSSPAbortRsp FAIL IOMB=%p\n", pMsg1)); 2501 } 2502 2503 break; 2504 } 2505 case OPC_OUB_SATA_ABORT_RSP: 2506 { 2507 #ifdef SALL_API_TEST 2508 saRoot->LLCounters.IOCounter.numSataAbortedCB++; 2509 #else 2510 SA_DBG3(("mpiParseOBIomb, SATA_ABORT Response received IOMB=%p\n", pMsg1)); 2511 #endif 2512 /* process the response message */ 2513 mpiSATAAbortRsp(agRoot, (agsaSATAAbortRsp_t *)pMsg1); 2514 break; 2515 } 2516 case OPC_OUB_SATA_EVENT: 2517 { 2518 SA_DBG3(("mpiParseOBIomb, SATA_EVENT Response received IOMB=%p\n", pMsg1)); 2519 /* process the response message */ 2520 mpiSATAEvent(agRoot, (agsaSATAEventRsp_t *)pMsg1); 2521 break; 2522 } 2523 case OPC_OUB_SSP_EVENT: 2524 { 2525 SA_DBG3(("mpiParseOBIomb, SSP_EVENT Response received IOMB=%p\n", pMsg1)); 2526 /* process the response message */ 2527 mpiSSPEvent(agRoot, (agsaSSPEventRsp_t *)pMsg1); 2528 break; 2529 } 2530 case OPC_OUB_SMP_COMP: 2531 { 2532 #ifdef SALL_API_TEST 2533 saRoot->LLCounters.IOCounter.numSMPCompleted++; 2534 SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p, %d\n", 2535 pMsg1, saRoot->LLCounters.IOCounter.numSMPCompleted)); 2536 #else 2537 SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p\n", pMsg1)); 2538 #endif 2539 /* process the response message */ 2540 mpiSMPCompletion(agRoot, (agsaSMPCompletionRsp_t *)pMsg1); 2541 break; 2542 } 2543 case OPC_OUB_ECHO: 2544 { 2545 #ifdef SALL_API_TEST 2546 saRoot->LLCounters.IOCounter.numEchoCB++; 2547 SA_DBG3(("mpiParseOBIomb, ECHO Response received %d\n", saRoot->LLCounters.IOCounter.numEchoCB)); 2548 #else 2549 SA_DBG3(("mpiParseOBIomb, ECHO Response received\n")); 2550 #endif 2551 /* process the response message */ 2552 mpiEchoRsp(agRoot, (agsaEchoRsp_t *)pMsg1); 2553 break; 2554 } 2555 case OPC_OUB_GET_NVMD_DATA: 2556 { 2557 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_NVMD_DATA received IOMB=%p\n", pMsg1)); 2558 /* process the response message */ 2559 mpiGetNVMDataRsp(agRoot, (agsaGetNVMDataRsp_t *)pMsg1); 2560 break; 2561 } 2562 case OPC_OUB_SPC_HW_EVENT: 2563 { 2564 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2565 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_HW_EVENT Response received IOMB=%p\n", pMsg1)); 2566 /* process the response message */ 2567 mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); 2568 break; 2569 } 2570 case OPC_OUB_HW_EVENT: 2571 { 2572 SA_DBG3(("mpiParseOBIomb, HW_EVENT Response received IOMB=%p\n", pMsg1)); 2573 /* process the response message */ 2574 mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); 2575 break; 2576 } 2577 case OPC_OUB_PHY_START_RESPONSE: 2578 { 2579 SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_START_RESPONSE Response received IOMB=%p\n", pMsg1)); 2580 /* process the response message */ 2581 mpiPhyStartEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); 2582 2583 break; 2584 } 2585 case OPC_OUB_PHY_STOP_RESPONSE: 2586 { 2587 SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_STOP_RESPONSE Response received IOMB=%p\n", pMsg1)); 2588 /* process the response message */ 2589 mpiPhyStopEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); 2590 break; 2591 } 2592 2593 case OPC_OUB_LOCAL_PHY_CNTRL: 2594 { 2595 SA_DBG3(("mpiParseOBIomb, PHY CONTROL Response received IOMB=%p\n", pMsg1)); 2596 /* process the response message */ 2597 mpiPhyCntrlRsp(agRoot, (agsaLocalPhyCntrlRsp_t *)pMsg1); 2598 break; 2599 } 2600 case OPC_OUB_SPC_DEV_REGIST: 2601 { 2602 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2603 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_DEV_REGIST Response received IOMB=%p\n", pMsg1)); 2604 /* process the response message */ 2605 mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); 2606 break; 2607 } 2608 case OPC_OUB_DEV_REGIST: 2609 { 2610 SA_DBG2(("mpiParseOBIomb, DEV_REGISTRATION Response received IOMB=%p\n", pMsg1)); 2611 /* process the response message */ 2612 mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); 2613 break; 2614 } 2615 case OPC_OUB_DEREG_DEV: 2616 { 2617 SA_DBG3(("mpiParseOBIomb, DEREGISTRATION DEVICE Response received IOMB=%p\n", pMsg1)); 2618 /* process the response message */ 2619 mpiDeregDevHandleRsp(agRoot, (agsaDeregDevHandleRsp_t *)pMsg1); 2620 break; 2621 } 2622 case OPC_OUB_GET_DEV_HANDLE: 2623 { 2624 SA_DBG3(("mpiParseOBIomb, GET_DEV_HANDLE Response received IOMB=%p\n", pMsg1)); 2625 /* process the response message */ 2626 mpiGetDevHandleRsp(agRoot, (agsaGetDevHandleRsp_t *)pMsg1); 2627 break; 2628 } 2629 case OPC_OUB_SPC_DEV_HANDLE_ARRIV: 2630 { 2631 SA_DBG3(("mpiParseOBIomb, SPC_DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); 2632 /* process the response message */ 2633 mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); 2634 break; 2635 } 2636 case OPC_OUB_DEV_HANDLE_ARRIV: 2637 { 2638 SA_DBG3(("mpiParseOBIomb, DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); 2639 /* process the response message */ 2640 mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); 2641 break; 2642 } 2643 case OPC_OUB_SSP_RECV_EVENT: 2644 { 2645 SA_DBG3(("mpiParseOBIomb, SSP_RECV_EVENT Response received IOMB=%p\n", pMsg1)); 2646 /* process the response message */ 2647 mpiSSPReqReceivedNotify(agRoot, (agsaSSPReqReceivedNotify_t *)pMsg1); 2648 break; 2649 } 2650 case OPC_OUB_DEV_INFO: 2651 { 2652 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2653 SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); 2654 /* process the response message */ 2655 mpiGetDevInfoRsp(agRoot, (agsaGetDevInfoRspV_t *)pMsg1); 2656 break; 2657 } 2658 case OPC_OUB_GET_PHY_PROFILE_RSP: 2659 { 2660 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2661 SA_DBG2(("mpiParseOBIomb, OPC_OUB_GET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); 2662 /* process the response message */ 2663 mpiGetPhyProfileRsp(agRoot, (agsaGetPhyProfileRspV_t *)pMsg1); 2664 break; 2665 } 2666 case OPC_OUB_SET_PHY_PROFILE_RSP: 2667 { 2668 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2669 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); 2670 /* process the response message */ 2671 mpiSetPhyProfileRsp(agRoot, (agsaSetPhyProfileRspV_t *)pMsg1); 2672 break; 2673 } 2674 case OPC_OUB_SPC_DEV_INFO: 2675 { 2676 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2677 SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); 2678 /* process the response message */ 2679 mpiGetDevInfoRspSpc(agRoot, (agsaGetDevInfoRsp_t *)pMsg1); 2680 break; 2681 } 2682 case OPC_OUB_FW_FLASH_UPDATE: 2683 { 2684 SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_FLASH_UPDATE Response received IOMB=%p\n", pMsg1)); 2685 /* process the response message */ 2686 mpiFwFlashUpdateRsp(agRoot, (agsaFwFlashUpdateRsp_t *)pMsg1); 2687 break; 2688 } 2689 case OPC_OUB_FLASH_OP_EXT_RSP: 2690 { 2691 SA_DBG3(("mpiParseOBIomb, OPC_OUB_FLASH_OP_EXT_RSP Response received IOMB=%p\n", pMsg1)); 2692 /* process the response message */ 2693 mpiFwExtFlashUpdateRsp(agRoot, (agsaFwFlashOpExtRsp_t *)pMsg1); 2694 break; 2695 } 2696 #ifdef SPC_ENABLE_PROFILE 2697 case OPC_OUB_FW_PROFILE: 2698 { 2699 SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_PROFILE Response received IOMB=%p\n", pMsg1)); 2700 /* process the response message */ 2701 mpiFwProfileRsp(agRoot, (agsaFwProfileRsp_t *)pMsg1); 2702 break; 2703 } 2704 #endif 2705 case OPC_OUB_SET_NVMD_DATA: 2706 { 2707 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_NVMD_DATA received IOMB=%p\n", pMsg1)); 2708 /* process the response message */ 2709 mpiSetNVMDataRsp(agRoot, (agsaSetNVMDataRsp_t *)pMsg1); 2710 break; 2711 } 2712 case OPC_OUB_GPIO_RESPONSE: 2713 { 2714 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2715 /* process the response message */ 2716 mpiGPIORsp(agRoot, (agsaGPIORsp_t *)pMsg1); 2717 break; 2718 } 2719 case OPC_OUB_GPIO_EVENT: 2720 { 2721 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2722 /* process the response message */ 2723 mpiGPIOEventRsp(agRoot, (agsaGPIOEvent_t *)pMsg1); 2724 break; 2725 } 2726 case OPC_OUB_GENERAL_EVENT: 2727 { 2728 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GENERAL_EVENT Response received IOMB=%p\n", pMsg1)); 2729 /* process the response message */ 2730 mpiGeneralEventRsp(agRoot, (agsaGeneralEventRsp_t *)pMsg1); 2731 break; 2732 } 2733 case OPC_OUB_SAS_DIAG_MODE_START_END: 2734 { 2735 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_MODE_START_END Response received IOMB=%p\n", pMsg1)); 2736 /* process the response message */ 2737 mpiSASDiagStartEndRsp(agRoot, (agsaSASDiagStartEndRsp_t *)pMsg1); 2738 break; 2739 } 2740 case OPC_OUB_SAS_DIAG_EXECUTE: 2741 { 2742 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_EXECUTE_RSP Response received IOMB=%p\n", pMsg1)); 2743 /* process the response message */ 2744 mpiSASDiagExecuteRsp(agRoot, (agsaSASDiagExecuteRsp_t *)pMsg1); 2745 break; 2746 } 2747 case OPC_OUB_GET_TIME_STAMP: 2748 { 2749 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_TIME_STAMP Response received IOMB=%p\n", pMsg1)); 2750 /* process the response message */ 2751 mpiGetTimeStampRsp(agRoot, (agsaGetTimeStampRsp_t *)pMsg1); 2752 break; 2753 } 2754 2755 case OPC_OUB_SPC_SAS_HW_EVENT_ACK: 2756 { 2757 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2758 SA_DBG3(("mpiParseOBIomb,OPC_OUB_SPC_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); 2759 /* process the response message */ 2760 mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); 2761 break; 2762 } 2763 2764 case OPC_OUB_SAS_HW_EVENT_ACK: 2765 { 2766 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2767 SA_DBG1(("mpiParseOBIomb, OPC_OUB_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); 2768 /* process the response message */ 2769 mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); 2770 break; 2771 } 2772 case OPC_OUB_PORT_CONTROL: 2773 { 2774 SA_DBG1(("mpiParseOBIomb, OPC_OUB_PORT_CONTROL Response received IOMB=%p\n", pMsg1)); 2775 /* process the response message */ 2776 mpiPortControlRsp(agRoot, (agsaPortControlRsp_t *)pMsg1); 2777 break; 2778 } 2779 case OPC_OUB_SMP_ABORT_RSP: 2780 { 2781 #ifdef SALL_API_TEST 2782 saRoot->LLCounters.IOCounter.numSMPAbortedCB++; 2783 SA_DBG3(("mpiParseOBIomb, SMP_ABORT Response received IOMB=%p, %d\n", 2784 pMsg1, saRoot->LLCounters.IOCounter.numSMPAbortedCB)); 2785 #else 2786 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SMP_ABORT_RSP Response received IOMB=%p\n", pMsg1)); 2787 #endif 2788 /* process the response message */ 2789 mpiSMPAbortRsp(agRoot, (agsaSMPAbortRsp_t *)pMsg1); 2790 break; 2791 } 2792 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 2793 { 2794 SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEVICE_HANDLE_REMOVAL received IOMB=%p\n", pMsg1)); 2795 /* process the response message */ 2796 mpiDeviceHandleRemoval(agRoot, (agsaDeviceHandleRemoval_t *)pMsg1); 2797 break; 2798 } 2799 case OPC_OUB_SET_DEVICE_STATE: 2800 { 2801 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEVICE_STATE received IOMB=%p\n", pMsg1)); 2802 /* process the response message */ 2803 mpiSetDeviceStateRsp(agRoot, (agsaSetDeviceStateRsp_t *)pMsg1); 2804 break; 2805 } 2806 case OPC_OUB_GET_DEVICE_STATE: 2807 { 2808 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DEVICE_STATE received IOMB=%p\n", pMsg1)); 2809 /* process the response message */ 2810 mpiGetDeviceStateRsp(agRoot, (agsaGetDeviceStateRsp_t *)pMsg1); 2811 break; 2812 } 2813 case OPC_OUB_SET_DEV_INFO: 2814 { 2815 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEV_INFO received IOMB=%p\n", pMsg1)); 2816 /* process the response message */ 2817 mpiSetDevInfoRsp(agRoot, (agsaSetDeviceInfoRsp_t *)pMsg1); 2818 break; 2819 } 2820 case OPC_OUB_SAS_RE_INITIALIZE: 2821 { 2822 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2823 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_RE_INITIALIZE received IOMB=%p\n", pMsg1)); 2824 /* process the response message */ 2825 mpiSasReInitializeRsp(agRoot, (agsaSasReInitializeRsp_t *)pMsg1); 2826 break; 2827 } 2828 2829 case OPC_OUB_SGPIO_RESPONSE: 2830 { 2831 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SGPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2832 /* process the response message */ 2833 mpiSGpioRsp(agRoot, (agsaSGpioRsp_t *)pMsg1); 2834 break; 2835 } 2836 2837 case OPC_OUB_PCIE_DIAG_EXECUTE: 2838 { 2839 SA_DBG3(("mpiParseOBIomb, OPC_OUB_PCIE_DIAG_EXECUTE Response received IOMB=%p\n", pMsg1)); 2840 /* process the response message */ 2841 mpiPCIeDiagExecuteRsp(agRoot, (agsaPCIeDiagExecuteRsp_t *)pMsg1); 2842 break; 2843 } 2844 2845 case OPC_OUB_GET_VIST_CAP_RSP: 2846 { 2847 SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); 2848 /* process the response message */ 2849 mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); 2850 break; 2851 } 2852 case 2104: 2853 { 2854 if(smIS_SPC6V(agRoot)) 2855 { 2856 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DFE_DATA_RSP Response received IOMB=%p\n", pMsg1)); 2857 /* process the response message */ 2858 mpiGetDFEDataRsp(agRoot, (agsaGetDDEFDataRsp_t *)pMsg1); 2859 } 2860 if(smIS_SPC12V(agRoot)) 2861 { 2862 SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); 2863 /* process the response message */ 2864 mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); 2865 } 2866 else 2867 { 2868 SA_DBG1(("mpiParseOBIomb, 2104 Response received IOMB=%p\n", pMsg1)); 2869 /* process the response message */ 2870 } 2871 break; 2872 } 2873 case OPC_OUB_SET_CONTROLLER_CONFIG: 2874 { 2875 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); 2876 mpiSetControllerConfigRsp(agRoot, (agsaSetControllerConfigRsp_t *)pMsg1); 2877 break; 2878 } 2879 case OPC_OUB_GET_CONTROLLER_CONFIG: 2880 { 2881 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); 2882 mpiGetControllerConfigRsp(agRoot, (agsaGetControllerConfigRsp_t *)pMsg1); 2883 break; 2884 } 2885 case OPC_OUB_KEK_MANAGEMENT: 2886 { 2887 SA_DBG3(("mpiParseOBIomb, OPC_OUB_KEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); 2888 mpiKekManagementRsp(agRoot, (agsaKekManagementRsp_t *)pMsg1); 2889 break; 2890 } 2891 case OPC_OUB_DEK_MANAGEMENT: 2892 { 2893 SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); 2894 mpiDekManagementRsp(agRoot, (agsaDekManagementRsp_t *)pMsg1); 2895 break; 2896 } 2897 case OPC_OUB_OPR_MGMT: 2898 { 2899 SA_DBG1(("mpiParseOBIomb, OPC_OUB_OPR_MGMT Response received IOMB=%p\n", pMsg1)); 2900 mpiOperatorManagementRsp(agRoot, (agsaOperatorMangmenRsp_t *)pMsg1); 2901 break; 2902 } 2903 case OPC_OUB_ENC_TEST_EXECUTE: 2904 { 2905 SA_DBG1(("mpiParseOBIomb, OPC_OUB_ENC_TEST_EXECUTE Response received IOMB=%p\n", pMsg1)); 2906 mpiBistRsp(agRoot, (agsaEncryptBistRsp_t *)pMsg1); 2907 break; 2908 } 2909 case OPC_OUB_SET_OPERATOR: 2910 { 2911 SA_DBG1(("mpiParseOBIomb, OPC_OUB_SET_OPERATOR Response received IOMB=%p\n", pMsg1)); 2912 mpiSetOperatorRsp(agRoot, (agsaSetOperatorRsp_t *)pMsg1); 2913 break; 2914 } 2915 case OPC_OUB_GET_OPERATOR: 2916 { 2917 SA_DBG1(("mpiParseOBIomb, OPC_OUB_GET_OPERATOR Response received IOMB=%p\n", pMsg1)); 2918 mpiGetOperatorRsp(agRoot, (agsaGetOperatorRsp_t *)pMsg1); 2919 break; 2920 } 2921 case OPC_OUB_DIF_ENC_OFFLOAD_RSP: 2922 { 2923 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2924 SA_DBG1(("mpiParseOBIomb, OPC_OUB_DIF_ENC_OFFLOAD_RSP Response received IOMB=%p\n", pMsg1)); 2925 /* process the response message */ 2926 mpiDifEncOffloadRsp(agRoot, (agsaDifEncOffloadRspV_t *)pMsg1); 2927 break; 2928 } 2929 default: 2930 { 2931 #ifdef SALL_API_TEST 2932 saRoot->LLCounters.IOCounter.numUNKNWRespIOMB++; 2933 SA_DBG1(("mpiParseOBIomb, UnKnown Response received IOMB=%p, %d\n", 2934 pMsg1, saRoot->LLCounters.IOCounter.numUNKNWRespIOMB)); 2935 #else 2936 SA_DBG1(("mpiParseOBIomb, Unknown IOMB Response received opcode 0x%X IOMB=%p\n",opcode, pMsg1)); 2937 #endif 2938 break; 2939 } 2940 } /* switch */ 2941 2942 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2f"); 2943 2944 return ret; 2945 2946 } 2947 2948 2949 /******************************************************************************/ 2950 /*! \brief SPC MPI SATA Completion 2951 * 2952 * This function handles the SATA completion. 2953 * 2954 * \param agRoot Handles for this instance of SAS/SATA LLL 2955 * \param pIomb1 Pointer of Message1 2956 * \param bc buffer count 2957 * 2958 * \return The read value 2959 * 2960 */ 2961 /*******************************************************************************/ 2962 GLOBAL FORCEINLINE 2963 bit32 mpiSATACompletion( 2964 agsaRoot_t *agRoot, 2965 bit32 *pIomb1 2966 ) 2967 { 2968 bit32 ret = AGSA_RC_SUCCESS; 2969 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2970 bit32 status; 2971 bit32 tag; 2972 bit32 param; 2973 agsaIORequestDesc_t *pRequest; 2974 bit32 *agFirstDword; 2975 bit32 *pResp; 2976 2977 smTraceFuncEnter(hpDBG_VERY_LOUD,"2s"); 2978 2979 OSSA_READ_LE_32(AGROOT, &tag, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, tag)) ; 2980 OSSA_READ_LE_32(AGROOT, &status, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, status)) ; 2981 OSSA_READ_LE_32(AGROOT, &param, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, param)) ; 2982 2983 SA_DBG3(("mpiSATACompletion: start, HTAG=0x%x\n", tag)); 2984 2985 /* get IOrequest from IOMap */ 2986 pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; 2987 SA_ASSERT((pRequest), "pRequest"); 2988 2989 if(agNULL == pRequest) 2990 { 2991 SA_DBG1(("mpiSATACompletion: agNULL == pRequest tag 0x%X status 0x%X\n",tag, status )); 2992 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2s"); 2993 return AGSA_RC_FAILURE; 2994 } 2995 2996 SA_ASSERT((pRequest->valid), "pRequest->valid"); 2997 if(!pRequest->valid) 2998 { 2999 SA_DBG1(("mpiSATACompletion: not valid IOMB tag=0x%x status=0x%x param=0x%x Device =0x%x\n", tag, status, param, 3000 pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); 3001 } 3002 3003 switch (status) 3004 { 3005 case OSSA_IO_SUCCESS: 3006 { 3007 SA_DBG3(("mpiSATACompletion: OSSA_IO_SUCCESS, param=0x%x\n", param)); 3008 if (!param) 3009 { 3010 /* SATA request completion */ 3011 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); 3012 } 3013 else 3014 { 3015 /* param number bytes of SATA Rsp */ 3016 agFirstDword = &pIomb1[3]; 3017 pResp = &pIomb1[4]; 3018 3019 /* CB function to the up layer */ 3020 /* Response Length not include firstDW */ 3021 saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3022 SA_DBG2(("mpiSATACompletion: param 0x%x agFirstDwordResp 0x%x Resp 0x%x tag 0x%x\n",param,*agFirstDword,*pResp ,tag)); 3023 siEventSATAResponseWtDataRcvd(agRoot, pRequest, agFirstDword, pResp, (param - 4)); 3024 } 3025 3026 break; 3027 } 3028 case OSSA_IO_ABORTED: 3029 { 3030 SA_DBG2(("mpiSATACompletion: OSSA_IO_ABORTED tag 0x%X\n", tag)); 3031 saRoot->IoErrorCount.agOSSA_IO_ABORTED++; 3032 siAbnormal(agRoot, pRequest, status, param, 0); 3033 break; 3034 } 3035 case OSSA_IO_UNDERFLOW: 3036 { 3037 /* SATA Completion with error */ 3038 SA_DBG1(("mpiSATACompletion, OSSA_IO_UNDERFLOW tag 0x%X\n", tag)); 3039 /*underflow means underrun, treat it as success*/ 3040 saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++; 3041 siAbnormal(agRoot, pRequest, status, param, 0); 3042 break; 3043 } 3044 case OSSA_IO_NO_DEVICE: 3045 { 3046 SA_DBG1(("mpiSATACompletion, OSSA_IO_NO_DEVICE tag 0x%X\n", tag)); 3047 saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; 3048 siAbnormal(agRoot, pRequest, status, 0, 0); 3049 break; 3050 } 3051 case OSSA_IO_XFER_ERROR_BREAK: 3052 { 3053 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_BREAK SPC tag 0x%X\n", tag)); 3054 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; 3055 siAbnormal(agRoot, pRequest, status, 0, 0); 3056 break; 3057 } 3058 case OSSA_IO_XFER_ERROR_PHY_NOT_READY: 3059 { 3060 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%X\n", tag)); 3061 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; 3062 siAbnormal(agRoot, pRequest, status, 0, 0); 3063 break; 3064 } 3065 case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3066 { 3067 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%X\n", tag)); 3068 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; 3069 siAbnormal(agRoot, pRequest, status, 0, 0); 3070 break; 3071 } 3072 case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3073 { 3074 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%X\n", tag)); 3075 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; 3076 siAbnormal(agRoot, pRequest, status, 0, 0); 3077 break; 3078 } 3079 case OSSA_IO_OPEN_CNX_ERROR_BREAK: 3080 { 3081 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BREAK SPC tag 0x%X\n", tag)); 3082 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; 3083 siAbnormal(agRoot, pRequest, status, 0, 0); 3084 break; 3085 } 3086 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3087 { 3088 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%X\n", tag)); 3089 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; 3090 siAbnormal(agRoot, pRequest, status, 0, 0); 3091 break; 3092 } 3093 case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3094 { 3095 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%X\n", tag)); 3096 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; 3097 siAbnormal(agRoot, pRequest, status, 0, 0); 3098 break; 3099 } 3100 case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3101 { 3102 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%X\n", tag)); 3103 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; 3104 siAbnormal(agRoot, pRequest, status, 0, 0); 3105 break; 3106 } 3107 case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 3108 { 3109 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY tag 0x%X\n", tag)); 3110 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY++; 3111 siAbnormal(agRoot, pRequest, status, 0, 0); 3112 break; 3113 } 3114 case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3115 { 3116 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%X\n", tag)); 3117 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; 3118 siAbnormal(agRoot, pRequest, status, 0, 0); 3119 break; 3120 } 3121 case OSSA_IO_XFER_ERROR_NAK_RECEIVED: 3122 { 3123 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%X\n", tag)); 3124 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; 3125 siAbnormal(agRoot, pRequest, status, 0, 0); 3126 break; 3127 } 3128 case OSSA_IO_XFER_ERROR_DMA: 3129 { 3130 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_DMA tag 0x%X\n", tag)); 3131 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; 3132 siAbnormal(agRoot, pRequest, status, 0, 0); 3133 break; 3134 } 3135 case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: 3136 { 3137 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT tag 0x%X\n", tag)); 3138 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT++; 3139 siAbnormal(agRoot, pRequest, status, 0, 0); 3140 break; 3141 } 3142 case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: 3143 { 3144 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE tag 0x%X\n", tag)); 3145 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE++; 3146 siAbnormal(agRoot, pRequest, status, 0, 0); 3147 break; 3148 } 3149 case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: 3150 { 3151 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%X\n", tag)); 3152 saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; 3153 siAbnormal(agRoot, pRequest, status, 0, 0); 3154 break; 3155 } 3156 case OSSA_IO_PORT_IN_RESET: 3157 { 3158 SA_DBG1(("mpiSATACompletion: OSSA_IO_PORT_IN_RESET tag 0x%X\n", tag)); 3159 saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; 3160 siAbnormal(agRoot, pRequest, status, 0, 0); 3161 break; 3162 } 3163 case OSSA_IO_DS_NON_OPERATIONAL: 3164 { 3165 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%X\n", tag)); 3166 saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; 3167 siAbnormal(agRoot, pRequest, status, 0, 0); 3168 break; 3169 } 3170 case OSSA_IO_DS_IN_RECOVERY: 3171 { 3172 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%X\n", tag)); 3173 saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; 3174 siAbnormal(agRoot, pRequest, status, 0, 0); 3175 break; 3176 } 3177 case OSSA_IO_DS_IN_ERROR: 3178 { 3179 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_ERROR tag 0x%X\n", tag)); 3180 saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; 3181 siAbnormal(agRoot, pRequest, status, 0, 0); 3182 break; 3183 } 3184 3185 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3186 { 3187 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%X\n", tag)); 3188 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; 3189 siAbnormal(agRoot, pRequest, status, 0, 0); 3190 break; 3191 } 3192 case OSSA_IO_ABORT_IN_PROGRESS: 3193 { 3194 SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%X\n", tag)); 3195 saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; 3196 siAbnormal(agRoot, pRequest, status, 0, 0); 3197 break; 3198 } 3199 case OSSA_IO_ABORT_DELAYED: 3200 { 3201 SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_DELAYED tag 0x%X\n", tag)); 3202 saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; 3203 siAbnormal(agRoot, pRequest, status, 0, 0); 3204 break; 3205 } 3206 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: 3207 { 3208 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%X\n", tag)); 3209 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; 3210 siAbnormal(agRoot, pRequest, status, 0, 0); 3211 break; 3212 } 3213 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3214 { 3215 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x\n", tag)); 3216 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; 3217 siAbnormal(agRoot, pRequest, status, 0, 0); 3218 break; 3219 } 3220 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3221 { 3222 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x\n", tag)); 3223 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; 3224 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3225 break; 3226 } 3227 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3228 { 3229 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x\n", tag)); 3230 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; 3231 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3232 break; 3233 } 3234 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3235 { 3236 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x\n", tag)); 3237 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; 3238 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3239 break; 3240 } 3241 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3242 { 3243 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x\n", tag)); 3244 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; 3245 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3246 break; 3247 } 3248 case OSSA_IO_DS_INVALID: 3249 { 3250 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_INVALID tag 0x%X\n", tag)); 3251 saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; 3252 siAbnormal(agRoot, pRequest, status, 0, 0); 3253 break; 3254 } 3255 case OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR: 3256 { 3257 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR tag 0x%X\n", tag)); 3258 saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR++; 3259 siAbnormal(agRoot, pRequest, status, 0, 0); 3260 break; 3261 } 3262 case OSSA_MPI_IO_RQE_BUSY_FULL: 3263 { 3264 SA_DBG1(("mpiSATACompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%X\n", tag)); 3265 saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; 3266 siAbnormal(agRoot, pRequest, status, 0, 0); 3267 break; 3268 } 3269 #ifdef REMOVED 3270 case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: 3271 { 3272 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x\n", tag)); 3273 saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; 3274 siAbnormal(agRoot, pRequest, status, 0, 0); 3275 break; 3276 } 3277 #endif 3278 case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: 3279 { 3280 SA_DBG1(("mpiSATACompletion: OPC_OUB_SATA_COMP:OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE \n")); 3281 saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; 3282 siAbnormal(agRoot, pRequest, status, 0, 0); 3283 break; 3284 } 3285 case OSSA_MPI_ERR_ATAPI_DEVICE_BUSY: 3286 { 3287 SA_DBG1(("mpiSATACompletion: OSSA_MPI_ERR_ATAPI_DEVICE_BUSY tag 0x%X\n", tag)); 3288 saRoot->IoErrorCount.agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY++; 3289 siAbnormal(agRoot, pRequest, status, param, 0 ); 3290 break; 3291 } 3292 case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: 3293 { 3294 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%X\n", tag)); 3295 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3296 siAbnormal(agRoot, pRequest, status, 0, 0); 3297 break; 3298 } 3299 case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: 3300 { 3301 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%X\n", tag)); 3302 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3303 siAbnormal(agRoot, pRequest, status, 0, 0); 3304 break; 3305 } 3306 case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: 3307 { 3308 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%X\n", tag)); 3309 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; 3310 siAbnormal(agRoot, pRequest, status, 0, 0); 3311 break; 3312 } 3313 case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: 3314 { 3315 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%X\n", tag)); 3316 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; 3317 siAbnormal(agRoot, pRequest, status, 0, 0); 3318 break; 3319 } 3320 case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: 3321 { 3322 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%X\n", tag)); 3323 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; 3324 siAbnormal(agRoot, pRequest, status, 0, 0); 3325 break; 3326 } 3327 3328 case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: 3329 { 3330 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%X\n", tag)); 3331 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; 3332 siAbnormal(agRoot, pRequest, status, 0, 0); 3333 break; 3334 } 3335 case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: 3336 { 3337 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%X\n", tag)); 3338 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3339 siAbnormal(agRoot, pRequest, status, 0, 0); 3340 break; 3341 } 3342 case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: 3343 { 3344 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%X\n", tag)); 3345 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3346 siAbnormal(agRoot, pRequest, status, 0, 0); 3347 break; 3348 } 3349 3350 default: 3351 { 3352 SA_DBG1(("mpiSATACompletion: Unknown status 0x%x tag 0x%x\n", status, tag)); 3353 saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; 3354 siAbnormal(agRoot, pRequest, status, param, 0); 3355 break; 3356 } 3357 } 3358 3359 /* The HTag should equal to the IOMB tag */ 3360 if (pRequest->HTag != tag) 3361 { 3362 SA_DBG1(("mpiSATACompletion: Error Htag %d not equal IOMBtag %d\n", pRequest->HTag, tag)); 3363 } 3364 3365 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2s"); 3366 return ret; 3367 } 3368 3369 /******************************************************************************/ 3370 /*! \brief SPC MPI SSP Completion 3371 * 3372 * This function handles the SSP completion. 3373 * 3374 * \param agRoot Handles for this instance of SAS/SATA LLL 3375 * \param pIomb1 Pointer of Message1 3376 * \param bc buffer count 3377 * 3378 * \return The read value 3379 * 3380 */ 3381 /*******************************************************************************/ 3382 GLOBAL FORCEINLINE 3383 bit32 mpiSSPCompletion( 3384 agsaRoot_t *agRoot, 3385 bit32 *pIomb1 3386 ) 3387 { 3388 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 3389 agsaSSPCompletionRsp_t *pIomb = (agsaSSPCompletionRsp_t *)pIomb1; 3390 agsaIORequestDesc_t *pRequest = agNULL; 3391 agsaSSPResponseInfoUnit_t *pRespIU = agNULL; 3392 bit32 tag = 0; 3393 bit32 sspTag = 0; 3394 bit32 status, param = 0; 3395 bit32 ret = AGSA_RC_SUCCESS; 3396 3397 smTraceFuncEnter(hpDBG_VERY_LOUD, "5A"); 3398 3399 /* get Tag */ 3400 OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, tag)); 3401 OSSA_READ_LE_32(agRoot, &status, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, status)); 3402 OSSA_READ_LE_32(agRoot, &param, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, param)); 3403 OSSA_READ_LE_32(agRoot, &sspTag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, SSPTag)); 3404 /* get SSP_START IOrequest from IOMap */ 3405 pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 3406 SA_ASSERT((pRequest), "pRequest"); 3407 3408 if(pRequest == agNULL) 3409 { 3410 SA_DBG1(("mpiSSPCompletion,AGSA_RC_FAILURE SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, status, param, sspTag)); 3411 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5A"); 3412 return(AGSA_RC_FAILURE); 3413 } 3414 SA_ASSERT((pRequest->valid), "pRequest->valid"); 3415 3416 if(!pRequest->valid) 3417 { 3418 SA_DBG1(("mpiSSPCompletion, SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x Device =0x%x\n", tag, status, param, sspTag, 3419 pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); 3420 } 3421 3422 switch (status) 3423 { 3424 case OSSA_IO_SUCCESS: 3425 { 3426 if (!param) 3427 { 3428 /* Completion of SSP without Response Data */ 3429 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); 3430 } 3431 else 3432 { 3433 /* Get SSP Response with Response Data */ 3434 pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); 3435 if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || 3436 pRespIU->status == 0x30 || pRespIU->status == 0x40 ) 3437 { 3438 /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ 3439 saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3440 SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); 3441 } 3442 siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); 3443 } 3444 3445 break; 3446 } 3447 3448 case OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME: 3449 { 3450 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3451 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME++; 3452 /* Get SSP Response with Response Data */ 3453 pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); 3454 if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || 3455 pRespIU->status == 0x30 || pRespIU->status == 0x40 ) 3456 { 3457 /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ 3458 saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3459 SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); 3460 } 3461 siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); 3462 3463 break; 3464 } 3465 3466 case OSSA_IO_ABORTED: 3467 { 3468 #ifdef SALL_API_TEST 3469 saRoot->LLCounters.IOCounter.numSSPAborted++; 3470 SA_DBG3(("mpiSSPCompletion, OSSA_IO_ABORTED Response received IOMB=%p %d\n", 3471 pIomb1, saRoot->LLCounters.IOCounter.numSSPAborted)); 3472 #endif 3473 SA_DBG2(("mpiSSPCompletion, OSSA_IO_ABORTED IOMB tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3474 saRoot->IoErrorCount.agOSSA_IO_ABORTED++; 3475 /* SSP Abort CB */ 3476 siAbnormal(agRoot, pRequest, status, param, sspTag); 3477 break; 3478 } 3479 case OSSA_IO_UNDERFLOW: 3480 { 3481 /* SSP Completion with error */ 3482 SA_DBG2(("mpiSSPCompletion, OSSA_IO_UNDERFLOW tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3483 /*saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++;*/ 3484 siAbnormal(agRoot, pRequest, status, param, sspTag); 3485 break; 3486 } 3487 case OSSA_IO_NO_DEVICE: 3488 { 3489 SA_DBG1(("mpiSSPCompletion: OSSA_IO_NO_DEVICE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3490 saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; 3491 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3492 break; 3493 } 3494 case OSSA_IO_XFER_ERROR_BREAK: 3495 { 3496 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3497 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; 3498 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3499 break; 3500 } 3501 case OSSA_IO_XFER_ERROR_PHY_NOT_READY: 3502 { 3503 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3504 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; 3505 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3506 break; 3507 } 3508 case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3509 { 3510 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3511 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; 3512 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3513 break; 3514 } 3515 case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3516 { 3517 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; 3518 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3519 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3520 break; 3521 } 3522 case OSSA_IO_OPEN_CNX_ERROR_BREAK: 3523 { 3524 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3525 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; 3526 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3527 break; 3528 } 3529 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3530 { 3531 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3532 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; 3533 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3534 break; 3535 } 3536 case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3537 { 3538 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3539 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; 3540 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3541 break; 3542 } 3543 case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3544 { 3545 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3546 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; 3547 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3548 break; 3549 } 3550 case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3551 { 3552 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3553 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; 3554 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3555 break; 3556 } 3557 case OSSA_IO_XFER_ERROR_NAK_RECEIVED: 3558 { 3559 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3560 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; 3561 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3562 break; 3563 } 3564 case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: 3565 { 3566 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3567 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT++; 3568 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3569 break; 3570 } 3571 case OSSA_IO_XFER_ERROR_DMA: 3572 { 3573 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DMA tag 0x%x ssptag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3574 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; 3575 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3576 break; 3577 } 3578 case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: 3579 { 3580 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3581 saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; 3582 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3583 break; 3584 } 3585 case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: 3586 { 3587 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3588 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE++; 3589 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3590 break; 3591 } 3592 case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: 3593 { 3594 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3595 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH++; 3596 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3597 break; 3598 } 3599 case OSSA_IO_PORT_IN_RESET: 3600 { 3601 SA_DBG1(("mpiSSPCompletion: OSSA_IO_PORT_IN_RESET tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3602 saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; 3603 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3604 break; 3605 } 3606 case OSSA_IO_DS_NON_OPERATIONAL: 3607 { 3608 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3609 saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; 3610 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3611 break; 3612 } 3613 case OSSA_IO_DS_IN_RECOVERY: 3614 { 3615 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3616 saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; 3617 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3618 break; 3619 } 3620 case OSSA_IO_TM_TAG_NOT_FOUND: 3621 { 3622 SA_DBG1(("mpiSSPCompletion: OSSA_IO_TM_TAG_NOT_FOUND tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3623 saRoot->IoErrorCount.agOSSA_IO_TM_TAG_NOT_FOUND++; 3624 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3625 break; 3626 } 3627 case OSSA_IO_XFER_PIO_SETUP_ERROR: 3628 { 3629 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_PIO_SETUP_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3630 saRoot->IoErrorCount.agOSSA_IO_XFER_PIO_SETUP_ERROR++; 3631 /* not allowed case. Therefore, return failed status */ 3632 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3633 break; 3634 } 3635 case OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR: 3636 { 3637 SA_DBG1(("mpiSSPCompletion: OSSA_IO_SSP_IU_ZERO_LEN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3638 saRoot->IoErrorCount.agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR++; 3639 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3640 break; 3641 } 3642 case OSSA_IO_DS_IN_ERROR: 3643 { 3644 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3645 saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; 3646 /* not allowed case. Therefore, return failed status */ 3647 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3648 break; 3649 } 3650 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3651 { 3652 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3653 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; 3654 /* not allowed case. Therefore, return failed status */ 3655 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3656 break; 3657 } 3658 case OSSA_IO_ABORT_IN_PROGRESS: 3659 { 3660 SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3661 saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; 3662 /* not allowed case. Therefore, return failed status */ 3663 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3664 break; 3665 } 3666 case OSSA_IO_ABORT_DELAYED: 3667 { 3668 SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_DELAYED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3669 saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; 3670 /* not allowed case. Therefore, return failed status */ 3671 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3672 break; 3673 } 3674 case OSSA_IO_INVALID_LENGTH: 3675 { 3676 SA_DBG1(("mpiSSPCompletion: OSSA_IO_INVALID_LENGTH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3677 saRoot->IoErrorCount.agOSSA_IO_INVALID_LENGTH++; 3678 /* not allowed case. Therefore, return failed status */ 3679 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3680 break; 3681 } 3682 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: 3683 { 3684 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3685 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; 3686 /* not allowed case. Therefore, return failed status */ 3687 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3688 break; 3689 } 3690 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3691 { 3692 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x ssptag = 0x%x\n", tag, sspTag)); 3693 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; 3694 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3695 break; 3696 } 3697 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3698 { 3699 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3700 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; 3701 siAbnormal(agRoot, pRequest, status, param, sspTag); 3702 break; 3703 } 3704 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3705 { 3706 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3707 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; 3708 siAbnormal(agRoot, pRequest, status, param, sspTag); 3709 break; 3710 } 3711 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3712 { 3713 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3714 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; 3715 siAbnormal(agRoot, pRequest, status, param, sspTag); 3716 break; 3717 } 3718 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3719 { 3720 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3721 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; 3722 siAbnormal(agRoot, pRequest, status, param, sspTag); 3723 break; 3724 } 3725 case OSSA_IO_DS_INVALID: 3726 { 3727 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3728 saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; 3729 siAbnormal(agRoot, pRequest, status, param, sspTag); 3730 break; 3731 } 3732 case OSSA_MPI_IO_RQE_BUSY_FULL: 3733 { 3734 SA_DBG1(("mpiSSPCompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3735 saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; 3736 siAbnormal(agRoot, pRequest, status, param, sspTag); 3737 break; 3738 } 3739 case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: 3740 { 3741 SA_DBG1(("mpiSSPCompletion: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3742 saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; 3743 siAbnormal(agRoot, pRequest, status, param, sspTag); 3744 break; 3745 } 3746 case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: 3747 { 3748 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3749 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3750 siAbnormal(agRoot, pRequest, status, param, sspTag); 3751 break; 3752 } 3753 case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: 3754 { 3755 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3756 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; 3757 siAbnormal(agRoot, pRequest, status, param, sspTag); 3758 break; 3759 } 3760 case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: 3761 { 3762 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3763 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID++; 3764 siAbnormal(agRoot, pRequest, status, param, sspTag); 3765 break; 3766 } 3767 case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: 3768 { 3769 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3770 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; 3771 siAbnormal(agRoot, pRequest, status, param, sspTag); 3772 break; 3773 } 3774 case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: 3775 { 3776 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3777 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; 3778 siAbnormal(agRoot, pRequest, status, param, sspTag); 3779 break; 3780 } 3781 case OSSA_IO_XFR_ERROR_INTERNAL_RAM: 3782 { 3783 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INTERNAL_RAM tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3784 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INTERNAL_RAM++; 3785 siAbnormal(agRoot, pRequest, status, param, sspTag); 3786 break; 3787 } 3788 case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: 3789 { 3790 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3791 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3792 siAbnormal(agRoot, pRequest, status, param, sspTag); 3793 break; 3794 } 3795 case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: 3796 { 3797 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3798 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE++; 3799 siAbnormal(agRoot, pRequest, status, param, sspTag); 3800 break; 3801 } 3802 #ifdef SA_TESTBASE_EXTRA 3803 /* TestBase */ 3804 case OSSA_IO_HOST_BST_INVALID: 3805 { 3806 SA_DBG1(("mpiParseOBIomb, OPC_OUB_SSP_COMP: OSSA_IO_HOST_BST_INVALID 0x%x\n", status)); 3807 siAbnormal(agRoot, pRequest, status, param, sspTag); 3808 break; 3809 } 3810 #endif /* SA_TESTBASE_EXTRA */ 3811 case OSSA_IO_XFR_ERROR_DIF_MISMATCH: 3812 { 3813 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3814 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_MISMATCH++; 3815 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3816 break; 3817 } 3818 case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: 3819 { 3820 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3821 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH++; 3822 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3823 break; 3824 } 3825 case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: 3826 { 3827 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3828 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH++; 3829 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3830 break; 3831 } 3832 case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: 3833 { 3834 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3835 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH++; 3836 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3837 break; 3838 } 3839 case OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR: 3840 { 3841 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3842 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR++; 3843 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3844 break; 3845 } 3846 case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: 3847 { 3848 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3849 saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; 3850 siAbnormal(agRoot, pRequest, status, param, sspTag); 3851 break; 3852 } 3853 case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: 3854 { 3855 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3856 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; 3857 siAbnormal(agRoot, pRequest, status, param, sspTag); 3858 break; 3859 } 3860 default: 3861 { 3862 SA_DBG1(("mpiSSPCompletion: Unknown tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3863 /* not allowed case. Therefore, return failed status */ 3864 saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; 3865 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3866 break; 3867 } 3868 } 3869 3870 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5A"); 3871 return ret; 3872 }

Cache object: 06171c7f51f9e23c8c47be32a6786030

FreeBSD/Linux Kernel Cross Reference sys/dev/pms/RefTisa/sallsdk/spc/saint.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/pms/RefTisa/sallsdk/spc/saint.c