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sys/dev/pms/RefTisa/sallsdk/spc/spcdefs.h
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1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * $FreeBSD$ 22 * 23 ********************************************************************************/ 24 /*******************************************************************************/ 25 /*! \file spcdefs.h 26 * \brief The file defines the MPI Application Programming Interface (API) 27 * 28 * The file defines the MPI Application Programming Interfacde (API) 29 * 30 */ 31 /*******************************************************************************/ 32 #ifndef __SPCDEFS_H__ 33 #define __SPCDEFS_H__ 34 35 /*******************************************************************************/ 36 /*******************************************************************************/ 37 /* CONSTANTS */ 38 /*******************************************************************************/ 39 /*******************************************************************************/ 40 /*******************************************************************************/ 41 /* MSGU CONFIGURATION TABLE */ 42 /*******************************************************************************/ 43 #define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */ 44 #define SPC_MSGU_CFG_TABLE_RESET 0x002 /* Inbound doorbell bit1 */ 45 #define SPC_MSGU_CFG_TABLE_FREEZE 0x004 /* Inbound doorbell bit2 */ 46 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x008 /* Inbound doorbell bit4 */ 47 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080 /* Inbound doorbell bit7 SPCV */ 48 #define SPCV_MSGU_HALT_CPUS 0x100 /* Inbound doorbell bit8 SPCV */ 49 50 /***** Notes *****/ 51 /* The firmware side is using Little Endian (MIPs). */ 52 /* So anything sending or receiving from FW must be in Little Endian */ 53 /*******************************************************************************/ 54 /** \struct mpiMsgHeader_s 55 * \brief MPI message header 56 * 57 * The mpiMsgHeader_s defines the fields in the header of every message 58 */ 59 /*******************************************************************************/ 60 /* This structire defines the fields in the header of every message */ 61 62 63 struct mpiMsgHeader_s 64 { 65 bit32 Header; /* Bits [11:0] - Message operation code */ 66 /* Bits [15:12] - Message Category */ 67 /* Bits [21:16] - Outboundqueue ID for the operation completion message */ 68 /* Bits [23:22] - Reserved */ 69 /* Bits [28:24] - Buffer Count, indicates how many buffer are allocated for the massage */ 70 /* Bits [30:29] - Reserved */ 71 /* Bits [31] - Message Valid bit */ 72 }; 73 74 typedef struct mpiMsgHeader_s mpiMsgHeader_t; 75 76 #define V_BIT 0x1 77 78 #define V_MASK 0x1 79 #define BC_MASK 0x1F 80 #define OBID_MASK 0x3F 81 #define CAT_MASK 0x0F 82 #define OPCODE_MASK 0xFFF 83 #define HEADER_V_MASK 0x80000000 84 #define HEADER_BC_MASK 0x1f000000 85 86 #ifndef SPC_CONFIG 87 /*******************************************************************************/ 88 /** \struct spc_ConfigMainDescriptor_s 89 * \brief This structure is used to configure main part of Configuration Table 90 * 91 * This structure specifies all required attributes to configuration table 92 */ 93 /*******************************************************************************/ 94 /* new MPI configuration main table */ 95 struct spc_configMainDescriptor_s 96 { 97 bit8 Signature[4]; /**< DW0 signature - Indicate coherent table */ 98 bit32 InterfaceRev; /**< DW1 Revsion of Interface */ 99 bit32 FWRevision; /**< DW2 Revsion of FW */ 100 bit32 MaxOutstandingIO; /**< DW3 Max outstanding IO */ 101 bit32 MDevMaxSGL; /**< DW4 Maximum SGL elements & Max Devices */ 102 /* bit0-15 Maximum SGL */ 103 /* bit16-31 Maximum Devices */ 104 bit32 ContrlCapFlag; /**< DW5 Controller Capability */ 105 /* bit0-7 Max number of inbound queue */ 106 /* bit8-15 Max number of outbound queue */ 107 /* bit16 high priority of inbound queue is supported */ 108 /* bit17 reserved */ 109 /* bit18 interrupt coalescing is supported, SPCV-reserved */ 110 /* bit19-24 Maximum number of valid phys */ 111 /* bit25-31 SAS Revision SPecification */ 112 bit32 GSTOffset; /**< DW6 General Status Table */ 113 bit32 inboundQueueOffset; /**< DW7 inbound configuration table offset */ 114 /* bit23-0 inbound queue table offset */ 115 /* bit31-24 entry size, new in SPCV */ 116 bit32 outboundQueueOffset; /**< DW8 outbound configuration table offset */ 117 /* bit23-0 outbound queue table offset */ 118 /* bit31-24 entry size, new in SPCV */ 119 bit32 iQNPPD_HPPD_GEvent; /**< DW9 inbound Queue Process depth and General Event */ 120 /* bit0-7 inbound normal priority process depth */ 121 /* bit8-15 inbound high priority process depth */ 122 /* bit16-23 OQ number to receive GENERAL_EVENT Notification */ 123 /* bit24-31 OQ number to receive DEVICE_HANDLE_REMOVAL Notification */ 124 bit32 outboundHWEventPID0_3; /**< DWA outbound HW event for PortId 0 to 3, SPCV-reserved */ 125 /* bit0-7 outbound queue number of SAS_HW event for PhyId 0 */ 126 /* bit8-15 outbound queue number of SAS_HW event for PhyId 1 */ 127 /* bit16-23 outbound queue number of SAS_HW event for PhyId 2 */ 128 /* bit24-31 outbound queue number of SAS_HW event for PhyId 3 */ 129 bit32 outboundHWEventPID4_7; /**< DWB outbound HW event for PortId 4 to 7, SPCV-reserved */ 130 /* bit0-7 outbound queue number of SAS_HW event for PhyId 4 */ 131 /* bit8-15 outbound queue number of SAS_HW event for PhyId 5 */ 132 /* bit16-23 outbound queue number of SAS_HW event for PhyId 6 */ 133 /* bit24-31 outbound queue number of SAS_HW event for PhyId 7 */ 134 bit32 outboundNCQEventPID0_3; /**< DWC outbound NCQ event for PortId 0 to 3, SPCV-reserved */ 135 /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 0 */ 136 /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 1 */ 137 /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 2 */ 138 /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */ 139 bit32 outboundNCQEventPID4_7; /**< DWD outbound NCQ event for PortId 4 to 7, SPCV-reserved*/ 140 /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 4 */ 141 /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 5 */ 142 /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 6 */ 143 /* bit24-31 outbound queue number of SATA_NCQ event for PhyId 7 */ 144 bit32 outboundTargetITNexusEventPID0_3; /**< DWE outbound target ITNexus Event for PortId 0 to 3, SPCV-reserved */ 145 /* bit0-7 outbound queue number of ITNexus event for PhyId 0 */ 146 /* bit8-15 outbound queue number of ITNexus event for PhyId 1 */ 147 /* bit16-23 outbound queue number of ITNexus event for PhyId 2 */ 148 /* bit24-31 outbound queue number of ITNexus event for PhyId 3 */ 149 bit32 outboundTargetITNexusEventPID4_7; /**< DWF outbound target ITNexus Event for PortId 4 to 7, SPCV-reserved */ 150 /* bit0-7 outbound queue number of ITNexus event for PhyId 4 */ 151 /* bit8-15 outbound queue number of ITNexus event for PhyId 5 */ 152 /* bit16-23 outbound queue number of ITNexus event for PhyId 6 */ 153 /* bit24-31 outbound queue number of ITNexus event for PhyId 7 */ 154 bit32 outboundTargetSSPEventPID0_3; /**< DW10 outbound target SSP event for PordId 0 to 3, SPCV-reserved */ 155 /* bit0-7 outbound queue number of SSP event for PhyId 0 */ 156 /* bit8-15 outbound queue number of SSP event for PhyId 1 */ 157 /* bit16-23 outbound queue number of SSP event for PhyId 2 */ 158 /* bit24-31 outbound queue number of SSP event for PhyId 3 */ 159 bit32 outboundTargetSSPEventPID4_7; /**< DW11 outbound target SSP event for PordId 4 to 7, SPCV-reserved */ 160 /* bit0-7 outbound queue number of SSP event for PhyId 4 */ 161 /* bit8-15 outbound queue number of SSP event for PhyId 5 */ 162 /* bit16-23 outbound queue number of SSP event for PhyId 6 */ 163 /* bit24-31 outbound queue number of SSP event for PhyId 7 */ 164 bit32 ioAbortDelay; /**< DW12 IO Abort Delay (bit15:0) MPI_TABLE_CHANGE*/ 165 bit32 custset; /**< DW13 custset */ 166 bit32 upperEventLogAddress; /**< DW14 Upper physical MSGU Event log address */ 167 bit32 lowerEventLogAddress; /**< DW15 Lower physical MSGU Event log address */ 168 bit32 eventLogSize; /**< DW16 Size of MSGU Event log, 0 means log disable */ 169 bit32 eventLogOption; /**< DW17 Option of MSGU Event log */ 170 /* bit3-0 log severity, 0x0 Disable Logging */ 171 /* 0x1 Critical Error */ 172 /* 0x2 Minor Error */ 173 /* 0x3 Warning */ 174 /* 0x4 Information */ 175 /* 0x5 Debugging */ 176 /* 0x6 - 0xF Reserved */ 177 bit32 upperIOPeventLogAddress; /**< DW18 Upper physical IOP Event log address */ 178 bit32 lowerIOPeventLogAddress; /**< DW19 Lower physical IOP Event log address */ 179 bit32 IOPeventLogSize; /**< DW1A Size of IOP Event log, 0 means log disable */ 180 bit32 IOPeventLogOption; /**< DW1B Option of IOP Event log */ 181 /* bit3-0 log severity, 0x0 Critical Error */ 182 /* 0x1 Minor Error */ 183 /* 0x2 Warning */ 184 /* 0x3 Information */ 185 /* 0x4 Unknown */ 186 /* 0x5 - 0xF Reserved */ 187 bit32 FatalErrorInterrupt; /**< DW1C Fatal Error Interrupt enable and vector */ 188 /* bit0 Fatal Error Interrupt Enable */ 189 /* bit1 PI/CI 64bit address */ 190 /* bit2 SGPIO IOMB support */ 191 /* bit6-2 Reserved */ 192 /* bit7 OQ NP/HPriority Path enable */ 193 /* bit15-8 Fatal Error Interrupt Vector */ 194 /* bit16 Enable IQ/OQ 64 */ 195 /* bit17 Interrupt Reassertion Enable */ 196 /* bit18 Interrupt Reassertion Delay in ms */ 197 /* bit31-19 Interrupt Reassertion delay, 0-default 1ms */ 198 bit32 FatalErrorDumpOffset0; /**< DW1D FERDOMS-GU Fatal Error Register Dump Offset for MSGU */ 199 bit32 FatalErrorDumpLength0; /**< DW1E FERDLMS-GU Fatal Error Register Dump Length for MSGU */ 200 bit32 FatalErrorDumpOffset1; /**< DW1F FERDO-SSTRUCPCS Fatal Error Register Dump Offset for IOP */ 201 bit32 FatalErrorDumpLength1; /**< DW20 FERDLSTRUCTTPCS Fatal Error Register Dump Length for IOP */ 202 bit32 HDAModeFlags; /**< DW21 HDA Mode Flags, SPCV-reserved */ 203 bit32 analogSetupTblOffset; /**< DW22 SPASTO Phy Calibration Table offset */ 204 /* bit23-0 phy calib table offset */ 205 /* bit31-24 entry size */ 206 bit32 InterruptVecTblOffset; /**< DW23 Interrupt Vector Table MPI_TABLE_CHANG */ 207 /* bit23-0 interrupt vector table offset */ 208 /* bit31-24 entry size */ 209 bit32 phyAttributeTblOffset; /**< DW24 SAS Phy Attribute Table Offset MPI_TABLE_CHANG*/ 210 /* bit23-0 phy attribute table offset */ 211 /* bit31-24 entry size */ 212 bit32 portRecoveryResetTimer; /* Offset 0x25 [31:16] Port recovery timer default that is 0 213 used for all SAS ports. Granularity of this timer is 100ms. The host can 214 change the individual port recovery timer by using the PORT_CONTROL 215 [15:0] Port reset timer default that is used 3 (i.e 300ms) for all 216 SAS ports. Granularity of this timer is 100ms. Host can change the 217 individual port recovery timer by using PORT_CONTROL Command */ 218 bit32 interruptReassertionDelay; /* Offset 0x26 [23:0] Remind host of outbound completion 0 disabled 100usec per increment */ 219 220 bit32 ilaRevision; /* Offset 0x27 */ 221 }; 222 223 /* main configuration offset - byte offset */ 224 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 (R) */ 225 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 (R) */ 226 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 (R) */ 227 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 (R) */ 228 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 (R) */ 229 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 (R) */ 230 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 (R) */ 231 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 (R) */ 232 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 (R) */ 233 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 (W) */ 234 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28 /* DWORD 0x0A (W) */ /* reserved for SPCV */ 235 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C /* DWORD 0x0B (W) */ /* reserved for SPCV */ 236 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30 /* DWORD 0x0C (W) */ /* reserved for SPCV */ 237 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34 /* DWORD 0x0D (W) */ /* reserved for SPCV */ 238 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38 /* DWORD 0x0E (W) */ /* reserved for SPCV */ 239 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C /* DWORD 0x0F (W) */ /* reserved for SPCV */ 240 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40 /* DWORD 0x10 (W) */ /* reserved for SPCV */ 241 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44 /* DWORD 0x11 (W) */ /* reserved for SPCV */ 242 #define MAIN_IO_ABORT_DELAY 0x48 /* DWORD 0x12 (W) */ /* reserved for SPCV */ 243 #define MAIN_CUSTOMER_SETTING 0x4C /* DWORD 0x13 (W) */ /* reserved for SPCV */ 244 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 (W) */ 245 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 (W) */ 246 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 (W) */ 247 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 (W) */ 248 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 (W) */ 249 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 (W) */ 250 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A (W) */ 251 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B (W) */ 252 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C (W) */ 253 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D (R) */ 254 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E (R) */ 255 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F (R) */ 256 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 (R) */ 257 #define MAIN_HDA_FLAGS_OFFSET 0x84 /* DWORD 0x21 (R) */ /* reserved for SPCV */ 258 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 (R) */ 259 #define MAIN_INT_VEC_TABLE_OFFSET 0x8C /* DWORD 0x23 (W) */ /* for SPCV */ 260 #define MAIN_PHY_ATTRIBUTE_OFFSET 0x90 /* DWORD 0x24 (W) */ /* for SPCV */ 261 #define MAIN_PRECTD_PRESETD 0x94 /* DWORD 0x25 (W) */ /* for SPCV */ 262 #define MAIN_IRAD_RESERVED 0x98 /* DWORD 0x26 (W) */ /* for SPCV */ 263 #define MAIN_MOQFOT_MOQFOES 0x9C /* DWORD 0x27 (W) */ /* for SPCV */ 264 #define MAIN_MERRDCTO_MERRDCES 0xA0 /* DWORD 0x28 (W) */ /* for SPCV */ 265 #define MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN 0xA4 /* DWORD 0x29 (W) */ /* for SPCV */ 266 #define MAIN_INACTIVE_ILA_REVSION 0xA8 /* DWORD 0x2A (W) */ /* for SPCV V 3.02 */ 267 #define MAIN_SEEPROM_REVSION 0xAC /* DWORD 0x2B (W) */ /* for SPCV V 3.02 */ 268 #define MAIN_UNKNOWN1 0xB0 /* DWORD 0x2C (W) */ /* for SPCV V 3.03 */ 269 #define MAIN_UNKNOWN2 0xB4 /* DWORD 0x2D (W) */ /* for SPCV V 3.03 */ 270 #define MAIN_UNKNOWN3 0xB8 /* DWORD 0x2E (W) */ /* for SPCV V 3.03 */ 271 #define MAIN_XCBI_REF_TAG_PAT 0xBC /* DWORD 0x2F (W) */ /* for SPCV V 3.03 */ 272 #define MAIN_AWT_MIDRANGE 0xC0 /* DWORD 0x30 (W) */ /* for SPCV V 3.03 */ 273 274 275 typedef struct spc_configMainDescriptor_s spc_configMainDescriptor_t; 276 #define SPC_CONFIG 277 #endif 278 279 /* bit to disable end to end crc checking ins SPCv */ 280 #define MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x00010000 281 282 /* bit mask for field Controller Capability in main part */ 283 #define MAIN_MAX_IB_MASK 0x000000ff /* bit7-0 */ 284 #define MAIN_MAX_OB_MASK 0x0000ff00 /* bit15-8 */ 285 #define MAIN_PHY_COUNT_MASK 0x01f80000 /* bit24-19 */ 286 #define MAIN_QSUPPORT_BITS 0x0007ffff 287 #define MAIN_SAS_SUPPORT_BITS 0xfe000000 288 289 /* bit mask for field max sgl in main part */ 290 #define MAIN_MAX_SGL_BITS 0xFFFF 291 #define MAIN_MAX_DEV_BITS 0xFFFF0000 292 293 /* bit mask for HDA flags field */ 294 #define MAIN_HDA_FLAG_BITS 0x000000FF 295 296 #define FATAL_ERROR_INT_BITS 0xFF 297 #define INT_REASRT_ENABLE 0x00020000 298 #define INT_REASRT_MS_ENABLE 0x00040000 299 #define INT_REASRT_DELAY_BITS 0xFFF80000 300 301 #define MAX_VALID_PHYS 8 302 #define IB_QUEUE_CFGSIZE 64 303 #define OB_QUEUE_CFGSIZE 64 304 305 /* inbound queue configuration offset - byte offset */ 306 #define IB_PROPERITY_OFFSET 0x00 307 #define IB_BASE_ADDR_HI_OFFSET 0x04 308 #define IB_BASE_ADDR_LO_OFFSET 0x08 309 #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C 310 #define IB_CI_BASE_ADDR_LO_OFFSET 0x10 311 #define IB_PIPCI_BAR 0x14 312 #define IB_PIPCI_BAR_OFFSET 0x18 313 #define IB_RESERVED_OFFSET 0x1C 314 315 /* outbound queue configuration offset - byte offset */ 316 #define OB_PROPERITY_OFFSET 0x00 317 #define OB_BASE_ADDR_HI_OFFSET 0x04 318 #define OB_BASE_ADDR_LO_OFFSET 0x08 319 #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C 320 #define OB_PI_BASE_ADDR_LO_OFFSET 0x10 321 #define OB_CIPCI_BAR 0x14 322 #define OB_CIPCI_BAR_OFFSET 0x18 323 #define OB_INTERRUPT_COALES_OFFSET 0x1C 324 #define OB_DYNAMIC_COALES_OFFSET 0x20 325 326 #define OB_PROPERTY_INT_ENABLE 0x40000000 327 328 /* General Status Table offset - byte offset */ 329 #define GST_GSTLEN_MPIS_OFFSET 0x00 330 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04 331 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08 332 #define GST_MSGUTCNT_OFFSET 0x0C 333 #define GST_IOPTCNT_OFFSET 0x10 334 #define GST_IOP1TCNT_OFFSET 0x14 335 #define GST_PHYSTATE_OFFSET 0x18 /* SPCV reserved */ 336 #define GST_PHYSTATE0_OFFSET 0x18 /* SPCV reserved */ 337 #define GST_PHYSTATE1_OFFSET 0x1C /* SPCV reserved */ 338 #define GST_PHYSTATE2_OFFSET 0x20 /* SPCV reserved */ 339 #define GST_PHYSTATE3_OFFSET 0x24 /* SPCV reserved */ 340 #define GST_PHYSTATE4_OFFSET 0x28 /* SPCV reserved */ 341 #define GST_PHYSTATE5_OFFSET 0x2C /* SPCV reserved */ 342 #define GST_PHYSTATE6_OFFSET 0x30 /* SPCV reserved */ 343 #define GST_PHYSTATE7_OFFSET 0x34 /* SPCV reserved */ 344 #define GST_GPIO_PINS_OFFSET 0x38 345 #define GST_RERRINFO_OFFSET 0x44 346 347 /* General Status Table - MPI state */ 348 #define GST_MPI_STATE_UNINIT 0x00 349 #define GST_MPI_STATE_INIT 0x01 350 #define GST_MPI_STATE_TERMINATION 0x02 351 #define GST_MPI_STATE_ERROR 0x03 352 #define GST_MPI_STATE_MASK 0x07 353 354 #define GST_INF_STATE_BITS 0xfffe0007 355 356 357 /* MPI fatal and non fatal offset mask */ 358 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF 359 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */ 360 361 /* MPI fatal and non fatal Error dump capture table offset - byte offset */ 362 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ 363 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ 364 #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ 365 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ 366 #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ 367 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ 368 /* */ 369 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 370 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 371 /* */ 372 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 373 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 374 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 375 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 376 377 #define IOCTL_ERROR_NO_FATAL_ERROR 0x77 378 379 /*******************************************************************************/ 380 /** \struct spc_GSTableDescriptor_s 381 * \brief This structure is used for SPC MPI General Status Table 382 * 383 * This structure specifies all required attributes to Gereral Status Table 384 */ 385 /*******************************************************************************/ 386 struct spc_GSTableDescriptor_s 387 { 388 bit32 GSTLenMPIS; /**< DW0 - GST Length, MPI State */ 389 /**< bit02-00 MPI state */ 390 /**< 000 - not initialized, 001 - initialized, 391 010 - Configuration termination in progress */ 392 /**< bit3 - IQ Frozen */ 393 /**< bit15-04 GST Length */ 394 /**< bit31-16 MPI-S Initialize Error */ 395 bit32 IQFreezeState0; /**< DW1 - Inbound Queue Freeze State0 */ 396 bit32 IQFreezeState1; /**< DW2 - Inbound Qeue Freeze State1 */ 397 bit32 MsguTcnt; /**< DW3 - MSGU Tick count */ 398 bit32 IopTcnt; /**< DW4 - IOP Tick count */ 399 bit32 Iop1Tcnt; /**< DW5 - IOP1 Tick count */ 400 bit32 PhyState[MAX_VALID_PHYS]; /* SPCV = reserved */ 401 /**< DW6 to DW 0D - Phy Link state 0 to 7, Phy Start State 0 to 7 */ 402 /**< bit00 Phy Start state n, 0 not started, 1 started */ 403 /**< bit01 Phy Link state n, 0 link down, 1 link up */ 404 /**< bit31-2 Reserved */ 405 bit32 GPIOpins; /**< DWE - GPIO pins */ 406 bit32 reserved1; /**< DWF - reserved */ 407 bit32 reserved2; /**< DW10 - reserved */ 408 bit32 recoverErrInfo[8]; /**< DW11 to DW18 - Recoverable Error Information */ 409 }; 410 411 typedef struct spc_GSTableDescriptor_s spc_GSTableDescriptor_t; 412 413 /*******************************************************************************/ 414 /** \struct spc_SPASTable_s 415 * \brief SAS Phy Analog Setup Table 416 * 417 * The spc_SPASTable_s structure is used to set Phy Calibration 418 * attributes 419 */ 420 /*******************************************************************************/ 421 struct spc_SPASTable_s 422 { 423 bit32 spaReg0; /* transmitter per port configuration 1 SAS_SATA G1 */ 424 bit32 spaReg1; /* transmitter per port configuration 2 SAS_SATA G1*/ 425 bit32 spaReg2; /* transmitter per port configuration 3 SAS_SATA G1*/ 426 bit32 spaReg3; /* transmitter configuration 1 */ 427 bit32 spaReg4; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 428 bit32 spaReg5; /* reveiver per port configuration 2 SAS_SATA G3 */ 429 bit32 spaReg6; /* reveiver per configuration 1 */ 430 bit32 spaReg7; /* reveiver per configuration 2 */ 431 bit32 reserved[2]; /* reserved */ 432 }; 433 434 typedef struct spc_SPASTable_s spc_SPASTable_t; 435 436 /*******************************************************************************/ 437 /** \struct spc_inboundQueueDescriptor_s 438 * \brief This structure is used to configure inbound queues 439 * 440 * This structure specifies all required attributes to configure inbound queues 441 */ 442 /*******************************************************************************/ 443 struct spc_inboundQueueDescriptor_s 444 { 445 bit32 elementPriSizeCount; /**< Priority, Size, Count in the queue */ 446 /**< bit00-15 Count */ 447 /**< When set to 0, this queue is disabled */ 448 /**< bit16-29 Size */ 449 /**< bit30-31 Priority 00:Normal, 01:High Priority */ 450 bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ 451 bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ 452 bit32 ciUpperBaseAddress; /**< Upper physical address for inbound queue CI */ 453 bit32 ciLowerBaseAddress; /**< Lower physical address for inbound queue CI */ 454 bit32 PIPCIBar; /**< PCI BAR for PI Offset */ 455 bit32 PIOffset; /**< Offset address for inbound queue PI */ 456 bit32 reserved; /**< reserved */ 457 }; 458 459 typedef struct spc_inboundQueueDescriptor_s spc_inboundQueueDescriptor_t; 460 461 /*******************************************************************************/ 462 /** \struct spc_outboundQueueDescriptor_s 463 * \brief This structure is used to configure outbound queues 464 * 465 * This structure specifies all required attributes to configure outbound queues 466 */ 467 /*******************************************************************************/ 468 struct spc_outboundQueueDescriptor_s 469 { 470 bit32 elementSizeCount; /**< Size & Count of each element (slot) in the queue) */ 471 /**< bit00-15 Count */ 472 /**< When set to 0, this queue is disabled */ 473 /**< bit16-29 Size */ 474 /**< bit30 Interrupt enable/disable */ 475 /**< bit31 reserved */ 476 bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ 477 bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ 478 bit32 piUpperBaseAddress; /**< PI Upper Base Address for outbound queue */ 479 bit32 piLowerBaseAddress; /**< PI Lower Base Address for outbound queue */ 480 bit32 CIPCIBar; /**< PCI BAR for CI Offset */ 481 bit32 CIOffset; /**< Offset address for outbound queue CI */ 482 bit32 interruptVecCntDelay; /**< Delay in microseconds before the interrupt is asserted */ 483 /**< if the interrupt threshold has not been reached */ 484 /**< Number of interrupt events before the interrupt is asserted */ 485 /**< If set to 0, interrupts for this queue are disable */ 486 /**< Interrupt vector number for this queue */ 487 /**< Note that the interrupt type can be MSI or MSI-X */ 488 /**< depending on the system configuration */ 489 /**< bit00-15 Delay */ 490 /**< bit16-23 Count */ 491 /**< bit24-31 Vector */ 492 bit32 DInterruptTOPCIOffset; /**< Dynamic Interrupt Coalescing Timeout PCI Bar Offset */ 493 }; 494 495 typedef struct spc_outboundQueueDescriptor_s spc_outboundQueueDescriptor_t; 496 497 typedef struct InterruptVT_s 498 { 499 bit32 iccict; /**< DW0 - Interrupt Colescing Control and Timer */ 500 bit32 iraeirad; /**< DW1 - Interrupt Reassertion Enable/Delay */ 501 } InterruptVT_t; 502 503 typedef struct mpiInterruptVT_s 504 { 505 InterruptVT_t IntVecTble[MAX_NUM_VECTOR << 1]; 506 } mpiInterruptVT_t; 507 508 #define INT_VT_Coal_CNT_TO 0 509 #define INT_VT_Coal_ReAssert_Enab 4 510 511 typedef struct phyAttrb_s 512 { 513 bit32 phyState; 514 bit32 phyEventOQ; 515 } phyAttrb_t; 516 517 typedef struct sasPhyAttribute_s 518 { 519 phyAttrb_t phyAttribute[MAX_VALID_PHYS]; 520 }sasPhyAttribute_t; 521 522 523 #define PHY_STATE 0 524 #define PHY_EVENT_OQ 4 525 526 /*******************************************************************************/ 527 /** \struct spcMSGUConfig_s 528 * \brief This structure is used to configure controller's message unit 529 * 530 */ 531 /*******************************************************************************/ 532 typedef struct fwMSGUConfig_s 533 { 534 spc_configMainDescriptor_t mainConfiguration; /**< main part of Configuration Table */ 535 spc_GSTableDescriptor_t GeneralStatusTable; /**< MPI general status table */ 536 spc_inboundQueueDescriptor_t inboundQueue[IB_QUEUE_CFGSIZE]; /**< Inbound queue configuration array */ 537 spc_outboundQueueDescriptor_t outboundQueue[OB_QUEUE_CFGSIZE]; /**< Outbound queue configuration array */ 538 agsaPhyAnalogSetupTable_t phyAnalogConfig; 539 mpiInterruptVT_t interruptVTable; 540 sasPhyAttribute_t phyAttributeTable; 541 }fwMSGUConfig_t; 542 543 544 typedef void (*EnadDisabHandler_t)( 545 agsaRoot_t *agRoot, 546 bit32 interruptVectorIndex 547 ); 548 549 typedef bit32 (*InterruptOurs_t)( 550 agsaRoot_t *agRoot, 551 bit32 interruptVectorIndex 552 ); 553 #endif /* __SPC_DEFS__ */
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