1 /*-
2 * Copyright (c) 2005 Ruslan Ermilov
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/amdsmb.c,v 1.6 2008/06/06 18:29:56 jhb Exp $
27 */
28
29 #include <sys/param.h>
30 #include <sys/bus.h>
31 #include <sys/globaldata.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/module.h>
35 #include <sys/systm.h>
36
37 #include <sys/rman.h>
38
39 #include <bus/pci/pcivar.h>
40 #include <bus/pci/pcireg.h>
41
42 #include <bus/smbus/smbconf.h>
43 #include "smbus_if.h"
44
45 #define AMDSMB_DEBUG(x) if (amdsmb_debug) (x)
46
47 #ifdef DEBUG
48 static int amdsmb_debug = 1;
49 #else
50 static int amdsmb_debug = 0;
51 #endif
52
53 #define AMDSMB_VENDORID_AMD 0x1022
54 #define AMDSMB_DEVICEID_AMD8111_SMB2 0x746a
55
56 /*
57 * ACPI 3.0, Chapter 12, Embedded Controller Interface.
58 */
59 #define EC_DATA 0x00 /* data register */
60 #define EC_SC 0x04 /* status of controller */
61 #define EC_CMD 0x04 /* command register */
62
63 #define EC_SC_IBF 0x02 /* data ready for embedded controller */
64 #define EC_SC_OBF 0x01 /* data ready for host */
65 #define EC_CMD_WR 0x81 /* write EC */
66 #define EC_CMD_RD 0x80 /* read EC */
67
68 /*
69 * ACPI 3.0, Chapter 12, SMBus Host Controller Interface.
70 */
71 #define SMB_PRTCL 0x00 /* protocol */
72 #define SMB_STS 0x01 /* status */
73 #define SMB_ADDR 0x02 /* address */
74 #define SMB_CMD 0x03 /* command */
75 #define SMB_DATA 0x04 /* 32 data registers */
76 #define SMB_BCNT 0x24 /* number of data bytes */
77 #define SMB_ALRM_A 0x25 /* alarm address */
78 #define SMB_ALRM_D 0x26 /* 2 bytes alarm data */
79
80 #define SMB_STS_DONE 0x80
81 #define SMB_STS_ALRM 0x40
82 #define SMB_STS_RES 0x20
83 #define SMB_STS_STATUS 0x1f
84 #define SMB_STS_OK 0x00 /* OK */
85 #define SMB_STS_UF 0x07 /* Unknown Failure */
86 #define SMB_STS_DANA 0x10 /* Device Address Not Acknowledged */
87 #define SMB_STS_DED 0x11 /* Device Error Detected */
88 #define SMB_STS_DCAD 0x12 /* Device Command Access Denied */
89 #define SMB_STS_UE 0x13 /* Unknown Error */
90 #define SMB_STS_DAD 0x17 /* Device Access Denied */
91 #define SMB_STS_T 0x18 /* Timeout */
92 #define SMB_STS_HUP 0x19 /* Host Unsupported Protocol */
93 #define SMB_STS_B 0x1a /* Busy */
94 #define SMB_STS_PEC 0x1f /* PEC (CRC-8) Error */
95
96 #define SMB_PRTCL_WRITE 0x00
97 #define SMB_PRTCL_READ 0x01
98 #define SMB_PRTCL_QUICK 0x02
99 #define SMB_PRTCL_BYTE 0x04
100 #define SMB_PRTCL_BYTE_DATA 0x06
101 #define SMB_PRTCL_WORD_DATA 0x08
102 #define SMB_PRTCL_BLOCK_DATA 0x0a
103 #define SMB_PRTCL_PROC_CALL 0x0c
104 #define SMB_PRTCL_BLOCK_PROC_CALL 0x0d
105 #define SMB_PRTCL_PEC 0x80
106
107 struct amdsmb_softc {
108 int rid;
109 struct resource *res;
110 device_t smbus;
111 struct lock lock;
112 };
113
114 #define AMDSMB_LOCK(amdsmb) lockmgr(&(amdsmb)->lock, LK_EXCLUSIVE)
115 #define AMDSMB_UNLOCK(amdsmb) lockmgr(&(amdsmb)->lock, LK_RELEASE)
116 #define AMDSMB_LOCK_ASSERT(amdsmb) KKASSERT(lockstatus(&(amdsmb)->lock, curthread) != 0)
117
118 #define AMDSMB_ECINB(amdsmb, register) \
119 (bus_read_1(amdsmb->res, register))
120 #define AMDSMB_ECOUTB(amdsmb, register, value) \
121 (bus_write_1(amdsmb->res, register, value))
122
123 static int amdsmb_detach(device_t dev);
124
125 static int
126 amdsmb_probe(device_t dev)
127 {
128 u_int16_t vid;
129 u_int16_t did;
130
131 vid = pci_get_vendor(dev);
132 did = pci_get_device(dev);
133
134 if (vid == AMDSMB_VENDORID_AMD) {
135 switch(did) {
136 case AMDSMB_DEVICEID_AMD8111_SMB2:
137 device_set_desc(dev, "AMD-8111 SMBus 2.0 Controller");
138 return (BUS_PROBE_DEFAULT);
139 }
140 }
141
142 return (ENXIO);
143 }
144
145 static int
146 amdsmb_attach(device_t dev)
147 {
148 struct amdsmb_softc *amdsmb_sc = device_get_softc(dev);
149
150 /* Allocate I/O space */
151 amdsmb_sc->rid = PCIR_BAR(0);
152
153 amdsmb_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
154 &amdsmb_sc->rid, RF_ACTIVE);
155
156 if (amdsmb_sc->res == NULL) {
157 device_printf(dev, "could not map i/o space\n");
158 return (ENXIO);
159 }
160
161 lockinit(&amdsmb_sc->lock, "amdsmb", 0, LK_CANRECURSE);
162
163 /* Allocate a new smbus device */
164 amdsmb_sc->smbus = device_add_child(dev, "smbus", -1);
165 if (!amdsmb_sc->smbus) {
166 amdsmb_detach(dev);
167 return (EINVAL);
168 }
169
170 bus_generic_attach(dev);
171
172 return (0);
173 }
174
175 static int
176 amdsmb_detach(device_t dev)
177 {
178 struct amdsmb_softc *amdsmb_sc = device_get_softc(dev);
179
180 if (amdsmb_sc->smbus) {
181 device_delete_child(dev, amdsmb_sc->smbus);
182 amdsmb_sc->smbus = NULL;
183 }
184
185 lockuninit(&amdsmb_sc->lock);
186 if (amdsmb_sc->res)
187 bus_release_resource(dev, SYS_RES_IOPORT, amdsmb_sc->rid,
188 amdsmb_sc->res);
189
190 return (0);
191 }
192
193 static int
194 amdsmb_callback(device_t dev, int index, void *data)
195 {
196 int error = 0;
197
198 switch (index) {
199 case SMB_REQUEST_BUS:
200 case SMB_RELEASE_BUS:
201 break;
202 default:
203 error = EINVAL;
204 }
205
206 return (error);
207 }
208
209 static int
210 amdsmb_ec_wait_write(struct amdsmb_softc *sc)
211 {
212 int timeout = 500;
213
214 while (timeout-- && AMDSMB_ECINB(sc, EC_SC) & EC_SC_IBF)
215 DELAY(1);
216 if (timeout == 0) {
217 device_printf(sc->smbus, "timeout waiting for IBF to clear\n");
218 return (1);
219 }
220 return (0);
221 }
222
223 static int
224 amdsmb_ec_wait_read(struct amdsmb_softc *sc)
225 {
226 int timeout = 500;
227
228 while (timeout-- && ~AMDSMB_ECINB(sc, EC_SC) & EC_SC_OBF)
229 DELAY(1);
230 if (timeout == 0) {
231 device_printf(sc->smbus, "timeout waiting for OBF to set\n");
232 return (1);
233 }
234 return (0);
235 }
236
237 static int
238 amdsmb_ec_read(struct amdsmb_softc *sc, u_char addr, u_char *data)
239 {
240
241 AMDSMB_LOCK_ASSERT(sc);
242 if (amdsmb_ec_wait_write(sc))
243 return (1);
244 AMDSMB_ECOUTB(sc, EC_CMD, EC_CMD_RD);
245
246 if (amdsmb_ec_wait_write(sc))
247 return (1);
248 AMDSMB_ECOUTB(sc, EC_DATA, addr);
249
250 if (amdsmb_ec_wait_read(sc))
251 return (1);
252 *data = AMDSMB_ECINB(sc, EC_DATA);
253
254 return (0);
255 }
256
257 static int
258 amdsmb_ec_write(struct amdsmb_softc *sc, u_char addr, u_char data)
259 {
260
261 AMDSMB_LOCK_ASSERT(sc);
262 if (amdsmb_ec_wait_write(sc))
263 return (1);
264 AMDSMB_ECOUTB(sc, EC_CMD, EC_CMD_WR);
265
266 if (amdsmb_ec_wait_write(sc))
267 return (1);
268 AMDSMB_ECOUTB(sc, EC_DATA, addr);
269
270 if (amdsmb_ec_wait_write(sc))
271 return (1);
272 AMDSMB_ECOUTB(sc, EC_DATA, data);
273
274 return (0);
275 }
276
277 static int
278 amdsmb_wait(struct amdsmb_softc *sc)
279 {
280 u_char sts, temp;
281 int error, count;
282
283 AMDSMB_LOCK_ASSERT(sc);
284 amdsmb_ec_read(sc, SMB_PRTCL, &temp);
285 if (temp != 0)
286 {
287 count = 10000;
288 do {
289 DELAY(500);
290 amdsmb_ec_read(sc, SMB_PRTCL, &temp);
291 } while (temp != 0 && count--);
292 if (count == 0)
293 return (SMB_ETIMEOUT);
294 }
295
296 amdsmb_ec_read(sc, SMB_STS, &sts);
297 sts &= SMB_STS_STATUS;
298 AMDSMB_DEBUG(kprintf("amdsmb: STS=0x%x\n", sts));
299
300 switch (sts) {
301 case SMB_STS_OK:
302 error = SMB_ENOERR;
303 break;
304 case SMB_STS_DANA:
305 error = SMB_ENOACK;
306 break;
307 case SMB_STS_B:
308 error = SMB_EBUSY;
309 break;
310 case SMB_STS_T:
311 error = SMB_ETIMEOUT;
312 break;
313 case SMB_STS_DCAD:
314 case SMB_STS_DAD:
315 case SMB_STS_HUP:
316 error = SMB_ENOTSUPP;
317 break;
318 default:
319 error = SMB_EBUSERR;
320 break;
321 }
322
323 return (error);
324 }
325
326 static int
327 amdsmb_quick(device_t dev, u_char slave, int how)
328 {
329 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
330 u_char protocol;
331 int error;
332
333 protocol = SMB_PRTCL_QUICK;
334
335 switch (how) {
336 case SMB_QWRITE:
337 protocol |= SMB_PRTCL_WRITE;
338 AMDSMB_DEBUG(kprintf("amdsmb: QWRITE to 0x%x", slave));
339 break;
340 case SMB_QREAD:
341 protocol |= SMB_PRTCL_READ;
342 AMDSMB_DEBUG(kprintf("amdsmb: QREAD to 0x%x", slave));
343 break;
344 default:
345 panic("%s: unknown QUICK command (%x)!", __func__, how);
346 }
347
348 AMDSMB_LOCK(sc);
349 amdsmb_ec_write(sc, SMB_ADDR, slave);
350 amdsmb_ec_write(sc, SMB_PRTCL, protocol);
351
352 error = amdsmb_wait(sc);
353
354 AMDSMB_DEBUG(kprintf(", error=0x%x\n", error));
355 AMDSMB_UNLOCK(sc);
356
357 return (error);
358 }
359
360 static int
361 amdsmb_sendb(device_t dev, u_char slave, char byte)
362 {
363 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
364 int error;
365
366 AMDSMB_LOCK(sc);
367 amdsmb_ec_write(sc, SMB_CMD, byte);
368 amdsmb_ec_write(sc, SMB_ADDR, slave);
369 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_WRITE | SMB_PRTCL_BYTE);
370
371 error = amdsmb_wait(sc);
372
373 AMDSMB_DEBUG(kprintf("amdsmb: SENDB to 0x%x, byte=0x%x, error=0x%x\n",
374 slave, byte, error));
375 AMDSMB_UNLOCK(sc);
376
377 return (error);
378 }
379
380 static int
381 amdsmb_recvb(device_t dev, u_char slave, char *byte)
382 {
383 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
384 int error;
385
386 AMDSMB_LOCK(sc);
387 amdsmb_ec_write(sc, SMB_ADDR, slave);
388 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_READ | SMB_PRTCL_BYTE);
389
390 if ((error = amdsmb_wait(sc)) == SMB_ENOERR)
391 amdsmb_ec_read(sc, SMB_DATA, byte);
392
393 AMDSMB_DEBUG(kprintf("amdsmb: RECVB from 0x%x, byte=0x%x, error=0x%x\n",
394 slave, *byte, error));
395 AMDSMB_UNLOCK(sc);
396
397 return (error);
398 }
399
400 static int
401 amdsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
402 {
403 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
404 int error;
405
406 AMDSMB_LOCK(sc);
407 amdsmb_ec_write(sc, SMB_CMD, cmd);
408 amdsmb_ec_write(sc, SMB_DATA, byte);
409 amdsmb_ec_write(sc, SMB_ADDR, slave);
410 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_WRITE | SMB_PRTCL_BYTE_DATA);
411
412 error = amdsmb_wait(sc);
413
414 AMDSMB_DEBUG(kprintf("amdsmb: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, "
415 "error=0x%x\n", slave, cmd, byte, error));
416 AMDSMB_UNLOCK(sc);
417
418 return (error);
419 }
420
421 static int
422 amdsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
423 {
424 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
425 int error;
426
427 AMDSMB_LOCK(sc);
428 amdsmb_ec_write(sc, SMB_CMD, cmd);
429 amdsmb_ec_write(sc, SMB_ADDR, slave);
430 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_READ | SMB_PRTCL_BYTE_DATA);
431
432 if ((error = amdsmb_wait(sc)) == SMB_ENOERR)
433 amdsmb_ec_read(sc, SMB_DATA, byte);
434
435 AMDSMB_DEBUG(kprintf("amdsmb: READB from 0x%x, cmd=0x%x, byte=0x%x, "
436 "error=0x%x\n", slave, cmd, (unsigned char)*byte, error));
437 AMDSMB_UNLOCK(sc);
438
439 return (error);
440 }
441
442 static int
443 amdsmb_writew(device_t dev, u_char slave, char cmd, short word)
444 {
445 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
446 int error;
447
448 AMDSMB_LOCK(sc);
449 amdsmb_ec_write(sc, SMB_CMD, cmd);
450 amdsmb_ec_write(sc, SMB_DATA, word);
451 amdsmb_ec_write(sc, SMB_DATA + 1, word >> 8);
452 amdsmb_ec_write(sc, SMB_ADDR, slave);
453 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_WRITE | SMB_PRTCL_WORD_DATA);
454
455 error = amdsmb_wait(sc);
456
457 AMDSMB_DEBUG(kprintf("amdsmb: WRITEW to 0x%x, cmd=0x%x, word=0x%x, "
458 "error=0x%x\n", slave, cmd, word, error));
459 AMDSMB_UNLOCK(sc);
460
461 return (error);
462 }
463
464 static int
465 amdsmb_readw(device_t dev, u_char slave, char cmd, short *word)
466 {
467 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
468 u_char temp[2];
469 int error;
470
471 AMDSMB_LOCK(sc);
472 amdsmb_ec_write(sc, SMB_CMD, cmd);
473 amdsmb_ec_write(sc, SMB_ADDR, slave);
474 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_READ | SMB_PRTCL_WORD_DATA);
475
476 if ((error = amdsmb_wait(sc)) == SMB_ENOERR) {
477 amdsmb_ec_read(sc, SMB_DATA + 0, &temp[0]);
478 amdsmb_ec_read(sc, SMB_DATA + 1, &temp[1]);
479 *word = temp[0] | (temp[1] << 8);
480 }
481
482 AMDSMB_DEBUG(kprintf("amdsmb: READW from 0x%x, cmd=0x%x, word=0x%x, "
483 "error=0x%x\n", slave, cmd, (unsigned short)*word, error));
484 AMDSMB_UNLOCK(sc);
485
486 return (error);
487 }
488
489 static int
490 amdsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
491 {
492 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
493 u_char i;
494 int error;
495
496 if (count < 1 || count > 32)
497 return (SMB_EINVAL);
498
499 AMDSMB_LOCK(sc);
500 amdsmb_ec_write(sc, SMB_CMD, cmd);
501 amdsmb_ec_write(sc, SMB_BCNT, count);
502 for (i = 0; i < count; i++)
503 amdsmb_ec_write(sc, SMB_DATA + i, buf[i]);
504 amdsmb_ec_write(sc, SMB_ADDR, slave);
505 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_WRITE | SMB_PRTCL_BLOCK_DATA);
506
507 error = amdsmb_wait(sc);
508
509 AMDSMB_DEBUG(kprintf("amdsmb: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, "
510 "error=0x%x", slave, count, cmd, error));
511 AMDSMB_UNLOCK(sc);
512
513 return (error);
514 }
515
516 static int
517 amdsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
518 {
519 struct amdsmb_softc *sc = (struct amdsmb_softc *)device_get_softc(dev);
520 u_char data, len, i;
521 int error;
522
523 if (*count < 1 || *count > 32)
524 return (SMB_EINVAL);
525
526 AMDSMB_LOCK(sc);
527 amdsmb_ec_write(sc, SMB_CMD, cmd);
528 amdsmb_ec_write(sc, SMB_ADDR, slave);
529 amdsmb_ec_write(sc, SMB_PRTCL, SMB_PRTCL_READ | SMB_PRTCL_BLOCK_DATA);
530
531 if ((error = amdsmb_wait(sc)) == SMB_ENOERR) {
532 amdsmb_ec_read(sc, SMB_BCNT, &len);
533 for (i = 0; i < len; i++) {
534 amdsmb_ec_read(sc, SMB_DATA + i, &data);
535 if (i < *count)
536 buf[i] = data;
537 }
538 *count = len;
539 }
540
541 AMDSMB_DEBUG(kprintf("amdsmb: READBLK to 0x%x, count=0x%x, cmd=0x%x, "
542 "error=0x%x", slave, *count, cmd, error));
543 AMDSMB_UNLOCK(sc);
544
545 return (error);
546 }
547
548 static device_method_t amdsmb_methods[] = {
549 /* Device interface */
550 DEVMETHOD(device_probe, amdsmb_probe),
551 DEVMETHOD(device_attach, amdsmb_attach),
552 DEVMETHOD(device_detach, amdsmb_detach),
553
554 /* SMBus interface */
555 DEVMETHOD(smbus_callback, amdsmb_callback),
556 DEVMETHOD(smbus_quick, amdsmb_quick),
557 DEVMETHOD(smbus_sendb, amdsmb_sendb),
558 DEVMETHOD(smbus_recvb, amdsmb_recvb),
559 DEVMETHOD(smbus_writeb, amdsmb_writeb),
560 DEVMETHOD(smbus_readb, amdsmb_readb),
561 DEVMETHOD(smbus_writew, amdsmb_writew),
562 DEVMETHOD(smbus_readw, amdsmb_readw),
563 DEVMETHOD(smbus_bwrite, amdsmb_bwrite),
564 DEVMETHOD(smbus_bread, amdsmb_bread),
565
566 DEVMETHOD_END
567 };
568
569 static devclass_t amdsmb_devclass;
570
571 static driver_t amdsmb_driver = {
572 "amdsmb",
573 amdsmb_methods,
574 sizeof(struct amdsmb_softc),
575 };
576
577 DRIVER_MODULE(amdsmb, pci, amdsmb_driver, amdsmb_devclass, NULL, NULL);
578 DRIVER_MODULE(smbus, amdsmb, smbus_driver, smbus_devclass, NULL, NULL);
579
580 MODULE_DEPEND(amdsmb, pci, 1, 1, 1);
581 MODULE_DEPEND(amdsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
582 MODULE_VERSION(amdsmb, 1);
Cache object: 32052e378aeacdb350a8b777804e22e0
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