pucdata.c

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    1 /*-
    2  * Copyright (c) 2006 Marcel Moolenaar
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  *
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/8.1/sys/dev/puc/pucdata.c 208518 2010-05-24 19:36:15Z jhb $");
   29 
   30 /*
   31  * PCI "universal" communications card driver configuration data (used to
   32  * match/attach the cards).
   33  */
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/kernel.h>
   38 #include <sys/bus.h>
   39 
   40 #include <machine/resource.h>
   41 #include <machine/bus.h>
   42 #include <sys/rman.h>
   43 
   44 #include <dev/pci/pcivar.h>
   45 
   46 #include <dev/puc/puc_bus.h>
   47 #include <dev/puc/puc_cfg.h>
   48 #include <dev/puc/puc_bfe.h>
   49 
   50 static puc_config_f puc_config_amc;
   51 static puc_config_f puc_config_cronyx;
   52 static puc_config_f puc_config_diva;
   53 static puc_config_f puc_config_icbook;
   54 static puc_config_f puc_config_quatech;
   55 static puc_config_f puc_config_syba;
   56 static puc_config_f puc_config_siig;
   57 static puc_config_f puc_config_timedia;
   58 static puc_config_f puc_config_titan;
   59 
   60 const struct puc_cfg puc_pci_devices[] = {
   61 
   62         {   0x0009, 0x7168, 0xffff, 0,
   63             "Sunix SUN1889",
   64             DEFAULT_RCLK * 8,
   65             PUC_PORT_2S, 0x10, 0, 8,
   66         },
   67 
   68         {   0x103c, 0x1048, 0x103c, 0x1049,
   69             "HP Diva Serial [GSP] Multiport UART - Tosca Console",
   70             DEFAULT_RCLK,
   71             PUC_PORT_3S, 0x10, 0, -1,
   72             .config_function = puc_config_diva
   73         },
   74 
   75         {   0x103c, 0x1048, 0x103c, 0x104a,
   76             "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
   77             DEFAULT_RCLK,
   78             PUC_PORT_2S, 0x10, 0, -1,
   79             .config_function = puc_config_diva
   80         },
   81 
   82         {   0x103c, 0x1048, 0x103c, 0x104b,
   83             "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
   84             DEFAULT_RCLK,
   85             PUC_PORT_4S, 0x10, 0, -1,
   86             .config_function = puc_config_diva
   87         },
   88 
   89         {   0x103c, 0x1048, 0x103c, 0x1223,
   90             "HP Diva Serial [GSP] Multiport UART - Superdome Console",
   91             DEFAULT_RCLK,
   92             PUC_PORT_3S, 0x10, 0, -1,
   93             .config_function = puc_config_diva
   94         },
   95 
   96         {   0x103c, 0x1048, 0x103c, 0x1226,
   97             "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
   98             DEFAULT_RCLK,
   99             PUC_PORT_3S, 0x10, 0, -1,
  100             .config_function = puc_config_diva
  101         },
  102 
  103         {   0x103c, 0x1048, 0x103c, 0x1282,
  104             "HP Diva Serial [GSP] Multiport UART - Everest SP2",
  105             DEFAULT_RCLK,
  106             PUC_PORT_3S, 0x10, 0, -1,
  107             .config_function = puc_config_diva
  108         },
  109 
  110         {   0x10b5, 0x1076, 0x10b5, 0x1076,
  111             "VScom PCI-800",
  112             DEFAULT_RCLK * 8,
  113             PUC_PORT_8S, 0x18, 0, 8,
  114         },
  115 
  116         {   0x10b5, 0x1077, 0x10b5, 0x1077,
  117             "VScom PCI-400",
  118             DEFAULT_RCLK * 8,
  119             PUC_PORT_4S, 0x18, 0, 8,
  120         },
  121 
  122         {   0x10b5, 0x1103, 0x10b5, 0x1103,
  123             "VScom PCI-200",
  124             DEFAULT_RCLK * 8,
  125             PUC_PORT_2S, 0x18, 4, 0,
  126         },
  127 
  128         /*
  129          * Boca Research Turbo Serial 658 (8 serial port) card.
  130          * Appears to be the same as Chase Research PLC PCI-FAST8
  131          * and Perle PCI-FAST8 Multi-Port serial cards.
  132          */
  133         {   0x10b5, 0x9050, 0x12e0, 0x0021,
  134             "Boca Research Turbo Serial 658",
  135             DEFAULT_RCLK * 4,
  136             PUC_PORT_8S, 0x18, 0, 8,
  137         },
  138 
  139         {   0x10b5, 0x9050, 0x12e0, 0x0031,
  140             "Boca Research Turbo Serial 654",
  141             DEFAULT_RCLK * 4,
  142             PUC_PORT_4S, 0x18, 0, 8,
  143         },
  144 
  145         /*
  146          * Dolphin Peripherals 4035 (dual serial port) card.  PLX 9050, with
  147          * a seemingly-lame EEPROM setup that puts the Dolphin IDs
  148          * into the subsystem fields, and claims that it's a
  149          * network/misc (0x02/0x80) device.
  150          */
  151         {   0x10b5, 0x9050, 0xd84d, 0x6808,
  152             "Dolphin Peripherals 4035",
  153             DEFAULT_RCLK,
  154             PUC_PORT_2S, 0x18, 4, 0,
  155         },
  156 
  157         /*
  158          * Dolphin Peripherals 4014 (dual parallel port) card.  PLX 9050, with
  159          * a seemingly-lame EEPROM setup that puts the Dolphin IDs
  160          * into the subsystem fields, and claims that it's a
  161          * network/misc (0x02/0x80) device.
  162          */
  163         {   0x10b5, 0x9050, 0xd84d, 0x6810,
  164             "Dolphin Peripherals 4014",
  165             0,
  166             PUC_PORT_2P, 0x20, 4, 0,
  167         },
  168 
  169         {   0x10e8, 0x818e, 0xffff, 0,
  170             "Applied Micro Circuits 8 Port UART",
  171             DEFAULT_RCLK,
  172             PUC_PORT_8S, 0x14, -1, -1,
  173             .config_function = puc_config_amc
  174         },
  175 
  176         {   0x11fe, 0x8010, 0xffff, 0,
  177             "Comtrol RocketPort 550/8 RJ11 part A",
  178             DEFAULT_RCLK * 4,
  179             PUC_PORT_4S, 0x10, 0, 8,
  180         },
  181 
  182         {   0x11fe, 0x8011, 0xffff, 0,
  183             "Comtrol RocketPort 550/8 RJ11 part B",
  184             DEFAULT_RCLK * 4,
  185             PUC_PORT_4S, 0x10, 0, 8,
  186         },
  187 
  188         {   0x11fe, 0x8012, 0xffff, 0,
  189             "Comtrol RocketPort 550/8 Octa part A",
  190             DEFAULT_RCLK * 4,
  191             PUC_PORT_4S, 0x10, 0, 8,
  192         },
  193 
  194         {   0x11fe, 0x8013, 0xffff, 0,
  195             "Comtrol RocketPort 550/8 Octa part B",
  196             DEFAULT_RCLK * 4,
  197             PUC_PORT_4S, 0x10, 0, 8,
  198         },
  199 
  200         {   0x11fe, 0x8014, 0xffff, 0,
  201             "Comtrol RocketPort 550/4 RJ45",
  202             DEFAULT_RCLK * 4,
  203             PUC_PORT_4S, 0x10, 0, 8,
  204         },
  205 
  206         {   0x11fe, 0x8015, 0xffff, 0,
  207             "Comtrol RocketPort 550/Quad",
  208             DEFAULT_RCLK * 4,
  209             PUC_PORT_4S, 0x10, 0, 8,
  210         },
  211 
  212         {   0x11fe, 0x8016, 0xffff, 0,
  213             "Comtrol RocketPort 550/16 part A",
  214             DEFAULT_RCLK * 4,
  215             PUC_PORT_4S, 0x10, 0, 8,
  216         },
  217 
  218         {   0x11fe, 0x8017, 0xffff, 0,
  219             "Comtrol RocketPort 550/16 part B",
  220             DEFAULT_RCLK * 4,
  221             PUC_PORT_12S, 0x10, 0, 8,
  222         },
  223 
  224         {   0x11fe, 0x8018, 0xffff, 0,
  225             "Comtrol RocketPort 550/8 part A",
  226             DEFAULT_RCLK * 4,
  227             PUC_PORT_4S, 0x10, 0, 8,
  228         },
  229 
  230         {   0x11fe, 0x8019, 0xffff, 0,
  231             "Comtrol RocketPort 550/8 part B",
  232             DEFAULT_RCLK * 4,
  233             PUC_PORT_4S, 0x10, 0, 8,
  234         },
  235 
  236         /*
  237          * IBM SurePOS 300 Series (481033H) serial ports
  238          * Details can be found on the IBM RSS websites
  239          */
  240 
  241         {   0x1014, 0x0297, 0xffff, 0,
  242             "IBM SurePOS 300 Series (481033H) serial ports",
  243             DEFAULT_RCLK,
  244             PUC_PORT_4S, 0x10, 4, 0
  245         },
  246 
  247         /*
  248          * SIIG Boards.
  249          *
  250          * SIIG provides documentation for their boards at:
  251          * <URL:http://www.siig.com/downloads.asp>
  252          */
  253 
  254         {   0x131f, 0x1010, 0xffff, 0,
  255             "SIIG Cyber I/O PCI 16C550 (10x family)",
  256             DEFAULT_RCLK,
  257             PUC_PORT_1S1P, 0x18, 4, 0,
  258         },
  259 
  260         {   0x131f, 0x1011, 0xffff, 0,
  261             "SIIG Cyber I/O PCI 16C650 (10x family)",
  262             DEFAULT_RCLK,
  263             PUC_PORT_1S1P, 0x18, 4, 0,
  264         },
  265 
  266         {   0x131f, 0x1012, 0xffff, 0,
  267             "SIIG Cyber I/O PCI 16C850 (10x family)",
  268             DEFAULT_RCLK,
  269             PUC_PORT_1S1P, 0x18, 4, 0,
  270         },
  271 
  272         {   0x131f, 0x1021, 0xffff, 0,
  273             "SIIG Cyber Parallel Dual PCI (10x family)",
  274             0,
  275             PUC_PORT_2P, 0x18, 8, 0,
  276         },
  277 
  278         {   0x131f, 0x1030, 0xffff, 0,
  279             "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
  280             DEFAULT_RCLK,
  281             PUC_PORT_2S, 0x18, 4, 0,
  282         },
  283 
  284         {   0x131f, 0x1031, 0xffff, 0,
  285             "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
  286             DEFAULT_RCLK,
  287             PUC_PORT_2S, 0x18, 4, 0,
  288         },
  289 
  290         {   0x131f, 0x1032, 0xffff, 0,
  291             "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
  292             DEFAULT_RCLK,
  293             PUC_PORT_2S, 0x18, 4, 0,
  294         },
  295 
  296         {   0x131f, 0x1034, 0xffff, 0,  /* XXX really? */
  297             "SIIG Cyber 2S1P PCI 16C550 (10x family)",
  298             DEFAULT_RCLK,
  299             PUC_PORT_2S1P, 0x18, 4, 0,
  300         },
  301 
  302         {   0x131f, 0x1035, 0xffff, 0,  /* XXX really? */
  303             "SIIG Cyber 2S1P PCI 16C650 (10x family)",
  304             DEFAULT_RCLK,
  305             PUC_PORT_2S1P, 0x18, 4, 0,
  306         },
  307 
  308         {   0x131f, 0x1036, 0xffff, 0,  /* XXX really? */
  309             "SIIG Cyber 2S1P PCI 16C850 (10x family)",
  310             DEFAULT_RCLK,
  311             PUC_PORT_2S1P, 0x18, 4, 0,
  312         },
  313 
  314         {   0x131f, 0x1050, 0xffff, 0,
  315             "SIIG Cyber 4S PCI 16C550 (10x family)",
  316             DEFAULT_RCLK,
  317             PUC_PORT_4S, 0x18, 4, 0,
  318         },
  319 
  320         {   0x131f, 0x1051, 0xffff, 0,
  321             "SIIG Cyber 4S PCI 16C650 (10x family)",
  322             DEFAULT_RCLK,
  323             PUC_PORT_4S, 0x18, 4, 0,
  324         },
  325 
  326         {   0x131f, 0x1052, 0xffff, 0,
  327             "SIIG Cyber 4S PCI 16C850 (10x family)",
  328             DEFAULT_RCLK,
  329             PUC_PORT_4S, 0x18, 4, 0,
  330         },
  331 
  332         {   0x131f, 0x2010, 0xffff, 0,
  333             "SIIG Cyber I/O PCI 16C550 (20x family)",
  334             DEFAULT_RCLK,
  335             PUC_PORT_1S1P, 0x10, 4, 0,
  336         },
  337 
  338         {   0x131f, 0x2011, 0xffff, 0,
  339             "SIIG Cyber I/O PCI 16C650 (20x family)",
  340             DEFAULT_RCLK,
  341             PUC_PORT_1S1P, 0x10, 4, 0,
  342         },
  343 
  344         {   0x131f, 0x2012, 0xffff, 0,
  345             "SIIG Cyber I/O PCI 16C850 (20x family)",
  346             DEFAULT_RCLK,
  347             PUC_PORT_1S1P, 0x10, 4, 0,
  348         },
  349 
  350         {   0x131f, 0x2021, 0xffff, 0,
  351             "SIIG Cyber Parallel Dual PCI (20x family)",
  352             0,
  353             PUC_PORT_2P, 0x10, 8, 0,
  354         },
  355 
  356         {   0x131f, 0x2030, 0xffff, 0,
  357             "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
  358             DEFAULT_RCLK,
  359             PUC_PORT_2S, 0x10, 4, 0,
  360         },
  361 
  362         {   0x131f, 0x2031, 0xffff, 0,
  363             "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
  364             DEFAULT_RCLK,
  365             PUC_PORT_2S, 0x10, 4, 0,
  366         },
  367 
  368         {   0x131f, 0x2032, 0xffff, 0,
  369             "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
  370             DEFAULT_RCLK,
  371             PUC_PORT_2S, 0x10, 4, 0,
  372         },
  373 
  374         {   0x131f, 0x2040, 0xffff, 0,
  375             "SIIG Cyber 2P1S PCI 16C550 (20x family)",
  376             DEFAULT_RCLK,
  377             PUC_PORT_1S2P, 0x10, -1, 0,
  378             .config_function = puc_config_siig
  379         },
  380 
  381         {   0x131f, 0x2041, 0xffff, 0,
  382             "SIIG Cyber 2P1S PCI 16C650 (20x family)",
  383             DEFAULT_RCLK,
  384             PUC_PORT_1S2P, 0x10, -1, 0,
  385             .config_function = puc_config_siig
  386         },
  387 
  388         {   0x131f, 0x2042, 0xffff, 0,
  389             "SIIG Cyber 2P1S PCI 16C850 (20x family)",
  390             DEFAULT_RCLK,
  391             PUC_PORT_1S2P, 0x10, -1, 0,
  392             .config_function = puc_config_siig
  393         },
  394 
  395         {   0x131f, 0x2050, 0xffff, 0,
  396             "SIIG Cyber 4S PCI 16C550 (20x family)",
  397             DEFAULT_RCLK,
  398             PUC_PORT_4S, 0x10, 4, 0,
  399         },
  400 
  401         {   0x131f, 0x2051, 0xffff, 0,
  402             "SIIG Cyber 4S PCI 16C650 (20x family)",
  403             DEFAULT_RCLK,
  404             PUC_PORT_4S, 0x10, 4, 0,
  405         },
  406 
  407         {   0x131f, 0x2052, 0xffff, 0,
  408             "SIIG Cyber 4S PCI 16C850 (20x family)",
  409             DEFAULT_RCLK,
  410             PUC_PORT_4S, 0x10, 4, 0,
  411         },
  412 
  413         {   0x131f, 0x2060, 0xffff, 0,
  414             "SIIG Cyber 2S1P PCI 16C550 (20x family)",
  415             DEFAULT_RCLK,
  416             PUC_PORT_2S1P, 0x10, 4, 0,
  417         },
  418 
  419         {   0x131f, 0x2061, 0xffff, 0,
  420             "SIIG Cyber 2S1P PCI 16C650 (20x family)",
  421             DEFAULT_RCLK,
  422             PUC_PORT_2S1P, 0x10, 4, 0,
  423         },
  424 
  425         {   0x131f, 0x2062, 0xffff, 0,
  426             "SIIG Cyber 2S1P PCI 16C850 (20x family)",
  427             DEFAULT_RCLK,
  428             PUC_PORT_2S1P, 0x10, 4, 0,
  429         },
  430 
  431         {   0x131f, 0x2081, 0xffff, 0,
  432             "SIIG PS8000 8S PCI 16C650 (20x family)",
  433             DEFAULT_RCLK,
  434             PUC_PORT_8S, 0x10, -1, -1,
  435             .config_function = puc_config_siig
  436         },
  437 
  438         {   0x135c, 0x0010, 0xffff, 0,
  439             "Quatech QSC-100",
  440             -3, /* max 8x clock rate */
  441             PUC_PORT_4S, 0x14, 0, 8,
  442             .config_function = puc_config_quatech
  443         },
  444 
  445         {   0x135c, 0x0020, 0xffff, 0,
  446             "Quatech DSC-100",
  447             -1, /* max 2x clock rate */
  448             PUC_PORT_2S, 0x14, 0, 8,
  449             .config_function = puc_config_quatech
  450         },
  451 
  452         {   0x135c, 0x0030, 0xffff, 0,
  453             "Quatech DSC-200/300",
  454             -1, /* max 2x clock rate */
  455             PUC_PORT_2S, 0x14, 0, 8,
  456             .config_function = puc_config_quatech
  457         },
  458 
  459         {   0x135c, 0x0040, 0xffff, 0,
  460             "Quatech QSC-200/300",
  461             -3, /* max 8x clock rate */
  462             PUC_PORT_4S, 0x14, 0, 8,
  463             .config_function = puc_config_quatech
  464         },
  465 
  466         {   0x135c, 0x0050, 0xffff, 0,
  467             "Quatech ESC-100D",
  468             -3, /* max 8x clock rate */
  469             PUC_PORT_8S, 0x14, 0, 8,
  470             .config_function = puc_config_quatech
  471         },
  472 
  473         {   0x135c, 0x0060, 0xffff, 0,
  474             "Quatech ESC-100M",
  475             -3, /* max 8x clock rate */
  476             PUC_PORT_8S, 0x14, 0, 8,
  477             .config_function = puc_config_quatech
  478         },
  479 
  480         {   0x135c, 0x0170, 0xffff, 0,
  481             "Quatech QSCLP-100",
  482             -1, /* max 2x clock rate */
  483             PUC_PORT_4S, 0x18, 0, 8,
  484             .config_function = puc_config_quatech
  485         },
  486 
  487         {   0x135c, 0x0180, 0xffff, 0,
  488             "Quatech DSCLP-100",
  489             -1, /* max 3x clock rate */
  490             PUC_PORT_2S, 0x18, 0, 8,
  491             .config_function = puc_config_quatech
  492         },
  493 
  494         {   0x135c, 0x01b0, 0xffff, 0,
  495             "Quatech DSCLP-200/300",
  496             -1, /* max 2x clock rate */
  497             PUC_PORT_2S, 0x18, 0, 8,
  498             .config_function = puc_config_quatech
  499         },
  500 
  501         {   0x135c, 0x01e0, 0xffff, 0,
  502             "Quatech ESCLP-100",
  503             -3, /* max 8x clock rate */
  504             PUC_PORT_8S, 0x10, 0, 8,
  505             .config_function = puc_config_quatech
  506         },
  507 
  508         {   0x1393, 0x1040, 0xffff, 0,
  509             "Moxa Technologies, Smartio C104H/PCI",
  510             DEFAULT_RCLK * 8,
  511             PUC_PORT_4S, 0x18, 0, 8,
  512         },
  513 
  514         {   0x1393, 0x1041, 0xffff, 0,
  515             "Moxa Technologies, Smartio CP-104UL/PCI",
  516             DEFAULT_RCLK * 8,
  517             PUC_PORT_4S, 0x18, 0, 8,
  518         },
  519 
  520         {   0x1393, 0x1043, 0xffff, 0,
  521             "Moxa Technologies, Smartio CP-104EL/PCIe",
  522             DEFAULT_RCLK * 8,
  523             PUC_PORT_4S, 0x18, 0, 8,
  524         },
  525 
  526         {   0x1393, 0x1141, 0xffff, 0,
  527             "Moxa Technologies, Industio CP-114",
  528             DEFAULT_RCLK * 8,
  529             PUC_PORT_4S, 0x18, 0, 8,
  530         },
  531 
  532         {   0x1393, 0x1680, 0xffff, 0,
  533             "Moxa Technologies, C168H/PCI",
  534             DEFAULT_RCLK * 8,
  535             PUC_PORT_8S, 0x18, 0, 8,
  536         },
  537 
  538         {   0x1393, 0x1681, 0xffff, 0,
  539             "Moxa Technologies, C168U/PCI",
  540             DEFAULT_RCLK * 8,
  541             PUC_PORT_8S, 0x18, 0, 8,
  542         },
  543 
  544         {   0x1393, 0x1682, 0xffff, 0,
  545             "Moxa Technologies, CP-168EL/PCIe",
  546             DEFAULT_RCLK * 8,
  547             PUC_PORT_8S, 0x18, 0, 8,
  548         },
  549 
  550         {   0x13a8, 0x0158, 0xffff, 0,
  551             "Cronyx Omega2-PCI",
  552             DEFAULT_RCLK * 8,
  553             PUC_PORT_8S, 0x10, 0, -1,
  554             .config_function = puc_config_cronyx
  555         },
  556 
  557         {   0x1407, 0x0100, 0xffff, 0,
  558             "Lava Computers Dual Serial",
  559             DEFAULT_RCLK,
  560             PUC_PORT_2S, 0x10, 4, 0,
  561         },
  562 
  563         {   0x1407, 0x0101, 0xffff, 0,
  564             "Lava Computers Quatro A",
  565             DEFAULT_RCLK,
  566             PUC_PORT_2S, 0x10, 4, 0,
  567         },
  568 
  569         {   0x1407, 0x0102, 0xffff, 0,
  570             "Lava Computers Quatro B",
  571             DEFAULT_RCLK,
  572             PUC_PORT_2S, 0x10, 4, 0,
  573         },
  574 
  575         {   0x1407, 0x0120, 0xffff, 0,
  576             "Lava Computers Quattro-PCI A",
  577             DEFAULT_RCLK,
  578             PUC_PORT_2S, 0x10, 4, 0,
  579         },
  580 
  581         {   0x1407, 0x0121, 0xffff, 0,
  582             "Lava Computers Quattro-PCI B",
  583             DEFAULT_RCLK,
  584             PUC_PORT_2S, 0x10, 4, 0,
  585         },
  586 
  587         {   0x1407, 0x0180, 0xffff, 0,
  588             "Lava Computers Octo A",
  589             DEFAULT_RCLK,
  590             PUC_PORT_4S, 0x10, 4, 0,
  591         },
  592 
  593         {   0x1407, 0x0181, 0xffff, 0,
  594             "Lava Computers Octo B",
  595             DEFAULT_RCLK,
  596             PUC_PORT_4S, 0x10, 4, 0,
  597         },
  598 
  599         {   0x1409, 0x7268, 0xffff, 0,
  600             "Sunix SUN1888",
  601             0,
  602             PUC_PORT_2P, 0x10, 0, 8,
  603         },
  604 
  605         {   0x1409, 0x7168, 0xffff, 0,
  606             NULL,
  607             DEFAULT_RCLK * 8,
  608             PUC_PORT_NONSTANDARD, 0x10, -1, -1,
  609             .config_function = puc_config_timedia
  610         },
  611 
  612         /*
  613          * Boards with an Oxford Semiconductor chip.
  614          *
  615          * Oxford Semiconductor provides documentation for their chip at:
  616          * <URL:http://www.oxsemi.com/products/uarts/index.html>
  617          *
  618          * As sold by Kouwell <URL:http://www.kouwell.com/>.
  619          * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
  620          */
  621 
  622         {   0x1415, 0x9501, 0x131f, 0x2050,
  623             "SIIG Cyber 4 PCI 16550",
  624             DEFAULT_RCLK * 10,
  625             PUC_PORT_4S, 0x10, 0, 8,
  626         },
  627 
  628         {   0x1415, 0x9501, 0x131f, 0x2051,
  629             "SIIG Cyber 4S PCI 16C650 (20x family)",
  630             DEFAULT_RCLK * 10,
  631             PUC_PORT_4S, 0x10, 0, 8,
  632         },
  633 
  634         {   0x1415, 0x9501, 0xffff, 0,
  635             "Oxford Semiconductor OX16PCI954 UARTs",
  636             DEFAULT_RCLK,
  637             PUC_PORT_4S, 0x10, 0, 8,
  638         },
  639 
  640         {   0x1415, 0x950a, 0xffff, 0,
  641             "Oxford Semiconductor OX16PCI954 UARTs",
  642             DEFAULT_RCLK,
  643             PUC_PORT_4S, 0x10, 0, 8,
  644         },
  645 
  646         {   0x1415, 0x9511, 0xffff, 0,
  647             "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
  648             DEFAULT_RCLK,
  649             PUC_PORT_4S, 0x10, 0, 8,
  650         },
  651 
  652         {   0x1415, 0x9521, 0xffff, 0,
  653             "Oxford Semiconductor OX16PCI952 UARTs",
  654             DEFAULT_RCLK,
  655             PUC_PORT_2S, 0x10, 4, 0,
  656         },
  657 
  658         {   0x1415, 0x9538, 0xffff, 0,
  659             "Oxford Semiconductor OX16PCI958 UARTs",
  660             DEFAULT_RCLK * 10,
  661             PUC_PORT_8S, 0x18, 0, 8,
  662         },
  663 
  664         /*
  665          * Perle boards use Oxford Semiconductor chips, but they store the
  666          * Oxford Semiconductor device ID as a subvendor device ID and use
  667          * their own device IDs.
  668          */
  669 
  670         {   0x155f, 0x0331, 0xffff, 0,
  671             "Perle Speed4 LE",
  672             DEFAULT_RCLK * 8,
  673             PUC_PORT_4S, 0x10, 0, 8,
  674         },
  675 
  676         {   0x14d2, 0x8010, 0xffff, 0,
  677             "VScom PCI-100L",
  678             DEFAULT_RCLK * 8,
  679             PUC_PORT_1S, 0x14, 0, 0,
  680         },
  681 
  682         {   0x14d2, 0x8020, 0xffff, 0,
  683             "VScom PCI-200L",
  684             DEFAULT_RCLK * 8,
  685             PUC_PORT_2S, 0x14, 4, 0,
  686         },
  687 
  688         {   0x14d2, 0x8028, 0xffff, 0,
  689             "VScom 200Li",
  690             DEFAULT_RCLK,
  691             PUC_PORT_2S, 0x20, 0, 8,
  692         },
  693 
  694         /*
  695          * VScom (Titan?) PCI-800L.  More modern variant of the
  696          * PCI-800.  Uses 6 discrete 16550 UARTs, plus another
  697          * two of them obviously implemented as macro cells in
  698          * the ASIC.  This causes the weird port access pattern
  699          * below, where two of the IO port ranges each access
  700          * one of the ASIC UARTs, and a block of IO addresses
  701          * access the external UARTs.
  702          */
  703         {   0x14d2, 0x8080, 0xffff, 0,
  704             "Titan VScom PCI-800L",
  705             DEFAULT_RCLK * 8,
  706             PUC_PORT_8S, 0x14, -1, -1,
  707             .config_function = puc_config_titan
  708         },
  709 
  710         /*
  711          * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
  712          * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
  713          * device ID 3 and PCI device 1 device ID 4.
  714          */
  715         {   0x14d2, 0xa003, 0xffff, 0,
  716             "Titan PCI-800H",
  717             DEFAULT_RCLK * 8,
  718             PUC_PORT_4S, 0x10, 0, 8,
  719         },
  720         {   0x14d2, 0xa004, 0xffff, 0,
  721             "Titan PCI-800H",
  722             DEFAULT_RCLK * 8,
  723             PUC_PORT_4S, 0x10, 0, 8,
  724         },
  725 
  726         {   0x14d2, 0xa005, 0xffff, 0,
  727             "Titan PCI-200H",
  728             DEFAULT_RCLK * 8,
  729             PUC_PORT_2S, 0x10, 0, 8,
  730         },
  731 
  732         {   0x14d2, 0xe020, 0xffff, 0,
  733             "Titan VScom PCI-200HV2",
  734             DEFAULT_RCLK * 8,
  735             PUC_PORT_2S, 0x10, 4, 0,
  736         },
  737 
  738         {   0x14db, 0x2130, 0xffff, 0,
  739             "Avlab Technology, PCI IO 2S",
  740             DEFAULT_RCLK,
  741             PUC_PORT_2S, 0x10, 4, 0,
  742         },
  743 
  744         {   0x14db, 0x2150, 0xffff, 0,
  745             "Avlab Low Profile PCI 4 Serial",
  746             DEFAULT_RCLK,
  747             PUC_PORT_4S, 0x10, 4, 0,
  748         },
  749 
  750         {   0x14db, 0x2152, 0xffff, 0,
  751             "Avlab Low Profile PCI 4 Serial",
  752             DEFAULT_RCLK,
  753             PUC_PORT_4S, 0x10, 4, 0,
  754         },
  755 
  756         {   0x1592, 0x0781, 0xffff, 0,
  757             "Syba Tech Ltd. PCI-4S2P-550-ECP",
  758             DEFAULT_RCLK,
  759             PUC_PORT_4S1P, 0x10, 0, -1,
  760             .config_function = puc_config_syba
  761         },
  762 
  763         {   0x6666, 0x0001, 0xffff, 0,
  764             "Decision Computer Inc, PCCOM 4-port serial",
  765             DEFAULT_RCLK,
  766             PUC_PORT_4S, 0x1c, 0, 8,
  767         },
  768 
  769         {   0x6666, 0x0002, 0xffff, 0,
  770             "Decision Computer Inc, PCCOM 8-port serial",
  771             DEFAULT_RCLK,
  772             PUC_PORT_8S, 0x1c, 0, 8,
  773         },
  774 
  775         {   0x6666, 0x0004, 0xffff, 0,
  776             "PCCOM dual port RS232/422/485",
  777             DEFAULT_RCLK,
  778             PUC_PORT_2S, 0x1c, 0, 8,
  779         },
  780 
  781         {   0x9710, 0x9815, 0xffff, 0,
  782             "NetMos NM9815 Dual 1284 Printer port", 
  783             0,
  784             PUC_PORT_2P, 0x10, 8, 0,
  785         }, 
  786 
  787         /*
  788          * This is more specific than the generic NM9835 entry that follows, and
  789          * is placed here to _prevent_ puc from claiming this single port card.
  790          *
  791          * uart(4) will claim this device.
  792          */
  793         {   0x9710, 0x9835, 0x1000, 1,
  794             "NetMos NM9835 based 1-port serial",
  795             DEFAULT_RCLK,
  796             PUC_PORT_1S, 0x10, 4, 0,
  797         },
  798 
  799         {   0x9710, 0x9835, 0x1000, 2,
  800             "NetMos NM9835 based 2-port serial",
  801             DEFAULT_RCLK,
  802             PUC_PORT_2S, 0x10, 4, 0,
  803         },
  804 
  805         {   0x9710, 0x9835, 0xffff, 0,
  806             "NetMos NM9835 Dual UART and 1284 Printer port",
  807             DEFAULT_RCLK,
  808             PUC_PORT_2S1P, 0x10, 4, 0,
  809         },
  810 
  811         {   0x9710, 0x9845, 0x1000, 0x0006,
  812             "NetMos NM9845 6 Port UART",
  813             DEFAULT_RCLK,
  814             PUC_PORT_6S, 0x10, 4, 0,
  815         },
  816 
  817         {   0x9710, 0x9845, 0xffff, 0,
  818             "NetMos NM9845 Quad UART and 1284 Printer port",
  819             DEFAULT_RCLK,
  820             PUC_PORT_4S1P, 0x10, 4, 0,
  821         },
  822 
  823         {   0x9710, 0x9865, 0xa000, 0x3002,
  824             "NetMos NM9865 Dual UART",
  825             DEFAULT_RCLK,
  826             PUC_PORT_2S, 0x10, 4, 0,
  827         },
  828 
  829         {   0x9710, 0x9865, 0xa000, 0x3003,
  830             "NetMos NM9865 Triple UART",
  831             DEFAULT_RCLK,
  832             PUC_PORT_3S, 0x10, 4, 0,
  833         },
  834 
  835         {   0x9710, 0x9865, 0xa000, 0x3004,
  836             "NetMos NM9865 Quad UART",
  837             DEFAULT_RCLK,
  838             PUC_PORT_4S, 0x10, 4, 0,0
  839         },
  840 
  841         {   0x9710, 0x9865, 0xa000, 0x3011,
  842             "NetMos NM9865 Single UART and 1284 Printer port",
  843             DEFAULT_RCLK,
  844             PUC_PORT_1S1P, 0x10, 4, 0,
  845         },
  846 
  847         {   0x9710, 0x9865, 0xa000, 0x3012,
  848             "NetMos NM9865 Dual UART and 1284 Printer port",
  849             DEFAULT_RCLK,
  850             PUC_PORT_2S1P, 0x10, 4, 0,
  851         },
  852 
  853         {   0x9710, 0x9865, 0xa000, 0x3020,
  854             "NetMos NM9865 Dual 1284 Printer port",
  855             DEFAULT_RCLK,
  856             PUC_PORT_2P, 0x10, 4, 0,
  857         },
  858 
  859         {   0xb00c, 0x021c, 0xffff, 0,
  860             "IC Book Labs Gunboat x4 Lite",
  861             DEFAULT_RCLK,
  862             PUC_PORT_4S, 0x10, 0, 8,
  863             .config_function = puc_config_icbook
  864         },
  865 
  866         {   0xb00c, 0x031c, 0xffff, 0,
  867             "IC Book Labs Gunboat x4 Pro",
  868             DEFAULT_RCLK,
  869             PUC_PORT_4S, 0x10, 0, 8,
  870             .config_function = puc_config_icbook
  871         },
  872 
  873         {   0xb00c, 0x041c, 0xffff, 0,
  874             "IC Book Labs Ironclad x8 Lite",
  875             DEFAULT_RCLK,
  876             PUC_PORT_8S, 0x10, 0, 8,
  877             .config_function = puc_config_icbook
  878         },
  879 
  880         {   0xb00c, 0x051c, 0xffff, 0,
  881             "IC Book Labs Ironclad x8 Pro",
  882             DEFAULT_RCLK,
  883             PUC_PORT_8S, 0x10, 0, 8,
  884             .config_function = puc_config_icbook
  885         },
  886 
  887         {   0xb00c, 0x081c, 0xffff, 0,
  888             "IC Book Labs Dreadnought x16 Pro",
  889             DEFAULT_RCLK * 8,
  890             PUC_PORT_16S, 0x10, 0, 8,
  891             .config_function = puc_config_icbook
  892         },
  893 
  894         {   0xb00c, 0x091c, 0xffff, 0,
  895             "IC Book Labs Dreadnought x16 Lite",
  896             DEFAULT_RCLK,
  897             PUC_PORT_16S, 0x10, 0, 8,
  898             .config_function = puc_config_icbook
  899         },
  900 
  901         {   0xb00c, 0x0a1c, 0xffff, 0,
  902             "IC Book Labs Gunboat x2 Low Profile",
  903             DEFAULT_RCLK,
  904             PUC_PORT_2S, 0x10, 0, 8,
  905         },
  906 
  907         {   0xb00c, 0x0b1c, 0xffff, 0,
  908             "IC Book Labs Gunboat x4 Low Profile",
  909             DEFAULT_RCLK,
  910             PUC_PORT_4S, 0x10, 0, 8,
  911             .config_function = puc_config_icbook
  912         },
  913 
  914         { 0xffff, 0, 0xffff, 0, NULL, 0 }
  915 };
  916 
  917 static int
  918 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
  919     intptr_t *res)
  920 {
  921         switch (cmd) {
  922         case PUC_CFG_GET_OFS:
  923                 *res = 8 * (port & 1);
  924                 return (0);
  925         case PUC_CFG_GET_RID:
  926                 *res = 0x14 + (port >> 1) * 4;
  927                 return (0);
  928         default:
  929                 break;
  930         }
  931         return (ENXIO);
  932 }
  933 
  934 static int
  935 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
  936     intptr_t *res)
  937 {
  938         if (cmd == PUC_CFG_GET_OFS) {
  939                 *res = port * 0x200;
  940                 return (0);
  941         }
  942         return (ENXIO);
  943 }
  944 
  945 static int
  946 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
  947     intptr_t *res)
  948 {
  949         const struct puc_cfg *cfg = sc->sc_cfg;
  950 
  951         if (cmd == PUC_CFG_GET_OFS) {
  952                 if (cfg->subdevice == 0x1282)           /* Everest SP */
  953                         port <<= 1;
  954                 else if (cfg->subdevice == 0x104b)      /* Maestro SP2 */
  955                         port = (port == 3) ? 4 : port;
  956                 *res = port * 8 + ((port > 2) ? 0x18 : 0);
  957                 return (0);
  958         }
  959         return (ENXIO);
  960 }
  961 
  962 static int
  963 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
  964     intptr_t *res)
  965 {
  966         if (cmd == PUC_CFG_GET_ILR) {
  967                 *res = PUC_ILR_DIGI;
  968                 return (0);
  969         }
  970         return (ENXIO);
  971 }
  972 
  973 static int
  974 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
  975     intptr_t *res)
  976 {
  977         const struct puc_cfg *cfg = sc->sc_cfg;
  978         struct puc_bar *bar;
  979         uint8_t v0, v1;
  980 
  981         switch (cmd) {
  982         case PUC_CFG_SETUP:
  983                 /*
  984                  * Check if the scratchpad register is enabled or if the
  985                  * interrupt status and options registers are active.
  986                  */
  987                 bar = puc_get_bar(sc, cfg->rid);
  988                 if (bar == NULL)
  989                         return (ENXIO);
  990                 /* Set DLAB in the LCR register of UART 0. */
  991                 bus_write_1(bar->b_res, 3, 0x80);
  992                 /* Write 0 to the SPR register of UART 0. */
  993                 bus_write_1(bar->b_res, 7, 0);
  994                 /* Read back the contents of the SPR register of UART 0. */
  995                 v0 = bus_read_1(bar->b_res, 7);
  996                 /* Write a specific value to the SPR register of UART 0. */
  997                 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
  998                 /* Read back the contents of the SPR register of UART 0. */
  999                 v1 = bus_read_1(bar->b_res, 7);
 1000                 /* Clear DLAB in the LCR register of UART 0. */
 1001                 bus_write_1(bar->b_res, 3, 0);
 1002                 /* Save the two values read-back from the SPR register. */
 1003                 sc->sc_cfg_data = (v0 << 8) | v1;
 1004                 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
 1005                         /*
 1006                          * The SPR register echoed the two values written
 1007                          * by us. This means that the SPAD jumper is set.
 1008                          */
 1009                         device_printf(sc->sc_dev, "warning: extra features "
 1010                             "not usable -- SPAD compatibility enabled\n");
 1011                         return (0);
 1012                 }
 1013                 if (v0 != 0) {
 1014                         /*
 1015                          * The first value doesn't match. This can only mean
 1016                          * that the SPAD jumper is not set and that a non-
 1017                          * standard fixed clock multiplier jumper is set.
 1018                          */
 1019                         if (bootverbose)
 1020                                 device_printf(sc->sc_dev, "fixed clock rate "
 1021                                     "multiplier of %d\n", 1 << v0);
 1022                         if (v0 < -cfg->clock)
 1023                                 device_printf(sc->sc_dev, "warning: "
 1024                                     "suboptimal fixed clock rate multiplier "
 1025                                     "setting\n");
 1026                         return (0);
 1027                 }
 1028                 /*
 1029                  * The first value matched, but the second didn't. We know
 1030                  * that the SPAD jumper is not set. We also know that the
 1031                  * clock rate multiplier is software controlled *and* that
 1032                  * we just programmed it to the maximum allowed.
 1033                  */
 1034                 if (bootverbose)
 1035                         device_printf(sc->sc_dev, "clock rate multiplier of "
 1036                             "%d selected\n", 1 << -cfg->clock);
 1037                 return (0);
 1038         case PUC_CFG_GET_CLOCK:
 1039                 v0 = (sc->sc_cfg_data >> 8) & 0xff;
 1040                 v1 = sc->sc_cfg_data & 0xff;
 1041                 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
 1042                         /*
 1043                          * XXX With the SPAD jumper applied, there's no
 1044                          * easy way of knowing if there's also a clock
 1045                          * rate multiplier jumper installed. Let's hope
 1046                          * not...
 1047                          */
 1048                         *res = DEFAULT_RCLK;
 1049                 } else if (v0 == 0) {
 1050                         /*
 1051                          * No clock rate multiplier jumper installed,
 1052                          * so we programmed the board with the maximum
 1053                          * multiplier allowed as given to us in the
 1054                          * clock field of the config record (negated).
 1055                          */
 1056                         *res = DEFAULT_RCLK << -cfg->clock;
 1057                 } else
 1058                         *res = DEFAULT_RCLK << v0;
 1059                 return (0);
 1060         case PUC_CFG_GET_ILR:
 1061                 v0 = (sc->sc_cfg_data >> 8) & 0xff;
 1062                 v1 = sc->sc_cfg_data & 0xff;
 1063                 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
 1064                     ? PUC_ILR_NONE : PUC_ILR_QUATECH;
 1065                 return (0);
 1066         default:
 1067                 break;
 1068         }
 1069         return (ENXIO);
 1070 }
 1071 
 1072 static int
 1073 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
 1074     intptr_t *res)
 1075 {
 1076         static int base[] = { 0x251, 0x3f0, 0 };
 1077         const struct puc_cfg *cfg = sc->sc_cfg;
 1078         struct puc_bar *bar;
 1079         int efir, idx, ofs;
 1080         uint8_t v;
 1081 
 1082         switch (cmd) {
 1083         case PUC_CFG_SETUP:
 1084                 bar = puc_get_bar(sc, cfg->rid);
 1085                 if (bar == NULL)
 1086                         return (ENXIO);
 1087 
 1088                 /* configure both W83877TFs */
 1089                 bus_write_1(bar->b_res, 0x250, 0x89);
 1090                 bus_write_1(bar->b_res, 0x3f0, 0x87);
 1091                 bus_write_1(bar->b_res, 0x3f0, 0x87);
 1092                 idx = 0;
 1093                 while (base[idx] != 0) {
 1094                         efir = base[idx];
 1095                         bus_write_1(bar->b_res, efir, 0x09);
 1096                         v = bus_read_1(bar->b_res, efir + 1);
 1097                         if ((v & 0x0f) != 0x0c)
 1098                                 return (ENXIO);
 1099                         bus_write_1(bar->b_res, efir, 0x16);
 1100                         v = bus_read_1(bar->b_res, efir + 1);
 1101                         bus_write_1(bar->b_res, efir, 0x16);
 1102                         bus_write_1(bar->b_res, efir + 1, v | 0x04);
 1103                         bus_write_1(bar->b_res, efir, 0x16);
 1104                         bus_write_1(bar->b_res, efir + 1, v & ~0x04);
 1105                         ofs = base[idx] & 0x300;
 1106                         bus_write_1(bar->b_res, efir, 0x23);
 1107                         bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
 1108                         bus_write_1(bar->b_res, efir, 0x24);
 1109                         bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
 1110                         bus_write_1(bar->b_res, efir, 0x25);
 1111                         bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
 1112                         bus_write_1(bar->b_res, efir, 0x17);
 1113                         bus_write_1(bar->b_res, efir + 1, 0x03);
 1114                         bus_write_1(bar->b_res, efir, 0x28);
 1115                         bus_write_1(bar->b_res, efir + 1, 0x43);
 1116                         idx++;
 1117                 }
 1118                 bus_write_1(bar->b_res, 0x250, 0xaa);
 1119                 bus_write_1(bar->b_res, 0x3f0, 0xaa);
 1120                 return (0);
 1121         case PUC_CFG_GET_OFS:
 1122                 switch (port) {
 1123                 case 0:
 1124                         *res = 0x2f8;
 1125                         return (0);
 1126                 case 1:
 1127                         *res = 0x2e8;
 1128                         return (0);
 1129                 case 2:
 1130                         *res = 0x3f8;
 1131                         return (0);
 1132                 case 3:
 1133                         *res = 0x3e8;
 1134                         return (0);
 1135                 case 4:
 1136                         *res = 0x278;
 1137                         return (0);
 1138                 }
 1139                 break;
 1140         default:
 1141                 break;
 1142         }
 1143         return (ENXIO);
 1144 }
 1145 
 1146 static int
 1147 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
 1148     intptr_t *res)
 1149 {
 1150         const struct puc_cfg *cfg = sc->sc_cfg;
 1151 
 1152         switch (cmd) {
 1153         case PUC_CFG_GET_OFS:
 1154                 if (cfg->ports == PUC_PORT_8S) {
 1155                         *res = (port > 4) ? 8 * (port - 4) : 0;
 1156                         return (0);
 1157                 }
 1158                 break;
 1159         case PUC_CFG_GET_RID:
 1160                 if (cfg->ports == PUC_PORT_8S) {
 1161                         *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
 1162                         return (0);
 1163                 }
 1164                 if (cfg->ports == PUC_PORT_2S1P) {
 1165                         switch (port) {
 1166                         case 0: *res = 0x10; return (0);
 1167                         case 1: *res = 0x14; return (0);
 1168                         case 2: *res = 0x1c; return (0);
 1169                         }
 1170                 }
 1171                 break;
 1172         default:
 1173                 break;
 1174         }
 1175         return (ENXIO);
 1176 }
 1177 
 1178 static int
 1179 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
 1180     intptr_t *res)
 1181 {
 1182         static uint16_t dual[] = {
 1183             0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 1184             0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 
 1185             0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 
 1186             0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 1187             0xD079, 0
 1188         };
 1189         static uint16_t quad[] = {
 1190             0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 
 1191             0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 
 1192             0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 1193             0xB157, 0
 1194         };
 1195         static uint16_t octa[] = {
 1196             0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 
 1197             0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 1198         };
 1199         static struct {
 1200                 int ports;
 1201                 uint16_t *ids;
 1202         } subdevs[] = {
 1203             { 2, dual },
 1204             { 4, quad },
 1205             { 8, octa },
 1206             { 0, NULL }
 1207         };
 1208         static char desc[64];
 1209         int dev, id;
 1210         uint16_t subdev;
 1211 
 1212         switch (cmd) {
 1213         case PUC_CFG_GET_DESC:
 1214                 snprintf(desc, sizeof(desc),
 1215                     "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
 1216                 *res = (intptr_t)desc;
 1217                 return (0);
 1218         case PUC_CFG_GET_NPORTS:
 1219                 subdev = pci_get_subdevice(sc->sc_dev);
 1220                 dev = 0;
 1221                 while (subdevs[dev].ports != 0) {
 1222                         id = 0;
 1223                         while (subdevs[dev].ids[id] != 0) {
 1224                                 if (subdev == subdevs[dev].ids[id]) {
 1225                                         sc->sc_cfg_data = subdevs[dev].ports;
 1226                                         *res = sc->sc_cfg_data;
 1227                                         return (0);
 1228                                 }
 1229                                 id++;
 1230                         }
 1231                         dev++;
 1232                 }
 1233                 return (ENXIO);
 1234         case PUC_CFG_GET_OFS:
 1235                 *res = (port == 1 || port == 3) ? 8 : 0;
 1236                 return (0);
 1237         case PUC_CFG_GET_RID:
 1238                 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
 1239                 return (0);
 1240         case PUC_CFG_GET_TYPE:
 1241                 *res = PUC_TYPE_SERIAL;
 1242                 return (0);
 1243         default:
 1244                 break;
 1245         }
 1246         return (ENXIO);
 1247 }
 1248 
 1249 static int
 1250 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
 1251     intptr_t *res)
 1252 {
 1253         switch (cmd) {
 1254         case PUC_CFG_GET_OFS:
 1255                 *res = (port < 3) ? 0 : (port - 2) << 3;
 1256                 return (0);
 1257         case PUC_CFG_GET_RID:
 1258                 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
 1259                 return (0);
 1260         default:
 1261                 break;
 1262         }
 1263         return (ENXIO);
 1264 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/puc/pucdata.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/puc/pucdata.c
