1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
3 /* $FreeBSD$ */
4 #ifndef __ICP_QAT_FW_LOADER_HANDLE_H__
5 #define __ICP_QAT_FW_LOADER_HANDLE_H__
6 #include "icp_qat_uclo.h"
7
8 struct icp_qat_fw_loader_ae_data {
9 unsigned int state;
10 unsigned int ustore_size;
11 unsigned int free_addr;
12 unsigned int free_size;
13 unsigned int live_ctx_mask;
14 };
15
16 struct icp_qat_fw_loader_hal_handle {
17 struct icp_qat_fw_loader_ae_data aes[ICP_QAT_UCLO_MAX_AE];
18 unsigned int ae_mask;
19 unsigned int admin_ae_mask;
20 unsigned int slice_mask;
21 unsigned int revision_id;
22 unsigned int ae_max_num;
23 unsigned int upc_mask;
24 unsigned int max_ustore;
25 };
26
27 struct icp_qat_fw_loader_handle {
28 struct icp_qat_fw_loader_hal_handle *hal_handle;
29 struct adf_accel_dev *accel_dev;
30 device_t pci_dev;
31 void *obj_handle;
32 void *sobj_handle;
33 void *mobj_handle;
34 bool fw_auth;
35 unsigned int cfg_ae_mask;
36 rman_res_t hal_sram_size;
37 struct resource *hal_sram_addr_v;
38 unsigned int hal_sram_offset;
39 struct resource *hal_misc_addr_v;
40 uintptr_t hal_cap_g_ctl_csr_addr_v;
41 uintptr_t hal_cap_ae_xfer_csr_addr_v;
42 uintptr_t hal_cap_ae_local_csr_addr_v;
43 uintptr_t hal_ep_csr_addr_v;
44 };
45
46 struct icp_firml_dram_desc {
47 struct bus_dmamem dram_mem;
48
49 struct resource *dram_base_addr;
50 void *dram_base_addr_v;
51 bus_addr_t dram_bus_addr;
52 u64 dram_size;
53 };
54 #endif
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