icp_qat_fw_init_admin.h

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    1 /* SPDX-License-Identifier: BSD-3-Clause */
    2 /* Copyright(c) 2007-2022 Intel Corporation */
    3 /* $FreeBSD$ */
    4 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_
    5 #define _ICP_QAT_FW_INIT_ADMIN_H_
    6 
    7 #include "icp_qat_fw.h"
    8 
    9 enum icp_qat_fw_init_admin_cmd_id {
   10         ICP_QAT_FW_INIT_ME = 0,
   11         ICP_QAT_FW_TRNG_ENABLE = 1,
   12         ICP_QAT_FW_TRNG_DISABLE = 2,
   13         ICP_QAT_FW_CONSTANTS_CFG = 3,
   14         ICP_QAT_FW_STATUS_GET = 4,
   15         ICP_QAT_FW_COUNTERS_GET = 5,
   16         ICP_QAT_FW_LOOPBACK = 6,
   17         ICP_QAT_FW_HEARTBEAT_SYNC = 7,
   18         ICP_QAT_FW_HEARTBEAT_GET = 8,
   19         ICP_QAT_FW_COMP_CAPABILITY_GET = 9,
   20         ICP_QAT_FW_CRYPTO_CAPABILITY_GET = 10,
   21         ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13,
   22         ICP_QAT_FW_RL_SLA_CONFIG = 14,
   23         ICP_QAT_FW_RL_INIT = 15,
   24         ICP_QAT_FW_RL_DU_START = 16,
   25         ICP_QAT_FW_RL_DU_STOP = 17,
   26         ICP_QAT_FW_TIMER_GET = 19,
   27         ICP_QAT_FW_CNV_STATS_GET = 20,
   28         ICP_QAT_FW_PKE_REPLAY_STATS_GET = 21
   29 };
   30 
   31 enum icp_qat_fw_init_admin_resp_status {
   32         ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
   33         ICP_QAT_FW_INIT_RESP_STATUS_FAIL = 1,
   34         ICP_QAT_FW_INIT_RESP_STATUS_UNSUPPORTED = 4
   35 };
   36 
   37 enum icp_qat_fw_cnv_error_type {
   38         CNV_ERR_TYPE_NO_ERROR = 0,
   39         CNV_ERR_TYPE_CHECKSUM_ERROR,
   40         CNV_ERR_TYPE_DECOMP_PRODUCED_LENGTH_ERROR,
   41         CNV_ERR_TYPE_DECOMPRESSION_ERROR,
   42         CNV_ERR_TYPE_TRANSLATION_ERROR,
   43         CNV_ERR_TYPE_DECOMP_CONSUMED_LENGTH_ERROR,
   44         CNV_ERR_TYPE_UNKNOWN_ERROR
   45 };
   46 
   47 #define CNV_ERROR_TYPE_GET(latest_error)                                       \
   48         ({                                                                     \
   49                 __typeof__(latest_error) _lerror = latest_error;               \
   50                 (_lerror >> 12) > CNV_ERR_TYPE_UNKNOWN_ERROR ?                 \
   51                     CNV_ERR_TYPE_UNKNOWN_ERROR :                               \
   52                     (enum icp_qat_fw_cnv_error_type)(_lerror >> 12);           \
   53         })
   54 #define CNV_ERROR_LENGTH_DELTA_GET(latest_error)                               \
   55         ({                                                                     \
   56                 __typeof__(latest_error) _lerror = latest_error;               \
   57                 ((s16)((_lerror & 0x0FFF) | (_lerror & 0x0800 ? 0xF000 : 0))); \
   58         })
   59 #define CNV_ERROR_DECOMP_STATUS_GET(latest_error) ((s8)(latest_error & 0xFF))
   60 
   61 struct icp_qat_fw_init_admin_req {
   62         u16 init_cfg_sz;
   63         u8 resrvd1;
   64         u8 cmd_id;
   65         u32 max_req_duration;
   66         u64 opaque_data;
   67 
   68         union {
   69                 /* ICP_QAT_FW_INIT_ME */
   70                 struct {
   71                         u64 resrvd2;
   72                         u16 ibuf_size_in_kb;
   73                         u16 resrvd3;
   74                         u32 resrvd4;
   75                 };
   76                 /* ICP_QAT_FW_CONSTANTS_CFG */
   77                 struct {
   78                         u64 init_cfg_ptr;
   79                         u64 resrvd5;
   80                 };
   81                 /* ICP_QAT_FW_HEARTBEAT_TIMER_SET */
   82                 struct {
   83                         u64 hb_cfg_ptr;
   84                         u32 heartbeat_ticks;
   85                         u32 resrvd6;
   86                 };
   87                 /* ICP_QAT_FW_RL_SLA_CONFIG */
   88                 struct {
   89                         u32 credit_per_sla;
   90                         u8 service_id;
   91                         u8 vf_id;
   92                         u8 resrvd7;
   93                         u8 resrvd8;
   94                         u32 resrvd9;
   95                         u32 resrvd10;
   96                 };
   97                 /* ICP_QAT_FW_RL_INIT */
   98                 struct {
   99                         u32 rl_period;
  100                         u8 config;
  101                         u8 resrvd11;
  102                         u8 num_me;
  103                         u8 resrvd12;
  104                         u8 pke_svc_arb_map;
  105                         u8 bulk_crypto_svc_arb_map;
  106                         u8 compression_svc_arb_map;
  107                         u8 resrvd13;
  108                         u32 resrvd14;
  109                 };
  110                 /* ICP_QAT_FW_RL_DU_STOP */
  111                 struct {
  112                         u64 cfg_ptr;
  113                         u32 resrvd15;
  114                         u32 resrvd16;
  115                 };
  116         };
  117 } __packed;
  118 
  119 struct icp_qat_fw_init_admin_resp {
  120         u8 flags;
  121         u8 resrvd1;
  122         u8 status;
  123         u8 cmd_id;
  124         union {
  125                 u32 resrvd2;
  126                 u32 ras_event_count;
  127                 /* ICP_QAT_FW_STATUS_GET */
  128                 struct {
  129                         u16 version_minor_num;
  130                         u16 version_major_num;
  131                 };
  132                 /* ICP_QAT_FW_COMP_CAPABILITY_GET */
  133                 u32 extended_features;
  134                 /* ICP_QAT_FW_CNV_STATS_GET */
  135                 struct {
  136                         u16 error_count;
  137                         u16 latest_error;
  138                 };
  139         };
  140         u64 opaque_data;
  141         union {
  142                 u32 resrvd3[4];
  143                 /* ICP_QAT_FW_STATUS_GET */
  144                 struct {
  145                         u32 version_patch_num;
  146                         u8 context_id;
  147                         u8 ae_id;
  148                         u16 resrvd4;
  149                         u64 resrvd5;
  150                 };
  151                 /* ICP_QAT_FW_COMP_CAPABILITY_GET */
  152                 struct {
  153                         u16 compression_algos;
  154                         u16 checksum_algos;
  155                         u32 deflate_capabilities;
  156                         u32 resrvd6;
  157                         u32 deprecated;
  158                 };
  159                 /* ICP_QAT_FW_CRYPTO_CAPABILITY_GET */
  160                 struct {
  161                         u32 cipher_algos;
  162                         u32 hash_algos;
  163                         u16 keygen_algos;
  164                         u16 other;
  165                         u16 public_key_algos;
  166                         u16 prime_algos;
  167                 };
  168                 /* ICP_QAT_FW_RL_DU_STOP */
  169                 struct {
  170                         u32 resrvd7;
  171                         u8 granularity;
  172                         u8 resrvd8;
  173                         u16 resrvd9;
  174                         u32 total_du_time;
  175                         u32 resrvd10;
  176                 };
  177                 /* ICP_QAT_FW_TIMER_GET  */
  178                 struct {
  179                         u64 timestamp;
  180                         u64 resrvd11;
  181                 };
  182                 /* ICP_QAT_FW_COUNTERS_GET */
  183                 struct {
  184                         u64 req_rec_count;
  185                         u64 resp_sent_count;
  186                 };
  187                 /* ICP_QAT_FW_PKE_REPLAY_STATS_GET */
  188                 struct {
  189                         u32 successful_count;
  190                         u32 unsuccessful_count;
  191                         u64 resrvd12;
  192                 };
  193         };
  194 } __packed;
  195 
  196 enum icp_qat_fw_init_admin_init_flag { ICP_QAT_FW_INIT_FLAG_PKE_DISABLED = 0 };
  197 
  198 struct icp_qat_fw_init_admin_hb_cnt {
  199         u16 resp_heartbeat_cnt;
  200         u16 req_heartbeat_cnt;
  201 };
  202 
  203 #define ICP_QAT_FW_COMN_HEARTBEAT_OK 0
  204 #define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1
  205 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0
  206 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1
  207 #define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE
  208 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t)                          \
  209         ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags)
  210 
  211 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val)                     \
  212         ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val)
  213 
  214 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags)                              \
  215         QAT_FIELD_GET(flags,                                                   \
  216                       ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS,                   \
  217                       ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK)
  218 #endif

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FreeBSD/Linux Kernel Cross Reference sys/dev/qat/include/icp_qat_fw_init_admin.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/qat/include/icp_qat_fw_init_admin.h