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sys/dev/qat/qat_api/firmware/include/icp_qat_hw.h
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1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 /** 5 ***************************************************************************** 6 * @file icp_qat_hw.h 7 * @defgroup icp_qat_hw_defs ICP QAT HW definitions 8 * @ingroup icp_qat_hw 9 * @description 10 * This file documents definitions for the QAT HW 11 * 12 *****************************************************************************/ 13 14 #ifndef _ICP_QAT_HW_H_ 15 #define _ICP_QAT_HW_H_ 16 17 /* 18 ****************************************************************************** 19 * Include public/global header files 20 ****************************************************************************** 21 */ 22 23 /* ========================================================================= */ 24 /* AccelerationEngine */ 25 /* ========================================================================= */ 26 27 typedef enum { 28 ICP_QAT_HW_AE_0 = 0, /*!< ID of AE0 */ 29 ICP_QAT_HW_AE_1 = 1, /*!< ID of AE1 */ 30 ICP_QAT_HW_AE_2 = 2, /*!< ID of AE2 */ 31 ICP_QAT_HW_AE_3 = 3, /*!< ID of AE3 */ 32 ICP_QAT_HW_AE_4 = 4, /*!< ID of AE4 */ 33 ICP_QAT_HW_AE_5 = 5, /*!< ID of AE5 */ 34 ICP_QAT_HW_AE_6 = 6, /*!< ID of AE6 */ 35 ICP_QAT_HW_AE_7 = 7, /*!< ID of AE7 */ 36 ICP_QAT_HW_AE_8 = 8, /*!< ID of AE8 */ 37 ICP_QAT_HW_AE_9 = 9, /*!< ID of AE9 */ 38 ICP_QAT_HW_AE_10 = 10, /*!< ID of AE10 */ 39 ICP_QAT_HW_AE_11 = 11, /*!< ID of AE11 */ 40 ICP_QAT_HW_AE_12 = 12, /*!< ID of AE12 */ 41 ICP_QAT_HW_AE_13 = 13, /*!< ID of AE13 */ 42 ICP_QAT_HW_AE_14 = 14, /*!< ID of AE14 */ 43 ICP_QAT_HW_AE_15 = 15, /*!< ID of AE15 */ 44 ICP_QAT_HW_AE_DELIMITER = 16 /**< Delimiter type */ 45 } icp_qat_hw_ae_id_t; 46 47 /* ========================================================================= */ 48 /* QAT */ 49 /* ========================================================================= */ 50 51 typedef enum { 52 ICP_QAT_HW_QAT_0 = 0, /*!< ID of QAT0 */ 53 ICP_QAT_HW_QAT_1 = 1, /*!< ID of QAT1 */ 54 ICP_QAT_HW_QAT_2 = 2, /*!< ID of QAT2 */ 55 ICP_QAT_HW_QAT_3 = 3, /*!< ID of QAT3 */ 56 ICP_QAT_HW_QAT_4 = 4, /*!< ID of QAT4 */ 57 ICP_QAT_HW_QAT_5 = 5, /*!< ID of QAT5 */ 58 ICP_QAT_HW_QAT_DELIMITER = 6 /**< Delimiter type */ 59 } icp_qat_hw_qat_id_t; 60 61 /* ========================================================================= */ 62 /* AUTH SLICE */ 63 /* ========================================================================= */ 64 65 /** 66 ***************************************************************************** 67 * @ingroup icp_qat_hw_defs 68 * Supported Authentication Algorithm types 69 * @description 70 * Enumeration which is used to define the authenticate algorithms 71 * 72 *****************************************************************************/ 73 74 typedef enum { 75 ICP_QAT_HW_AUTH_ALGO_NULL = 0, /*!< Null hashing */ 76 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, /*!< SHA1 hashing */ 77 ICP_QAT_HW_AUTH_ALGO_MD5 = 2, /*!< MD5 hashing */ 78 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, /*!< SHA-224 hashing */ 79 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, /*!< SHA-256 hashing */ 80 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, /*!< SHA-384 hashing */ 81 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, /*!< SHA-512 hashing */ 82 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, /*!< AES-XCBC-MAC hashing */ 83 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, /*!< AES-CBC-MAC hashing */ 84 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, /*!< AES F9 hashing */ 85 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, /*!< Galois 128 bit hashing */ 86 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, /*!< Galois 64 hashing */ 87 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, /*!< Kasumi F9 hashing */ 88 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, /*!< UIA2/SNOW_3G F9 hashing */ 89 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 90 14, /*!< 128_EIA3/ZUC_3G hashing */ 91 ICP_QAT_HW_AUTH_ALGO_SM3 = 15, /*!< SM3 hashing */ 92 ICP_QAT_HW_AUTH_ALGO_SHA3_224 = 16, /*!< SHA3-224 hashing */ 93 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, /*!< SHA3-256 hashing */ 94 ICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18, /*!< SHA3-384 hashing */ 95 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, /*!< SHA3-512 hashing */ 96 ICP_QAT_HW_AUTH_RESERVED_4 = 20, /*!< Reserved */ 97 ICP_QAT_HW_AUTH_RESERVED_5 = 21, /*!< Reserved */ 98 ICP_QAT_HW_AUTH_ALGO_POLY = 22, /*!< POLY hashing */ 99 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 23 /**< Delimiter type */ 100 } icp_qat_hw_auth_algo_t; 101 102 /** 103 ***************************************************************************** 104 * @ingroup icp_qat_hw_defs 105 * Definition of the supported Authentication modes 106 * @description 107 * Enumeration which is used to define the authentication slice modes. 108 * The concept of modes is very specific to the QAT implementation. Its 109 * main use is differentiate how the algorithms are used i.e. mode0 SHA1 110 * will configure the QAT Auth Slice to do plain SHA1 hashing while mode1 111 * configures it to do SHA1 HMAC with precomputes and mode2 sets up the 112 * slice to do SHA1 HMAC with no precomputes (uses key directly) 113 * 114 * @Note 115 * Only some algorithms are valid in some of the modes. If you dont know 116 * what you are doing then refer back to the HW documentation 117 * 118 *****************************************************************************/ 119 120 typedef enum { 121 ICP_QAT_HW_AUTH_MODE0 = 0, /*!< QAT Auth Mode0 configuration */ 122 ICP_QAT_HW_AUTH_MODE1 = 1, /*!< QAT Auth Mode1 configuration */ 123 ICP_QAT_HW_AUTH_MODE2 = 2, /*!< QAT AuthMode2 configuration */ 124 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 /**< Delimiter type */ 125 } icp_qat_hw_auth_mode_t; 126 127 /** 128 ***************************************************************************** 129 * @ingroup icp_qat_hw_defs 130 * Auth configuration structure 131 * 132 * @description 133 * Definition of the format of the authentication slice configuration 134 * 135 *****************************************************************************/ 136 typedef struct icp_qat_hw_auth_config_s { 137 uint32_t config; 138 /**< Configuration used for setting up the slice */ 139 140 uint32_t reserved; 141 /**< Reserved */ 142 } icp_qat_hw_auth_config_t; 143 144 /* Private defines */ 145 146 /* Note: Bit positions have been defined for little endian ordering */ 147 /* 148 * AUTH CONFIG WORD BITMAP 149 * + ===== + ------ + ------ + ------- + ------ + ------ + ----- + ----- + ------ + ------ + ---- + ----- + ----- + ----- + 150 * | Bit | 63:56 | 55:52 | 51:48 | 47:32 | 31:24 | 23:22 | 21:18 | 17 | 16 | 15 | 14:8 | 7:4 | 3:0 | 151 * + ===== + ------ + ------ + ------- + ------ + ------ + ----- + ----- + ------ + ------ + ---- + ----- + ------+ ----- + 152 * | Usage | Prog | Resvd | Prog | Resvd | Resvd | Algo | Rsvrd | SHA3 | SHA3 |Rsvrd | Cmp | Mode | Algo | 153 * | |padding | Bits=0 | padding | Bits=0 | Bits=0 | SHA3 | |Padding |Padding | | | | | 154 * | | SHA3 | | SHA3 | | | | |Override|Disable | | | | | 155 * | |(prefix)| |(postfix)| | | | | | | | | | | 156 * + ===== + ------ + ------ + ------- + ------ + ------ + ----- + ----- + ------ + ------ + ---- + ----- + ----- + ------+ 157 */ 158 159 /**< Flag mask & bit position */ 160 161 #define QAT_AUTH_MODE_BITPOS 4 162 /**< @ingroup icp_qat_hw_defs 163 * Starting bit position indicating the Auth mode */ 164 165 #define QAT_AUTH_MODE_MASK 0xF 166 /**< @ingroup icp_qat_hw_defs 167 * Four bit mask used for determing the Auth mode */ 168 169 #define QAT_AUTH_ALGO_BITPOS 0 170 /**< @ingroup icp_qat_hw_defs 171 * Starting bit position indicating the Auth Algo */ 172 173 #define QAT_AUTH_ALGO_MASK 0xF 174 /**< @ingroup icp_qat_hw_defs 175 * Four bit mask used for determining the Auth algo */ 176 177 #define QAT_AUTH_CMP_BITPOS 8 178 /**< @ingroup icp_qat_hw_defs 179 * Starting bit position indicating the Auth Compare */ 180 181 #define QAT_AUTH_CMP_MASK 0x7F 182 /**< @ingroup icp_qat_hw_defs 183 * Seven bit mask used to determine the Auth Compare */ 184 185 #define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16 186 /**< @ingroup icp_qat_hw_defs 187 * Starting bit position indicating the Auth h/w 188 * padding disable for SHA3. 189 * Flag set to 0 => h/w is required to pad (default) 190 * Flag set to 1 => No padding in h/w 191 */ 192 193 #define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1 194 /**< @ingroup icp_qat_hw_defs 195 * Single bit mask used to determine the Auth h/w 196 * padding disable for SHA3. 197 */ 198 199 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17 200 /**< @ingroup icp_qat_hw_defs 201 * Starting bit position indicating the Auth h/w 202 * padding override for SHA3. 203 * Flag set to 0 => default padding behaviour 204 * implemented in SHA3-256 slice will take effect 205 * (default hardware setting upon h/w reset) 206 * Flag set to 1 => SHA3-core will not use the padding 207 * sequence built into the SHA3 core. Instead, the 208 * padding sequence specified in bits 48-51 and 56-63 209 * of the 64-bit auth config word will apply 210 * (corresponds with EAS bits 32-43). 211 */ 212 213 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1 214 /**< @ingroup icp_qat_hw_defs 215 * Single bit mask used to determine the Auth h/w 216 * padding override for SHA3. 217 */ 218 219 #define QAT_AUTH_ALGO_SHA3_BITPOS 22 220 /**< @ingroup icp_qat_hw_defs 221 * Starting bit position for indicating the 222 * SHA3 Auth Algo 223 */ 224 225 #define QAT_AUTH_ALGO_SHA3_MASK 0x3 226 /**< @ingroup icp_qat_hw_defs 227 * Two bit mask used for determining the 228 * SHA3 Auth algo 229 */ 230 231 /**< Flag mask & bit position */ 232 233 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16 234 /**< @ingroup icp_qat_hw_defs 235 * Starting bit position indicating the SHA3 236 * flexible programmable padding postfix. 237 * Note that these bits are set using macro 238 * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER and are 239 * defined relative to the 32-bit value that 240 * this macro returns. In effect, therefore, this 241 * defines starting bit position 48 within the 242 * 64-bit auth config word. 243 */ 244 245 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF 246 /**< @ingroup icp_qat_hw_defs 247 * Four-bit mask used to determine the SHA3 248 * flexible programmable padding postfix 249 */ 250 251 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24 252 /**< @ingroup icp_qat_hw_defs 253 * Starting bit position indicating the SHA3 254 * flexible programmable padding prefix 255 * Note that these bits are set using macro 256 * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER and are 257 * defined relative to the 32-bit value that 258 * this macro returns. In effect, therefore, this 259 * defines starting bit position 56 within the 260 * 64-bit auth config word. 261 */ 262 263 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF 264 /**< @ingroup icp_qat_hw_defs 265 * Eight-bit mask used to determine the SHA3 266 * flexible programmable padding prefix 267 */ 268 269 /**< Flag usage - see additional notes @description for 270 * ICP_QAT_HW_AUTH_CONFIG_BUILD and 271 * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER macros. 272 */ 273 274 #define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0 275 /**< @ingroup icp_qat_hw_defs 276 * This setting enables h/w padding for SHA3. 277 */ 278 279 #define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1 280 /**< @ingroup icp_qat_hw_defs 281 * This setting disables h/w padding for SHA3. 282 */ 283 284 #define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0 285 /**< @ingroup icp_qat_hw_defs 286 * Default value for the Auth h/w padding disable. 287 * If set to 0 for SHA3-256, h/w padding is enabled. 288 * Padding_Disable is undefined for all non-SHA3-256 289 * algos and is consequently set to the default of 0. 290 */ 291 292 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0 293 /**< @ingroup icp_qat_hw_defs 294 * Value for the Auth h/w padding override for SHA3. 295 * Flag set to 0 => default padding behaviour 296 * implemented in SHA3-256 slice will take effect 297 * (default hardware setting upon h/w reset) 298 * For this setting of the override flag, all the 299 * bits of the padding sequence specified 300 * in bits 48-51 and 56-63 of the 64-bit 301 * auth config word are set to 0 (reserved). 302 */ 303 304 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1 305 /**< @ingroup icp_qat_hw_defs 306 * Value for the Auth h/w padding override for SHA3. 307 * Flag set to 1 => SHA3-core will not use the padding 308 * sequence built into the SHA3 core. Instead, the 309 * padding sequence specified in bits 48-51 and 56-63 310 * of the 64-bit auth config word will apply 311 * (corresponds with EAS bits 32-43). 312 */ 313 314 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0 315 /**< @ingroup icp_qat_hw_defs 316 * All the bits of the padding sequence specified in 317 * bits 48-51 of the 64-bit auth config word are set 318 * to 0 (reserved) if the padding override bit is set 319 * to 0, indicating default padding. 320 */ 321 322 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0 323 /**< @ingroup icp_qat_hw_defs 324 * All the bits of the padding sequence specified in 325 * bits 56-63 of the 64-bit auth config word are set 326 * to 0 (reserved) if the padding override bit is set 327 * to 0, indicating default padding. 328 */ 329 330 /** 331 *************************************************************************************** 332 * @ingroup icp_qat_hw_defs 333 * 334 * @description 335 * The derived configuration word for the auth slice is based on the inputs 336 * of mode, algorithm type and compare length. The total size of the auth 337 * config word in the setup block is 64 bits however the size of the value 338 * returned by this macro is assumed to be only 32 bits (for now) and sets 339 * the lower 32 bits of the auth config word. Unfortunately, changing the 340 * size of the returned value to 64 bits will also require changes to the 341 * shared RAM constants table so the macro size will remain at 32 bits. 342 * This means that the padding sequence bits specified in bits 48-51 and 343 * 56-63 of the 64-bit auth config word are NOT included in the 344 * ICP_QAT_HW_AUTH_CONFIG_BUILD macro and are defined in a 345 * separate macro, namely, ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER. 346 * 347 * For the digest generation case the compare length is a don't care value. 348 * Furthermore, if the client will be doing the digest validation, the 349 * compare_length will not be used. 350 * The padding and padding override bits for SHA3 are set internally 351 * by the macro. 352 * Padding_Disable is set it to 0 for SHA3-256 algo only i.e. we want to 353 * enable this to provide the ability to test with h/w padding enabled. 354 * Padding_Disable has no meaning for all non-SHA3-256 algos and is 355 * consequently set the default of 0. 356 * Padding Override is set to 0, implying that the padding behaviour 357 * implemented in the SHA3-256 slice will take effect (default hardware 358 * setting upon h/w reset). 359 * This flag has no meaning for other algos, so is also set to the default 360 * for non-SHA3-256 algos. 361 * 362 * @param mode Authentication mode to use 363 * @param algo Auth Algorithm to use 364 * @param cmp_len The length of the digest if the QAT is to the check 365 * 366 ****************************************************************************************/ 367 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 368 ((((mode)&QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \ 369 (((algo)&QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \ 370 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \ 371 << QAT_AUTH_ALGO_SHA3_BITPOS) | \ 372 (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT)&QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \ 373 << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \ 374 (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT)&QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \ 375 << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \ 376 (((cmp_len)&QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS)) 377 378 /** 379 *************************************************************************************** 380 * @ingroup icp_qat_hw_defs 381 * 382 * @description 383 * This macro sets the upper 32 bits of the 64-bit auth config word. 384 * The sequence bits specified in bits 48-51 and 56-63 of the 64-bit auth 385 * config word are included in this macro, which is therefore assumed to 386 * return a 32-bit value. 387 * Note that the Padding Override bit is set in macro 388 * ICP_QAT_HW_AUTH_CONFIG_BUILD. 389 * Since the Padding Override is set to 0 regardless, for now, all the bits 390 * of the padding sequence specified in bits 48-51 and 56-63 of the 64-bit 391 * auth config word are set to 0 (reserved). Note that the bit positions of 392 * the padding sequence bits are defined relative to the 32-bit value that 393 * this macro returns. 394 * 395 ****************************************************************************************/ 396 #define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \ 397 ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED)&QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \ 398 << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \ 399 (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED)&QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \ 400 << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS)) 401 402 /** 403 ***************************************************************************** 404 * @ingroup icp_qat_hw_defs 405 * Auth Counter structure 406 * 407 * @description 408 * 32 bit counter that tracks the number of data bytes passed through 409 * the slice. This is used by the padding logic for some algorithms. Note 410 * only the upper 32 bits are set. 411 * 412 *****************************************************************************/ 413 typedef struct icp_qat_hw_auth_counter_s { 414 uint32_t counter; 415 /**< Counter value */ 416 uint32_t reserved; 417 /**< Reserved */ 418 } icp_qat_hw_auth_counter_t; 419 420 /* Private defines */ 421 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF 422 /**< @ingroup icp_qat_hw_defs 423 * Thirty two bit mask used for determining the Auth count */ 424 425 #define QAT_AUTH_COUNT_BITPOS 0 426 /**< @ingroup icp_qat_hw_defs 427 * Starting bit position indicating the Auth count. */ 428 429 /** 430 ****************************************************************************** 431 * @ingroup icp_qat_hw_defs 432 * 433 * @description 434 * Macro to build the auth counter quad word 435 * 436 * @param val Counter value to set 437 * 438 *****************************************************************************/ 439 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ 440 (((val)&QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) 441 442 /** 443 ***************************************************************************** 444 * @ingroup icp_qat_hw_defs 445 * Definition of the common auth parameters 446 * @description 447 * This part of the configuration is constant for each service 448 * 449 *****************************************************************************/ 450 typedef struct icp_qat_hw_auth_setup_s { 451 icp_qat_hw_auth_config_t auth_config; 452 /**< Configuration word for the auth slice */ 453 icp_qat_hw_auth_counter_t auth_counter; 454 /**< Auth counter value for this request */ 455 } icp_qat_hw_auth_setup_t; 456 457 /* ************************************************************************* */ 458 /* ************************************************************************* */ 459 460 #define QAT_HW_DEFAULT_ALIGNMENT 8 461 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1))) 462 463 /* State1 */ 464 #define ICP_QAT_HW_NULL_STATE1_SZ 32 465 /**< @ingroup icp_qat_hw_defs 466 * State1 block size for NULL hashing */ 467 #define ICP_QAT_HW_MD5_STATE1_SZ 16 468 /**< @ingroup icp_qat_hw_defs 469 * State1 block size for MD5 */ 470 #define ICP_QAT_HW_SHA1_STATE1_SZ 20 471 /**< @ingroup icp_qat_hw_defs 472 * Define the state1 block size for SHA1 - Note that for the QAT HW the state 473 * is rounded to the nearest 8 byte multiple */ 474 #define ICP_QAT_HW_SHA224_STATE1_SZ 32 475 /**< @ingroup icp_qat_hw_defs 476 * State1 block size for SHA24 */ 477 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 478 /**< @ingroup icp_qat_hw_defs 479 * State1 block size for SHA3_224 */ 480 #define ICP_QAT_HW_SHA256_STATE1_SZ 32 481 /**< @ingroup icp_qat_hw_defs 482 * State1 block size for SHA256 */ 483 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 484 /**< @ingroup icp_qat_hw_defs 485 * State1 block size for SHA3_256 */ 486 #define ICP_QAT_HW_SHA384_STATE1_SZ 64 487 /**< @ingroup icp_qat_hw_defs 488 * State1 block size for SHA384 */ 489 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 490 /**< @ingroup icp_qat_hw_defs 491 * State1 block size for SHA3_384 */ 492 #define ICP_QAT_HW_SHA512_STATE1_SZ 64 493 /**< @ingroup icp_qat_hw_defs 494 * State1 block size for SHA512 */ 495 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 496 /**< @ingroup icp_qat_hw_defs 497 * State1 block size for SHA3_512 */ 498 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16 499 /**< @ingroup icp_qat_hw_defs 500 * State1 block size for XCBC */ 501 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16 502 /**< @ingroup icp_qat_hw_defs 503 * State1 block size for CBC */ 504 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32 505 /**< @ingroup icp_qat_hw_defs 506 * State1 block size for AES F9 */ 507 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16 508 /**< @ingroup icp_qat_hw_defs 509 * State1 block size for Kasumi F9 */ 510 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16 511 /**< @ingroup icp_qat_hw_defs 512 * State1 block size for Galois128 */ 513 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 514 /**< @ingroup icp_cpm_hw_defs 515 * State1 block size for UIA2 */ 516 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 517 /**< @ingroup icp_cpm_hw_defs 518 * State1 block size for EIA3 */ 519 #define ICP_QAT_HW_SM3_STATE1_SZ 32 520 /**< @ingroup icp_qat_hw_defs 521 * State1 block size for SM3 */ 522 #define ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ 200 523 /** <@ingroup icp_cpm_hw_defs 524 * State1 block size for stateful SHA3 processing*/ 525 526 /* State2 */ 527 #define ICP_QAT_HW_NULL_STATE2_SZ 32 528 /**< @ingroup icp_qat_hw_defs 529 * State2 block size for NULL hashing */ 530 #define ICP_QAT_HW_MD5_STATE2_SZ 16 531 /**< @ingroup icp_qat_hw_defs 532 * State2 block size for MD5 */ 533 #define ICP_QAT_HW_SHA1_STATE2_SZ 20 534 /**< @ingroup icp_qat_hw_defs 535 * State2 block size for SHA1 - Note that for the QAT HW the state is rounded 536 * to the nearest 8 byte multiple */ 537 #define ICP_QAT_HW_SHA224_STATE2_SZ 32 538 /**< @ingroup icp_qat_hw_defs 539 * State2 block size for SHA224 */ 540 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 541 /**< @ingroup icp_qat_hw_defs 542 * State2 block size for SHA3_224 */ 543 #define ICP_QAT_HW_SHA256_STATE2_SZ 32 544 /**< @ingroup icp_qat_hw_defs 545 * State2 block size for SHA256 */ 546 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 547 /**< @ingroup icp_qat_hw_defs 548 * State2 block size for SHA3_256 */ 549 #define ICP_QAT_HW_SHA384_STATE2_SZ 64 550 /**< @ingroup icp_qat_hw_defs 551 * State2 block size for SHA384 */ 552 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 553 /**< @ingroup icp_qat_hw_defs 554 * State2 block size for SHA3_384 */ 555 #define ICP_QAT_HW_SHA512_STATE2_SZ 64 556 /**< @ingroup icp_qat_hw_defs 557 * State2 block size for SHA512 */ 558 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 559 /**< @ingroup icp_qat_hw_defs 560 * State2 block size for SHA3_512 */ 561 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 562 /**< @ingroup icp_qat_hw_defs 563 * State2 block size for XCBC */ 564 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 565 /**< @ingroup icp_qat_hw_defs 566 * State2 block size for CBC */ 567 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16 568 /**< @ingroup icp_qat_hw_defs 569 * State2 block size for AES Encrypted Counter 0 */ 570 #define ICP_QAT_HW_F9_IK_SZ 16 571 /**< @ingroup icp_qat_hw_defs 572 * State2 block size for F9 IK */ 573 #define ICP_QAT_HW_F9_FK_SZ 16 574 /**< @ingroup icp_qat_hw_defs 575 * State2 block size for F9 FK */ 576 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ \ 577 (ICP_QAT_HW_F9_IK_SZ + ICP_QAT_HW_F9_FK_SZ) 578 /**< @ingroup icp_qat_hw_defs 579 * State2 complete size for Kasumi F9 */ 580 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ 581 /**< @ingroup icp_qat_hw_defs 582 * State2 complete size for AES F9 */ 583 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24 584 /**< @ingroup icp_cpm_hw_defs 585 * State2 block size for UIA2 */ 586 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32 587 /**< @ingroup icp_cpm_hw_defs 588 * State2 block size for EIA3 */ 589 #define ICP_QAT_HW_GALOIS_H_SZ 16 590 /**< @ingroup icp_qat_hw_defs 591 * State2 block size for Galois Multiplier H */ 592 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 593 /**< @ingroup icp_qat_hw_defs 594 * State2 block size for Galois AAD length */ 595 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 596 /**< @ingroup icp_qat_hw_defs 597 * State2 block size for Galois Encrypted Counter 0 */ 598 #define ICP_QAT_HW_SM3_STATE2_SZ 32 599 /**< @ingroup icp_qat_hw_defs 600 * State2 block size for SM3 */ 601 #define ICP_QAT_HW_SHA3_STATEFUL_STATE2_SZ 208 602 /** <@ingroup icp_cpm_hw_defs 603 * State2 block size for stateful SHA3 processing*/ 604 605 /* ************************************************************************* */ 606 /* ************************************************************************* */ 607 608 /** 609 ***************************************************************************** 610 * @ingroup icp_qat_hw_defs 611 * Definition of SHA512 auth algorithm processing struct 612 * @description 613 * This structs described the parameters to pass to the slice for 614 * configuring it for SHA512 processing. This is the largest possible 615 * setup block for authentication 616 * 617 *****************************************************************************/ 618 typedef struct icp_qat_hw_auth_sha512_s { 619 icp_qat_hw_auth_setup_t inner_setup; 620 /**< Inner loop configuration word for the slice */ 621 622 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ]; 623 /**< Slice state1 variable */ 624 625 icp_qat_hw_auth_setup_t outer_setup; 626 /**< Outer configuration word for the slice */ 627 628 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ]; 629 /**< Slice state2 variable */ 630 631 } icp_qat_hw_auth_sha512_t; 632 633 /** 634 ***************************************************************************** 635 * @ingroup icp_qat_hw_defs 636 * Definition of SHA3_512 auth algorithm processing struct 637 * @description 638 * This structs described the parameters to pass to the slice for 639 * configuring it for SHA3_512 processing. This is the largest possible 640 * setup block for authentication 641 * 642 *****************************************************************************/ 643 typedef struct icp_qat_hw_auth_sha3_512_s { 644 icp_qat_hw_auth_setup_t inner_setup; 645 /**< Inner loop configuration word for the slice */ 646 647 uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ]; 648 /**< Slice state1 variable */ 649 650 icp_qat_hw_auth_setup_t outer_setup; 651 /**< Outer configuration word for the slice */ 652 653 } icp_qat_hw_auth_sha3_512_t; 654 655 /** 656 ***************************************************************************** 657 * @ingroup icp_qat_hw_defs 658 * Definition of stateful SHA3 auth algorithm processing struct 659 * @description 660 * This structs described the parameters to pass to the slice for 661 * configuring it for stateful SHA3 processing. This is the largest 662 * possible setup block for authentication 663 * 664 *****************************************************************************/ 665 typedef struct icp_qat_hw_auth_sha3_stateful_s { 666 icp_qat_hw_auth_setup_t inner_setup; 667 /**< Inner loop configuration word for the slice */ 668 669 uint8_t inner_state1[ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ]; 670 /**< Inner hash block */ 671 672 icp_qat_hw_auth_setup_t outer_setup; 673 /**< Outer configuration word for the slice */ 674 675 uint8_t outer_state1[ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ]; 676 /**< Outer hash block */ 677 678 } icp_qat_hw_auth_sha3_stateful_t; 679 680 /** 681 ***************************************************************************** 682 * @ingroup icp_qat_hw_defs 683 * Supported hardware authentication algorithms 684 * @description 685 * Common grouping of the auth algorithm types supported by the QAT 686 * 687 *****************************************************************************/ 688 typedef union icp_qat_hw_auth_algo_blk_u { 689 icp_qat_hw_auth_sha512_t sha512; 690 /**< SHA512 Hashing */ 691 icp_qat_hw_auth_sha3_stateful_t sha3_stateful; 692 /**< Stateful SHA3 Hashing */ 693 694 } icp_qat_hw_auth_algo_blk_t; 695 696 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 697 /**< @ingroup icp_qat_hw_defs 698 * Bit position of the 32 bit A value in the 64 bit A configuration sent to 699 * the QAT */ 700 701 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF 702 /**< @ingroup icp_qat_hw_defs 703 * Mask value for A value */ 704 705 /* ========================================================================= */ 706 /* CIPHER SLICE */ 707 /* ========================================================================= */ 708 709 /** 710 ***************************************************************************** 711 * @ingroup icp_qat_hw_defs 712 * Definition of the supported Cipher Algorithm types 713 * @description 714 * Enumeration used to define the cipher algorithms 715 * 716 *****************************************************************************/ 717 718 typedef enum { 719 ICP_QAT_HW_CIPHER_ALGO_NULL = 0, /*!< Null ciphering */ 720 ICP_QAT_HW_CIPHER_ALGO_DES = 1, /*!< DES ciphering */ 721 ICP_QAT_HW_CIPHER_ALGO_3DES = 2, /*!< 3DES ciphering */ 722 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, /*!< AES-128 ciphering */ 723 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, /*!< AES-192 ciphering */ 724 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, /*!< AES-256 ciphering */ 725 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, /*!< ARC4 ciphering */ 726 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, /*!< Kasumi */ 727 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, /*!< Snow_3G */ 728 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, /*!< ZUC_3G */ 729 ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, /*!< SM4 ciphering */ 730 ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 731 11, /*!< CHACHA POLY SPC AEAD */ 732 ICP_QAT_HW_CIPHER_DELIMITER = 12 /**< Delimiter type */ 733 } icp_qat_hw_cipher_algo_t; 734 735 /** 736 ***************************************************************************** 737 * @ingroup icp_qat_hw_defs 738 * Definition of the supported cipher modes of operation 739 * @description 740 * Enumeration used to define the cipher slice modes. 741 * 742 * @Note 743 * Only some algorithms are valid in some of the modes. If you dont know 744 * what you are doing then refer back to the EAS 745 * 746 *****************************************************************************/ 747 748 typedef enum { 749 ICP_QAT_HW_CIPHER_ECB_MODE = 0, /*!< ECB mode */ 750 ICP_QAT_HW_CIPHER_CBC_MODE = 1, /*!< CBC more */ 751 ICP_QAT_HW_CIPHER_CTR_MODE = 2, /*!< CTR mode */ 752 ICP_QAT_HW_CIPHER_F8_MODE = 3, /*!< F8 mode */ 753 ICP_QAT_HW_CIPHER_AEAD_MODE = 4, /*!< AES-GCM SPC AEAD mode */ 754 ICP_QAT_HW_CIPHER_CCM_MODE = 5, /*!< AES-CCM SPC AEAD mode */ 755 ICP_QAT_HW_CIPHER_XTS_MODE = 6, /*!< XTS mode */ 756 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 /**< Delimiter type */ 757 } icp_qat_hw_cipher_mode_t; 758 759 /** 760 ***************************************************************************** 761 * @ingroup icp_qat_hw_defs 762 * Cipher Configuration Struct 763 * 764 * @description 765 * Configuration data used for setting up the QAT Cipher Slice 766 * 767 *****************************************************************************/ 768 769 typedef struct icp_qat_hw_cipher_config_s { 770 uint32_t val; 771 /**< Cipher slice configuration */ 772 773 uint32_t reserved; 774 /**< Reserved */ 775 } icp_qat_hw_cipher_config_t; 776 777 /** 778 ***************************************************************************** 779 * @ingroup icp_qat_hw_defs 780 * Cipher Configuration Struct 781 * 782 * @description 783 * Configuration data used for setting up the QAT UCS Cipher Slice 784 * 785 *****************************************************************************/ 786 typedef struct icp_qat_hw_ucs_cipher_config_s { 787 uint32_t val; 788 /**< Cipher slice configuration */ 789 790 uint32_t reserved[3]; 791 /**< Reserved */ 792 } icp_qat_hw_ucs_cipher_config_t; 793 794 /** 795 ***************************************************************************** 796 * @ingroup icp_qat_hw_defs 797 * Definition of the cipher direction 798 * @description 799 * Enumeration which is used to define the cipher direction to apply 800 * 801 *****************************************************************************/ 802 803 typedef enum { 804 /*!< Flag to indicate that encryption is required */ 805 ICP_QAT_HW_CIPHER_ENCRYPT = 0, 806 /*!< Flag to indicate that decryption is required */ 807 ICP_QAT_HW_CIPHER_DECRYPT = 1, 808 809 } icp_qat_hw_cipher_dir_t; 810 811 /** 812 ***************************************************************************** 813 * @ingroup icp_qat_hw_defs 814 * Definition of the cipher key conversion modes 815 * @description 816 * Enumeration which is used to define if cipher key conversion is needed 817 * 818 *****************************************************************************/ 819 820 typedef enum { 821 /*!< Flag to indicate that no key convert is required */ 822 ICP_QAT_HW_CIPHER_NO_CONVERT = 0, 823 /*!< Flag to indicate that key conversion is required */ 824 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1, 825 } icp_qat_hw_cipher_convert_t; 826 827 /* Private defines */ 828 829 /* Note: Bit positions have been arranged for little endian ordering */ 830 831 #define QAT_CIPHER_MODE_BITPOS 4 832 /**< @ingroup icp_qat_hw_defs 833 * Define for the cipher mode bit position */ 834 835 #define QAT_CIPHER_MODE_MASK 0xF 836 /**< @ingroup icp_qat_hw_defs 837 * Define for the cipher mode mask (four bits) */ 838 839 #define QAT_CIPHER_ALGO_BITPOS 0 840 /**< @ingroup icp_qat_hw_defs 841 * Define for the cipher algo bit position */ 842 843 #define QAT_CIPHER_ALGO_MASK 0xF 844 /**< @ingroup icp_qat_hw_defs 845 * Define for the cipher algo mask (four bits) */ 846 847 #define QAT_CIPHER_CONVERT_BITPOS 9 848 /**< @ingroup icp_qat_hw_defs 849 * Define the cipher convert key bit position */ 850 851 #define QAT_CIPHER_CONVERT_MASK 0x1 852 /**< @ingroup icp_qat_hw_defs 853 * Define for the cipher convert key mask (one bit)*/ 854 855 #define QAT_CIPHER_DIR_BITPOS 8 856 /**< @ingroup icp_qat_hw_defs 857 * Define for the cipher direction bit position */ 858 859 #define QAT_CIPHER_DIR_MASK 0x1 860 /**< @ingroup icp_qat_hw_defs 861 * Define for the cipher direction mask (one bit) */ 862 863 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F 864 /**< @ingroup icp_qat_hw_defs 865 * Define for the cipher AEAD Hash compare length mask (5 bits)*/ 866 867 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10 868 /**< @ingroup icp_qat_hw_defs 869 * Define for the cipher AEAD Hash compare length (5 bits)*/ 870 871 #define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF 872 /**< @ingroup icp_qat_hw_defs 873 * Define for the cipher AEAD AAD size lower byte mask */ 874 875 #define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F 876 /**< @ingroup icp_qat_hw_defs 877 * Define for the cipher AEAD AAD size upper 6 bits mask */ 878 879 #define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8 880 /**< @ingroup icp_qat_hw_defs 881 * Define for the cipher AEAD AAD size Upper byte shift */ 882 883 #define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24 884 /**< @ingroup icp_qat_hw_defs 885 * Define for the cipher AEAD AAD size Lower byte shift */ 886 887 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16 888 /**< @ingroup icp_qat_hw_defs 889 * Define for the cipher AEAD AAD size (14 bits)*/ 890 891 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 892 /**< @ingroup icp_qat_hw_defs 893 * Define for the cipher mode F8 key size */ 894 895 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 896 /**< @ingroup icp_qat_hw_defs 897 * Define for the cipher XTS mode key size */ 898 899 #define QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT 1 900 /**< @ingroup icp_qat_hw_defs 901 * Define for the UCS cipher XTS mode key size */ 902 903 /** 904 ****************************************************************************** 905 * @ingroup icp_qat_hw_defs 906 * 907 * @description 908 * Build the cipher configuration field 909 * 910 * @param mode Cipher Mode to use 911 * @param algo Cipher Algorithm to use 912 * @param convert Specify if the key is to be converted 913 * @param dir Specify the cipher direction either encrypt or decrypt 914 * 915 *****************************************************************************/ 916 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD( \ 917 mode, algo, convert, dir, aead_hash_cmp_len) \ 918 ((((mode)&QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \ 919 (((algo)&QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ 920 (((convert)&QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ 921 (((dir)&QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS) | \ 922 (((aead_hash_cmp_len)&QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK) \ 923 << QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS)) 924 925 /** 926 ****************************************************************************** 927 * @ingroup icp_qat_hw_defs 928 * 929 * @description 930 * Build the second QW of cipher slice config 931 * 932 * @param aad_size Specify the size of associated authentication data 933 * for AEAD processing 934 * 935 ******************************************************************************/ 936 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \ 937 (((((aad_size) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \ 938 QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) \ 939 << QAT_CIPHER_AEAD_AAD_SIZE_BITPOS) | \ 940 (((aad_size)&QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK) \ 941 << QAT_CIPHER_AEAD_AAD_LOWER_SHIFT)) 942 943 #define ICP_QAT_HW_DES_BLK_SZ 8 944 /**< @ingroup icp_qat_hw_defs 945 * Define the block size for DES. 946 * This used as either the size of the IV or CTR input value */ 947 #define ICP_QAT_HW_3DES_BLK_SZ 8 948 /**< @ingroup icp_qat_hw_defs 949 * Define the processing block size for 3DES */ 950 #define ICP_QAT_HW_NULL_BLK_SZ 8 951 /**< @ingroup icp_qat_hw_defs 952 * Define the processing block size for NULL */ 953 #define ICP_QAT_HW_AES_BLK_SZ 16 954 /**< @ingroup icp_qat_hw_defs 955 * Define the processing block size for AES 128, 192 and 256 */ 956 #define ICP_QAT_HW_KASUMI_BLK_SZ 8 957 /**< @ingroup icp_qat_hw_defs 958 * Define the processing block size for KASUMI */ 959 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8 960 /**< @ingroup icp_qat_hw_defs 961 * Define the processing block size for SNOW_3G */ 962 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8 963 /**< @ingroup icp_qat_hw_defs 964 * Define the processing block size for ZUC_3G */ 965 #define ICP_QAT_HW_NULL_KEY_SZ 256 966 /**< @ingroup icp_qat_hw_defs 967 * Define the key size for NULL */ 968 #define ICP_QAT_HW_DES_KEY_SZ 8 969 /**< @ingroup icp_qat_hw_defs 970 * Define the key size for DES */ 971 #define ICP_QAT_HW_3DES_KEY_SZ 24 972 /**< @ingroup icp_qat_hw_defs 973 * Define the key size for 3DES */ 974 #define ICP_QAT_HW_AES_128_KEY_SZ 16 975 /**< @ingroup icp_qat_hw_defs 976 * Define the key size for AES128 */ 977 #define ICP_QAT_HW_AES_192_KEY_SZ 24 978 /**< @ingroup icp_qat_hw_defs 979 * Define the key size for AES192 */ 980 #define ICP_QAT_HW_AES_256_KEY_SZ 32 981 /**< @ingroup icp_qat_hw_defs 982 * Define the key size for AES256 */ 983 /* AES UCS */ 984 #define ICP_QAT_HW_UCS_AES_128_KEY_SZ ICP_QAT_HW_AES_128_KEY_SZ 985 /**< @ingroup icp_qat_hw_defs 986 * Define the key size for AES128 for UCS slice*/ 987 #define ICP_QAT_HW_UCS_AES_192_KEY_SZ 32 988 /**< @ingroup icp_qat_hw_defs 989 * Define the key size for AES192 for UCS slice*/ 990 #define ICP_QAT_HW_UCS_AES_256_KEY_SZ ICP_QAT_HW_AES_256_KEY_SZ 991 /**< @ingroup icp_qat_hw_defs 992 * Define the key size for AES256 for UCS slice*/ 993 #define ICP_QAT_HW_AES_128_F8_KEY_SZ \ 994 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 995 /**< @ingroup icp_qat_hw_defs 996 * Define the key size for AES128 F8 */ 997 #define ICP_QAT_HW_AES_192_F8_KEY_SZ \ 998 (ICP_QAT_HW_AES_192_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 999 /**< @ingroup icp_qat_hw_defs 1000 * Define the key size for AES192 F8 */ 1001 #define ICP_QAT_HW_AES_256_F8_KEY_SZ \ 1002 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 1003 /**< @ingroup icp_qat_hw_defs 1004 * Define the key size for AES256 F8 */ 1005 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 1006 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1007 /**< @ingroup icp_qat_hw_defs 1008 * Define the key size for AES128 XTS */ 1009 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 1010 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1011 /**< @ingroup icp_qat_hw_defs 1012 * Define the key size for AES256 XTS */ 1013 #define ICP_QAT_HW_UCS_AES_128_XTS_KEY_SZ \ 1014 (ICP_QAT_HW_UCS_AES_128_KEY_SZ * QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT) 1015 /**< @ingroup icp_qat_hw_defs 1016 * Define the key size for AES128 XTS for the UCS Slice*/ 1017 #define ICP_QAT_HW_UCS_AES_256_XTS_KEY_SZ \ 1018 (ICP_QAT_HW_UCS_AES_256_KEY_SZ * QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT) 1019 /**< @ingroup icp_qat_hw_defs 1020 * Define the key size for AES256 XTS for the UCS Slice*/ 1021 #define ICP_QAT_HW_KASUMI_KEY_SZ 16 1022 /**< @ingroup icp_qat_hw_defs 1023 * Define the key size for Kasumi */ 1024 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ \ 1025 (ICP_QAT_HW_KASUMI_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 1026 /**< @ingroup icp_qat_hw_defs 1027 * Define the key size for Kasumi F8 */ 1028 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 1029 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1030 /**< @ingroup icp_qat_hw_defs 1031 * Define the key size for AES128 XTS */ 1032 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 1033 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1034 /**< @ingroup icp_qat_hw_defs 1035 * Define the key size for AES256 XTS */ 1036 #define ICP_QAT_HW_ARC4_KEY_SZ 256 1037 /**< @ingroup icp_qat_hw_defs 1038 * Define the key size for ARC4 */ 1039 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16 1040 /**< @ingroup icp_cpm_hw_defs 1041 * Define the key size for SNOW_3G_UEA2 */ 1042 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16 1043 /**< @ingroup icp_cpm_hw_defs 1044 * Define the iv size for SNOW_3G_UEA2 */ 1045 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16 1046 /**< @ingroup icp_cpm_hw_defs 1047 * Define the key size for ZUC_3G_EEA3 */ 1048 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16 1049 /**< @ingroup icp_cpm_hw_defs 1050 * Define the iv size for ZUC_3G_EEA3 */ 1051 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2 1052 /**< @ingroup icp_cpm_hw_defs 1053 * Number of the HW register to clear in F8 mode */ 1054 /**< @ingroup icp_qat_hw_defs 1055 * Define the State/ Initialization Vector size for CHACHAPOLY */ 1056 #define ICP_QAT_HW_CHACHAPOLY_KEY_SZ 32 1057 /**< @ingroup icp_qat_hw_defs 1058 * Define the key size for CHACHA20-Poly1305*/ 1059 #define ICP_QAT_HW_CHACHAPOLY_IV_SZ 12 1060 /**< @ingroup icp_qat_hw_defs 1061 * Define the block size for CHACHA20-Poly1305*/ 1062 #define ICP_QAT_HW_CHACHAPOLY_BLK_SZ 64 1063 /**< @ingroup icp_qat_hw_defs 1064 * Define the State/ Initialization Vector size for CHACHA20-Poly1305 */ 1065 #define ICP_QAT_HW_CHACHAPOLY_CTR_SZ 16 1066 /**< @ingroup icp_qat_hw_defs 1067 * Define the key size for CHACHA20-Poly1305*/ 1068 #define ICP_QAT_HW_SPC_CTR_SZ 16 1069 /**< @ingroup icp_qat_hw_defs 1070 * Define the Single Pass tag size*/ 1071 #define ICP_QAT_HW_CHACHAPOLY_ICV__SZ 16 1072 /**< @ingroup icp_qat_hw_defs 1073 * Define the key size for CHACHA20-Poly1305*/ 1074 #define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14 1075 /**< @ingroup icp_qat_hw_defs 1076 * Define the key size for CHACHA20-Poly1305*/ 1077 #define ICP_QAT_HW_SM4_BLK_SZ 16 1078 /**< @ingroup icp_qat_hw_defs 1079 * Define the processing block size for SM4 */ 1080 #define ICP_QAT_HW_SM4_KEY_SZ 16 1081 /**< @ingroup icp_qat_hw_defs 1082 * Number of the HW register to clear in F8 mode */ 1083 #define ICP_QAT_HW_SM4_IV_SZ 16 1084 /**< @ingroup icp_qat_hw_defs 1085 * Define the key size for SM4 */ 1086 1087 /* 1088 * SHRAM constants definitions 1089 */ 1090 #define INIT_SHRAM_CONSTANTS_TABLE_SZ (1024) 1091 #define SHRAM_CONSTANTS_TABLE_SIZE_QWS (INIT_SHRAM_CONSTANTS_TABLE_SZ / 4 / 2) 1092 1093 /** 1094 ***************************************************************************** 1095 * @ingroup icp_qat_hw_defs 1096 * Definition of AES-256 F8 cipher algorithm processing struct 1097 * @description 1098 * This structs described the parameters to pass to the slice for 1099 * configuring it for AES-256 F8 processing 1100 * 1101 *****************************************************************************/ 1102 typedef struct icp_qat_hw_cipher_aes256_f8_s { 1103 icp_qat_hw_cipher_config_t cipher_config; 1104 /**< Cipher configuration word for the slice set to 1105 * AES-256 and the F8 mode */ 1106 1107 uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ]; 1108 /**< Cipher key */ 1109 1110 } icp_qat_hw_cipher_aes256_f8_t; 1111 1112 /** 1113 ***************************************************************************** 1114 * @ingroup icp_qat_hw_defs 1115 * Supported hardware cipher algorithms 1116 * @description 1117 * Common grouping of the cipher algorithm types supported by the QAT. 1118 * This is the largest possible cipher setup block size 1119 * 1120 *****************************************************************************/ 1121 typedef union icp_qat_hw_cipher_algo_blk_u { 1122 1123 icp_qat_hw_cipher_aes256_f8_t aes256_f8; 1124 /**< AES-256 F8 Cipher */ 1125 1126 } icp_qat_hw_cipher_algo_blk_t; 1127 1128 /* ========================================================================= */ 1129 /* TRNG SLICE */ 1130 /* ========================================================================= */ 1131 1132 /** 1133 ***************************************************************************** 1134 * @ingroup icp_qat_hw_defs 1135 * Definition of the supported TRNG configuration modes 1136 * @description 1137 * Enumeration used to define the TRNG modes. Used by clients when 1138 * configuring the TRNG for use 1139 * 1140 *****************************************************************************/ 1141 1142 typedef enum { 1143 ICP_QAT_HW_TRNG_DBL = 0, /*!< TRNG Disabled mode */ 1144 ICP_QAT_HW_TRNG_NHT = 1, /*!< TRNG Normal Health Test mode */ 1145 ICP_QAT_HW_TRNG_KAT = 4, /*!< TRNG Known Answer Test mode */ 1146 ICP_QAT_HW_TRNG_DELIMITER = 8 /**< Delimiter type */ 1147 } icp_qat_hw_trng_cfg_mode_t; 1148 1149 /** 1150 ***************************************************************************** 1151 * @ingroup icp_qat_hw_defs 1152 * Definition of the supported TRNG KAT (known answer test) modes 1153 * @description 1154 * Enumeration which is used to define the TRNG KAT modes. Used by clients 1155 * when configuring the TRNG for testing 1156 * 1157 *****************************************************************************/ 1158 1159 typedef enum { 1160 ICP_QAT_HW_TRNG_NEG_0 = 0, /*!< TRNG Neg Zero Test */ 1161 ICP_QAT_HW_TRNG_NEG_1 = 1, /*!< TRNG Neg One Test */ 1162 ICP_QAT_HW_TRNG_POS = 2, /*!< TRNG POS Test */ 1163 ICP_QAT_HW_TRNG_POS_VNC = 3, /*!< TRNG POS VNC Test */ 1164 ICP_QAT_HW_TRNG_KAT_DELIMITER = 4 /**< Delimiter type */ 1165 } icp_qat_hw_trng_kat_mode_t; 1166 1167 /** 1168 ***************************************************************************** 1169 * @ingroup icp_qat_hw_defs 1170 * TRNG mode configuration structure. 1171 * 1172 * @description 1173 * Definition of the format of the TRNG slice configuration. Used 1174 * internally by the QAT FW for configuration of the KAT unit or the 1175 * TRNG depending on the slice command i.e. either a set_slice_config or 1176 * slice_wr_KAT_type 1177 * 1178 *****************************************************************************/ 1179 1180 typedef struct icp_qat_hw_trng_config_s { 1181 uint32_t val; 1182 /**< Configuration used for setting up the TRNG slice */ 1183 1184 uint32_t reserved; 1185 /**< Reserved */ 1186 } icp_qat_hw_trng_config_t; 1187 1188 /* Private Defines */ 1189 1190 /* Note: Bit positions have been arranged for little endian ordering */ 1191 1192 #define QAT_TRNG_CONFIG_MODE_MASK 0x7 1193 /**< @ingroup icp_qat_hw_defs 1194 * Mask for the TRNG configuration mode. (Three bits) */ 1195 1196 #define QAT_TRNG_CONFIG_MODE_BITPOS 5 1197 /**< @ingroup icp_qat_hw_defs 1198 * TRNG configuration mode bit positions start */ 1199 1200 #define QAT_TRNG_KAT_MODE_MASK 0x3 1201 /**< @ingroup icp_qat_hw_defs 1202 * Mask of two bits for the TRNG known answer test mode */ 1203 1204 #define QAT_TRNG_KAT_MODE_BITPOS 6 1205 /**< @ingroup icp_qat_hw_defs 1206 * TRNG known answer test mode bit positions start */ 1207 1208 /** 1209 ****************************************************************************** 1210 * @ingroup icp_qat_hw_defs 1211 * 1212 * @description 1213 * Build the configuration byte for the TRNG slice based on the mode 1214 * 1215 * @param mode Configuration mode parameter 1216 * 1217 *****************************************************************************/ 1218 #define ICP_QAT_HW_TRNG_CONFIG_MODE_BUILD(mode) \ 1219 (((mode)&QAT_TRNG_CONFIG_MODE_MASK) << QAT_TRNG_CONFIG_MODE_BITPOS) 1220 1221 /** 1222 ****************************************************************************** 1223 * @ingroup icp_qat_hw_defs 1224 * 1225 * @description 1226 * Build the configuration byte for the TRNG KAT based on the mode 1227 * 1228 * @param mode Configuration mode parameter 1229 * 1230 *****************************************************************************/ 1231 #define ICP_QAT_HW_TRNG_KAT_MODE_BUILD(mode) \ 1232 ((((mode)&QAT_TRNG_KAT_MODE_MASK) << QAT_TRNG_KAT_MODE_BITPOS)) 1233 1234 /** 1235 ***************************************************************************** 1236 * @ingroup icp_qat_hw_defs 1237 * TRNG test status structure. 1238 * 1239 * @description 1240 * Definition of the format of the TRNG slice test status structure. Used 1241 * internally by the QAT FW. 1242 * 1243 *****************************************************************************/ 1244 1245 typedef struct icp_qat_hw_trng_test_status_s { 1246 1247 uint32_t status; 1248 /**< Status used for setting up the TRNG slice */ 1249 1250 uint32_t fail_count; 1251 /**< Comparator fail count */ 1252 } icp_qat_hw_trng_test_status_t; 1253 1254 #define ICP_QAT_HW_TRNG_TEST_NO_FAILURES 1 1255 /**< @ingroup icp_qat_hw_defs 1256 * Flag to indicate that there were no Test Failures */ 1257 1258 #define ICP_QAT_HW_TRNG_TEST_FAILURES_FOUND 0 1259 /**< @ingroup icp_qat_hw_defs 1260 * Flag to indicate that there were Test Failures */ 1261 1262 #define ICP_QAT_HW_TRNG_TEST_STATUS_VALID 1 1263 /**< @ingroup icp_qat_hw_defs 1264 * Flag to indicate that there is no valid Test output */ 1265 1266 #define ICP_QAT_HW_TRNG_TEST_STATUS_INVALID 0 1267 /**< @ingroup icp_qat_hw_defs 1268 * Flag to indicate that the Test output is still invalid */ 1269 1270 /* Private defines */ 1271 #define QAT_TRNG_TEST_FAILURE_FLAG_MASK 0x1 1272 /**< @ingroup icp_qat_hw_defs 1273 * Mask of one bit used to determine the TRNG Test pass/fail */ 1274 1275 #define QAT_TRNG_TEST_FAILURE_FLAG_BITPOS 4 1276 /**< @ingroup icp_qat_hw_defs 1277 * Flag position to indicate that the TRNG Test status is pass of fail */ 1278 1279 #define QAT_TRNG_TEST_STATUS_MASK 0x1 1280 /**< @ingroup icp_qat_hw_defs 1281 * Mask of one bit used to determine the TRNG Test staus */ 1282 1283 #define QAT_TRNG_TEST_STATUS_BITPOS 1 1284 /**< @ingroup icp_qat_hw_defs 1285 * Flag position to indicate the TRNG Test status */ 1286 1287 /** 1288 ****************************************************************************** 1289 * @ingroup icp_qat_hw_defs 1290 * 1291 * @description 1292 * Extract the fail bit for the TRNG slice 1293 * 1294 * @param status TRNG status value 1295 * 1296 *****************************************************************************/ 1297 1298 #define ICP_QAT_HW_TRNG_FAIL_FLAG_GET(status) \ 1299 (((status) >> QAT_TRNG_TEST_FAILURE_FLAG_BITPOS) & \ 1300 QAT_TRNG_TEST_FAILURE_FLAG_MASK) 1301 1302 /** 1303 ****************************************************************************** 1304 * @ingroup icp_qat_hw_defs 1305 * 1306 * @description 1307 * Extract the status valid bit for the TRNG slice 1308 * 1309 * @param status TRNG status value 1310 * 1311 *****************************************************************************/ 1312 #define ICP_QAT_HW_TRNG_STATUS_VALID_GET(status) \ 1313 (((status) >> QAT_TRNG_TEST_STATUS_BITPOS) & QAT_TRNG_TEST_STATUS_MASK) 1314 1315 /** 1316 ***************************************************************************** 1317 * @ingroup icp_qat_hw_defs 1318 * TRNG entropy counters 1319 * 1320 * @description 1321 * Definition of the format of the TRNG entropy counters. Used internally 1322 * by the QAT FW. 1323 * 1324 *****************************************************************************/ 1325 1326 typedef struct icp_qat_hw_trng_entropy_counts_s { 1327 uint64_t raw_ones_count; 1328 /**< Count of raw ones of entropy */ 1329 1330 uint64_t raw_zeros_count; 1331 /**< Count of raw zeros of entropy */ 1332 1333 uint64_t cond_ones_count; 1334 /**< Count of conditioned ones entropy */ 1335 1336 uint64_t cond_zeros_count; 1337 /**< Count of conditioned zeros entropy */ 1338 } icp_qat_hw_trng_entropy_counts_t; 1339 1340 /* Private defines */ 1341 #define QAT_HW_TRNG_ENTROPY_STS_RSVD_SZ 4 1342 /**< @ingroup icp_qat_hw_defs 1343 * TRNG entropy status reserved size in bytes */ 1344 1345 /** 1346 ***************************************************************************** 1347 * @ingroup icp_qat_hw_defs 1348 * TRNG entropy available status. 1349 * 1350 * @description 1351 * Definition of the format of the TRNG slice entropy status available. 1352 * struct. Used internally by the QAT FW. 1353 * 1354 *****************************************************************************/ 1355 typedef struct icp_qat_hw_trng_entropy_status_s { 1356 uint32_t status; 1357 /**< Entropy status in the TRNG */ 1358 1359 uint8_t reserved[QAT_HW_TRNG_ENTROPY_STS_RSVD_SZ]; 1360 /**< Reserved */ 1361 } icp_qat_hw_trng_entropy_status_t; 1362 1363 #define ICP_QAT_HW_TRNG_ENTROPY_AVAIL 1 1364 /**< @ingroup icp_qat_hw_defs 1365 * Flag indicating that entropy data is available in the QAT TRNG slice */ 1366 1367 #define ICP_QAT_HW_TRNG_ENTROPY_NOT_AVAIL 0 1368 /**< @ingroup icp_qat_hw_defs 1369 * Flag indicating that no entropy data is available in the QAT TRNG slice */ 1370 1371 /* Private defines */ 1372 #define QAT_TRNG_ENTROPY_STATUS_MASK 1 1373 /**< @ingroup icp_qat_hw_defs 1374 * Mask of one bit used to determine the TRNG Entropy status */ 1375 1376 #define QAT_TRNG_ENTROPY_STATUS_BITPOS 0 1377 /**< @ingroup icp_qat_hw_defs 1378 * Starting bit position for TRNG Entropy status. */ 1379 1380 /** 1381 ****************************************************************************** 1382 * @ingroup icp_qat_hw_defs 1383 * 1384 * @description 1385 * Extract the entropy available status bit 1386 * 1387 * @param status TRNG status value 1388 * 1389 *****************************************************************************/ 1390 #define ICP_QAT_HW_TRNG_ENTROPY_STATUS_GET(status) \ 1391 (((status) >> QAT_TRNG_ENTROPY_STATUS_BITPOS) & \ 1392 QAT_TRNG_ENTROPY_STATUS_MASK) 1393 1394 /** 1395 ***************************************************************************** 1396 * @ingroup icp_qat_hw_defs 1397 * Entropy seed data 1398 * 1399 * @description 1400 * This type is used for the definition of the entropy generated by a read 1401 * of the TRNG slice 1402 * 1403 *****************************************************************************/ 1404 typedef uint64_t icp_qat_hw_trng_entropy; 1405 1406 /* ========================================================================= */ 1407 /* COMPRESSION SLICE */ 1408 /* ========================================================================= */ 1409 1410 /** 1411 ***************************************************************************** 1412 * @ingroup icp_qat_hw_defs 1413 * Definition of the supported compression directions 1414 * @description 1415 * Enumeration used to define the compression directions 1416 * 1417 *****************************************************************************/ 1418 1419 typedef enum { 1420 ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0, /*!< Compression */ 1421 ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1, /*!< Decompression */ 1422 ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2 /**< Delimiter type */ 1423 } icp_qat_hw_compression_direction_t; 1424 1425 /** 1426 ***************************************************************************** 1427 * @ingroup icp_qat_hw_defs 1428 * Definition of the supported delayed match modes 1429 * @description 1430 * Enumeration used to define whether delayed match is enabled 1431 * 1432 *****************************************************************************/ 1433 1434 typedef enum { 1435 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0, 1436 /*!< Delayed match disabled */ 1437 1438 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1, 1439 /*!< Delayed match enabled 1440 Note: This is the only valid mode - refer to CPM1.6 SAS */ 1441 1442 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2 1443 /**< Delimiter type */ 1444 1445 } icp_qat_hw_compression_delayed_match_t; 1446 1447 /** 1448 ***************************************************************************** 1449 * @ingroup icp_qat_hw_defs 1450 * Definition of the supported compression algorithms 1451 * @description 1452 * Enumeration used to define the compression algorithms 1453 * 1454 *****************************************************************************/ 1455 1456 typedef enum { 1457 ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, /*!< Deflate compression */ 1458 ICP_QAT_HW_COMPRESSION_DEPRECATED = 1, /*!< Deprecated */ 1459 ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 /**< Delimiter type */ 1460 } icp_qat_hw_compression_algo_t; 1461 1462 /** 1463 ***************************************************************************** 1464 * @ingroup icp_qat_hw_defs 1465 * Definition of the supported compression depths 1466 * @description 1467 * Enumeration used to define the compression slice depths. 1468 * 1469 *****************************************************************************/ 1470 1471 typedef enum { 1472 ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0, 1473 /*!< Search depth 1 (Fastest least exhaustive) */ 1474 1475 ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1, 1476 /*!< Search depth 4 */ 1477 1478 ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2, 1479 /*!< Search depth 8 */ 1480 1481 ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3, 1482 /*!< Search depth 16 */ 1483 1484 ICP_QAT_HW_COMPRESSION_DEPTH_128 = 4, 1485 /*!< Search depth 128 (Slowest, most exhaustive) */ 1486 1487 ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 5 1488 /**< Delimiter type */ 1489 1490 } icp_qat_hw_compression_depth_t; 1491 1492 /** 1493 ***************************************************************************** 1494 * @ingroup icp_qat_hw_defs 1495 * Definition of the supported file types 1496 * @description 1497 * Enumeration used to define the compression file types. 1498 * 1499 *****************************************************************************/ 1500 1501 typedef enum { 1502 ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0, 1503 /*!< Use Static Trees */ 1504 1505 ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1, 1506 /*!< Use Semi-Dynamic Trees at offset 0 */ 1507 1508 ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2, 1509 /*!< Use Semi-Dynamic Trees at offset 320 */ 1510 1511 ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3, 1512 /*!< Use Semi-Dynamic Trees at offset 640 */ 1513 1514 ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4, 1515 /*!< Use Semi-Dynamic Trees at offset 960 */ 1516 1517 ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5 1518 /**< Delimiter type */ 1519 1520 } icp_qat_hw_compression_file_type_t; 1521 1522 typedef enum { 1523 BNP_SKIP_MODE_DISABLED = 0, 1524 BNP_SKIP_MODE_AT_START = 1, 1525 BNP_SKIP_MODE_AT_END = 2, 1526 BNP_SKIP_MODE_STRIDE = 3 1527 } icp_qat_bnp_skip_mode_t; 1528 1529 /** 1530 ***************************************************************************** 1531 * @ingroup icp_qat_hw_defs 1532 * Compression Configuration Struct 1533 * 1534 * @description 1535 * Configuration data used for setting up the QAT Compression Slice 1536 * 1537 *****************************************************************************/ 1538 1539 typedef struct icp_qat_hw_compression_config_s { 1540 uint32_t lower_val; 1541 /**< Compression slice configuration lower LW */ 1542 1543 uint32_t upper_val; 1544 /**< Compression slice configuration upper LW */ 1545 } icp_qat_hw_compression_config_t; 1546 1547 /* Private defines */ 1548 #define QAT_COMPRESSION_DIR_BITPOS 4 1549 /**< @ingroup icp_qat_hw_defs 1550 * Define for the compression direction bit position */ 1551 1552 #define QAT_COMPRESSION_DIR_MASK 0x7 1553 /**< @ingroup icp_qat_hw_defs 1554 * Define for the compression direction mask (three bits) */ 1555 1556 #define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16 1557 /**< @ingroup icp_qat_hw_defs 1558 * Define for the compression delayed match bit position */ 1559 1560 #define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1 1561 /**< @ingroup icp_qat_hw_defs 1562 * Define for the delayed match mask (one bit) */ 1563 1564 #define QAT_COMPRESSION_ALGO_BITPOS 31 1565 /**< @ingroup icp_qat_hw_defs 1566 * Define for the compression algorithm bit position */ 1567 1568 #define QAT_COMPRESSION_ALGO_MASK 0x1 1569 /**< @ingroup icp_qat_hw_defs 1570 * Define for the compression algorithm mask (one bit) */ 1571 1572 #define QAT_COMPRESSION_DEPTH_BITPOS 28 1573 /**< @ingroup icp_qat_hw_defs 1574 * Define for the compression depth bit position */ 1575 1576 #define QAT_COMPRESSION_DEPTH_MASK 0x7 1577 /**< @ingroup icp_qat_hw_defs 1578 * Define for the compression depth mask (three bits) */ 1579 1580 #define QAT_COMPRESSION_FILE_TYPE_BITPOS 24 1581 /**< @ingroup icp_qat_hw_defs 1582 * Define for the compression file type bit position */ 1583 1584 #define QAT_COMPRESSION_FILE_TYPE_MASK 0xF 1585 /**< @ingroup icp_qat_hw_defs 1586 * Define for the compression file type mask (four bits) */ 1587 1588 /** 1589 ****************************************************************************** 1590 * @ingroup icp_qat_hw_defs 1591 * 1592 * @description 1593 * Build the compression slice configuration field 1594 * 1595 * @param dir Compression Direction to use, compress or decompress 1596 * @param delayed Specify if delayed match should be enabled 1597 * @param algo Compression algorithm to use 1598 * @param depth Compression search depth to use 1599 * @param filetype Compression file type to use, static or semi dynamic trees 1600 * 1601 *****************************************************************************/ 1602 #define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \ 1603 dir, delayed, algo, depth, filetype) \ 1604 ((((dir)&QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \ 1605 (((delayed)&QAT_COMPRESSION_DELAYED_MATCH_MASK) \ 1606 << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \ 1607 (((algo)&QAT_COMPRESSION_ALGO_MASK) << QAT_COMPRESSION_ALGO_BITPOS) | \ 1608 (((depth)&QAT_COMPRESSION_DEPTH_MASK) \ 1609 << QAT_COMPRESSION_DEPTH_BITPOS) | \ 1610 (((filetype)&QAT_COMPRESSION_FILE_TYPE_MASK) \ 1611 << QAT_COMPRESSION_FILE_TYPE_BITPOS)) 1612 1613 /* ========================================================================= */ 1614 /* TRANSLATOR SLICE */ 1615 /* ========================================================================= */ 1616 1617 /**< Translator slice configuration is set internally by the firmware */ 1618 1619 #endif /* _ICP_QAT_HW_H_ */
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