adf_gen4_hw_data.c

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    1 /* SPDX-License-Identifier: BSD-3-Clause */
    2 /* Copyright(c) 2021 Intel Corporation */
    3 /* $FreeBSD$ */
    4 #include "adf_accel_devices.h"
    5 #include "adf_gen4_hw_data.h"
    6 
    7 static u64
    8 build_csr_ring_base_addr(bus_addr_t addr, u32 size)
    9 {
   10         return BUILD_RING_BASE_ADDR(addr, size);
   11 }
   12 
   13 static u32
   14 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring)
   15 {
   16         return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
   17 }
   18 
   19 static void
   20 write_csr_ring_head(struct resource *csr_base_addr,
   21                     u32 bank,
   22                     u32 ring,
   23                     u32 value)
   24 {
   25         WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
   26 }
   27 
   28 static u32
   29 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring)
   30 {
   31         return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
   32 }
   33 
   34 static void
   35 write_csr_ring_tail(struct resource *csr_base_addr,
   36                     u32 bank,
   37                     u32 ring,
   38                     u32 value)
   39 {
   40         WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
   41 }
   42 
   43 static u32
   44 read_csr_e_stat(struct resource *csr_base_addr, u32 bank)
   45 {
   46         return READ_CSR_E_STAT(csr_base_addr, bank);
   47 }
   48 
   49 static void
   50 write_csr_ring_config(struct resource *csr_base_addr,
   51                       u32 bank,
   52                       u32 ring,
   53                       u32 value)
   54 {
   55         WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
   56 }
   57 
   58 static void
   59 write_csr_ring_base(struct resource *csr_base_addr,
   60                     u32 bank,
   61                     u32 ring,
   62                     bus_addr_t addr)
   63 {
   64         WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
   65 }
   66 
   67 static void
   68 write_csr_int_flag(struct resource *csr_base_addr, u32 bank, u32 value)
   69 {
   70         WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
   71 }
   72 
   73 static void
   74 write_csr_int_srcsel(struct resource *csr_base_addr, u32 bank)
   75 {
   76         WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
   77 }
   78 
   79 static void
   80 write_csr_int_col_en(struct resource *csr_base_addr, u32 bank, u32 value)
   81 {
   82         WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
   83 }
   84 
   85 static void
   86 write_csr_int_col_ctl(struct resource *csr_base_addr, u32 bank, u32 value)
   87 {
   88         WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
   89 }
   90 
   91 static void
   92 write_csr_int_flag_and_col(struct resource *csr_base_addr, u32 bank, u32 value)
   93 {
   94         WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
   95 }
   96 
   97 static u32
   98 read_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank)
   99 {
  100         return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);
  101 }
  102 
  103 static void
  104 write_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank, u32 value)
  105 {
  106         WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
  107 }
  108 
  109 void
  110 adf_gen4_init_hw_csr_info(struct adf_hw_csr_info *csr_info)
  111 {
  112         struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops;
  113 
  114         csr_info->arb_enable_mask = 0x1;
  115 
  116         csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
  117         csr_ops->read_csr_ring_head = read_csr_ring_head;
  118         csr_ops->write_csr_ring_head = write_csr_ring_head;
  119         csr_ops->read_csr_ring_tail = read_csr_ring_tail;
  120         csr_ops->write_csr_ring_tail = write_csr_ring_tail;
  121         csr_ops->read_csr_e_stat = read_csr_e_stat;
  122         csr_ops->write_csr_ring_config = write_csr_ring_config;
  123         csr_ops->write_csr_ring_base = write_csr_ring_base;
  124         csr_ops->write_csr_int_flag = write_csr_int_flag;
  125         csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
  126         csr_ops->write_csr_int_col_en = write_csr_int_col_en;
  127         csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
  128         csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
  129         csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en;
  130         csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
  131 }
  132 EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_info);
  133 
  134 static inline void
  135 adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper, u32 *lower)
  136 {
  137         *lower = lower_32_bits(value);
  138         *upper = upper_32_bits(value);
  139 }
  140 
  141 int
  142 adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
  143 {
  144         struct adf_hw_device_data *hw_data = accel_dev->hw_device;
  145         u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
  146         u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
  147         u32 ssm_wdt_pke_high = 0;
  148         u32 ssm_wdt_pke_low = 0;
  149         u32 ssm_wdt_high = 0;
  150         u32 ssm_wdt_low = 0;
  151         struct resource *pmisc_addr;
  152         struct adf_bar *pmisc;
  153         int pmisc_id;
  154 
  155         pmisc_id = hw_data->get_misc_bar_id(hw_data);
  156         pmisc = &GET_BARS(accel_dev)[pmisc_id];
  157         pmisc_addr = pmisc->virt_addr;
  158 
  159         /* Convert 64bit WDT timer value into 32bit values for
  160          * mmio write to 32bit CSRs.
  161          */
  162         adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low);
  163         adf_gen4_unpack_ssm_wdtimer(timer_val_pke,
  164                                     &ssm_wdt_pke_high,
  165                                     &ssm_wdt_pke_low);
  166 
  167         /* Enable WDT for sym and dc */
  168         ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low);
  169         ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high);
  170         /* Enable WDT for pke */
  171         ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low);
  172         ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high);
  173 
  174         return 0;
  175 }
  176 EXPORT_SYMBOL_GPL(adf_gen4_set_ssm_wdtimer);

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FreeBSD/Linux Kernel Cross Reference sys/dev/qat/qat_common/adf_gen4_hw_data.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/qat/qat_common/adf_gen4_hw_data.c