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sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_inline.h
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1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_C4XXX_INLINE_H_ 5 #define ADF_C4XXX_INLINE_H_ 6 7 /* Inline register addresses in SRAM BAR */ 8 #define ARAM_CSR_BAR_OFFSET 0x100000 9 #define ADF_C4XXX_REG_SA_CTRL_LOCK (ARAM_CSR_BAR_OFFSET + 0x00) 10 #define ADF_C4XXX_REG_SA_SCRATCH_0 (ARAM_CSR_BAR_OFFSET + 0x04) 11 #define ADF_C4XXX_REG_SA_SCRATCH_2 (ARAM_CSR_BAR_OFFSET + 0x0C) 12 #define ADF_C4XXX_REG_SA_ENTRY_CTRL (ARAM_CSR_BAR_OFFSET + 0x18) 13 #define ADF_C4XXX_REG_SA_DB_CTRL (ARAM_CSR_BAR_OFFSET + 0x1C) 14 #define ADF_C4XXX_REG_SA_REMAP (ARAM_CSR_BAR_OFFSET + 0x20) 15 #define ADF_C4XXX_REG_SA_INLINE_CAPABILITY (ARAM_CSR_BAR_OFFSET + 0x24) 16 #define ADF_C4XXX_REG_SA_INLINE_ENABLE (ARAM_CSR_BAR_OFFSET + 0x28) 17 #define ADF_C4XXX_REG_SA_LINK_UP (ARAM_CSR_BAR_OFFSET + 0x2C) 18 #define ADF_C4XXX_REG_SA_FUNC_LIMITS (ARAM_CSR_BAR_OFFSET + 0x38) 19 20 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24) 21 #define ADF_C4XXX_SADB_SIZE_IN_WORDS(accel_dev) \ 22 ((accel_dev)->aram_info->sadb_region_size / 32) 23 #define ADF_C4XXX_DEFAULT_MAX_CHAIN_LEN 0 24 #define ADF_C4XXX_DEFAULT_LIMIT_CHAIN_LEN 0 25 /* SADB CTRL register bit offsets */ 26 #define ADF_C4XXX_SADB_BIT_OFFSET 6 27 #define ADF_C4XXX_MAX_CHAIN_LEN_BIT_OFFS 1 28 29 #define ADF_C4XXX_SADB_REG_VALUE(accel_dev) \ 30 ((ADF_C4XXX_SADB_SIZE_IN_WORDS(accel_dev) \ 31 << ADF_C4XXX_SADB_BIT_OFFSET) | \ 32 (ADF_C4XXX_DEFAULT_MAX_CHAIN_LEN \ 33 << ADF_C4XXX_MAX_CHAIN_LEN_BIT_OFFS) | \ 34 (ADF_C4XXX_DEFAULT_LIMIT_CHAIN_LEN)) 35 36 #define ADF_C4XXX_INLINE_INGRESS_OFFSET 0x0 37 #define ADF_C4XXX_INLINE_EGRESS_OFFSET 0x1000 38 39 /* MAC_CFG register access related definitions */ 40 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16) 41 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16) 42 #define ADF_C4XXX_UNLOCK true 43 #define ADF_C4XXX_LOCK false 44 45 /* MAC IP register access related definitions */ 46 #define ADF_C4XXX_MAC_STATS_READY BIT(0) 47 #define ADF_C4XXX_MAX_NUM_STAT_READY_READS 10 48 #define ADF_C4XXX_MAC_STATS_POLLING_INTERVAL 100 49 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6) 50 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7) 51 #define ADF_C4XXX_MAC_ERROR_TX_DATA_CORRUPT BIT(8) 52 #define ADF_C4XXX_MAC_ERROR_RX_OVERRUN BIT(9) 53 #define ADF_C4XXX_MAC_ERROR_RX_RUNT BIT(10) 54 #define ADF_C4XXX_MAC_ERROR_RX_UNDERSIZE BIT(11) 55 #define ADF_C4XXX_MAC_ERROR_RX_JABBER BIT(12) 56 #define ADF_C4XXX_MAC_ERROR_RX_OVERSIZE BIT(13) 57 #define ADF_C4XXX_MAC_ERROR_RX_FCS BIT(14) 58 #define ADF_C4XXX_MAC_ERROR_RX_FRAME BIT(15) 59 #define ADF_C4XXX_MAC_ERROR_RX_CODE BIT(16) 60 #define ADF_C4XXX_MAC_ERROR_RX_PREAMBLE BIT(17) 61 #define ADF_C4XXX_MAC_RX_LINK_UP BIT(21) 62 #define ADF_C4XXX_MAC_INVALID_SPEED BIT(31) 63 #define ADF_C4XXX_MAC_PIA_RX_FIFO_OVERRUN (1ULL << 32) 64 #define ADF_C4XXX_MAC_PIA_TX_FIFO_OVERRUN (1ULL << 33) 65 #define ADF_C4XXX_MAC_PIA_TX_FIFO_UNDERRUN (1ULL << 34) 66 67 /* 64-bit inline control registers. It will require 68 * adding ADF_C4XXX_INLINE_INGRESS_OFFSET to the address for ingress 69 * direction or ADF_C4XXX_INLINE_EGRESS_OFFSET to the address for 70 * egress direction 71 */ 72 #define ADF_C4XXX_MAC_IP 0x8 73 #define ADF_C4XXX_MAC_CFG 0x18 74 #define ADF_C4XXX_MAC_PIA_CFG 0xA0 75 76 /* Default MAC_CFG value 77 * - MAC_LINKUP_ENABLE = 1 78 * - MAX_FRAME_LENGTH = 0x2600 79 */ 80 #define ADF_C4XXX_MAC_CFG_VALUE 0x00000000FA0C2600 81 82 /* Bit definitions for MAC_PIA_CFG register */ 83 #define ADF_C4XXX_ONPI_ENABLE BIT(0) 84 #define ADF_C4XXX_XOFF_ENABLE BIT(10) 85 86 /* New default value for MAC_PIA_CFG register */ 87 #define ADF_C4XXX_MAC_PIA_CFG_VALUE \ 88 (ADF_C4XXX_XOFF_ENABLE | ADF_C4XXX_ONPI_ENABLE) 89 90 /* 64-bit Inline statistics registers. It will require 91 * adding ADF_C4XXX_INLINE_INGRESS_OFFSET to the address for ingress 92 * direction or ADF_C4XXX_INLINE_EGRESS_OFFSET to the address for 93 * egress direction 94 */ 95 #define ADF_C4XXX_MAC_STAT_TX_OCTET 0x100 96 #define ADF_C4XXX_MAC_STAT_TX_FRAME 0x110 97 #define ADF_C4XXX_MAC_STAT_TX_BAD_FRAME 0x118 98 #define ADF_C4XXX_MAC_STAT_TX_FCS_ERROR 0x120 99 #define ADF_C4XXX_MAC_STAT_TX_64 0x130 100 #define ADF_C4XXX_MAC_STAT_TX_65 0x138 101 #define ADF_C4XXX_MAC_STAT_TX_128 0x140 102 #define ADF_C4XXX_MAC_STAT_TX_256 0x148 103 #define ADF_C4XXX_MAC_STAT_TX_512 0x150 104 #define ADF_C4XXX_MAC_STAT_TX_1024 0x158 105 #define ADF_C4XXX_MAC_STAT_TX_1519 0x160 106 #define ADF_C4XXX_MAC_STAT_TX_JABBER 0x168 107 #define ADF_C4XXX_MAC_STAT_RX_OCTET 0x200 108 #define ADF_C4XXX_MAC_STAT_RX_FRAME 0x210 109 #define ADF_C4XXX_MAC_STAT_RX_BAD_FRAME 0x218 110 #define ADF_C4XXX_MAC_STAT_RX_FCS_ERROR 0x220 111 #define ADF_C4XXX_MAC_STAT_RX_64 0x250 112 #define ADF_C4XXX_MAC_STAT_RX_65 0x258 113 #define ADF_C4XXX_MAC_STAT_RX_128 0x260 114 #define ADF_C4XXX_MAC_STAT_RX_256 0x268 115 #define ADF_C4XXX_MAC_STAT_RX_512 0x270 116 #define ADF_C4XXX_MAC_STAT_RX_1024 0x278 117 #define ADF_C4XXX_MAC_STAT_RX_1519 0x280 118 #define ADF_C4XXX_MAC_STAT_RX_OVERSIZE 0x288 119 #define ADF_C4XXX_MAC_STAT_RX_JABBER 0x290 120 121 /* 32-bit Inline statistics registers. It will require 122 * adding ADF_C4XXX_INLINE_INGRESS_OFFSET to the address for ingress 123 * direction or ADF_C4XXX_INLINE_EGRESS_OFFSET to the address for 124 * egress direction 125 */ 126 #define ADF_C4XXX_IC_PAR_IPSEC_DESC_COUNT 0xBC0 127 #define ADF_C4XXX_IC_PAR_MIXED_DESC_COUNT 0xBC4 128 #define ADF_C4XXX_IC_PAR_FULLY_CLEAR_DESC_COUNT 0xBC8 129 #define ADF_C4XXX_IC_PAR_CLR_COUNT 0xBCC 130 #define ADF_C4XXX_IC_CTPB_PKT_COUNT 0xDF4 131 #define ADF_C4XXX_RB_DATA_COUNT 0xDF8 132 #define ADF_C4XXX_IC_CLEAR_DESC_COUNT 0xDFC 133 #define ADF_C4XXX_IC_IPSEC_DESC_COUNT 0xE00 134 135 /* REG_CMD_DIS_MISC bit definitions */ 136 #define ADF_C4XXX_BYTE_SWAP_ENABLE BIT(0) 137 #define ADF_C4XXX_REG_CMD_DIS_MISC_DEFAULT_VALUE (ADF_C4XXX_BYTE_SWAP_ENABLE) 138 139 /* Command Dispatch Misc Register */ 140 #define ADF_C4XXX_INGRESS_CMD_DIS_MISC (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0x8A8) 141 142 #define ADF_C4XXX_EGRESS_CMD_DIS_MISC (ADF_C4XXX_INLINE_EGRESS_OFFSET + 0x8A8) 143 144 /* Congestion management threshold registers */ 145 #define ADF_C4XXX_NEXT_FCTHRESH_OFFSET 4 146 147 /* Number of congestion management domains */ 148 #define ADF_C4XXX_NUM_CONGEST_DOMAINS 8 149 150 #define ADF_C4XXX_BB_FCHTHRESH_OFFSET 0xB78 151 152 /* IC_BB_FCHTHRESH registers */ 153 #define ADF_C4XXX_ICI_BB_FCHTHRESH_OFFSET \ 154 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_FCHTHRESH_OFFSET) 155 156 #define ADF_C4XXX_ICE_BB_FCHTHRESH_OFFSET \ 157 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_FCHTHRESH_OFFSET) 158 159 #define ADF_C4XXX_WR_ICI_BB_FCHTHRESH(csr_base_addr, index, value) \ 160 ADF_CSR_WR(csr_base_addr, \ 161 (ADF_C4XXX_ICI_BB_FCHTHRESH_OFFSET + \ 162 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 163 value) 164 165 #define ADF_C4XXX_WR_ICE_BB_FCHTHRESH(csr_base_addr, index, value) \ 166 ADF_CSR_WR(csr_base_addr, \ 167 (ADF_C4XXX_ICE_BB_FCHTHRESH_OFFSET + \ 168 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 169 value) 170 171 #define ADF_C4XXX_BB_FCLTHRESH_OFFSET 0xB98 172 173 /* IC_BB_FCLTHRESH registers */ 174 #define ADF_C4XXX_ICI_BB_FCLTHRESH_OFFSET \ 175 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_FCLTHRESH_OFFSET) 176 177 #define ADF_C4XXX_ICE_BB_FCLTHRESH_OFFSET \ 178 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_FCLTHRESH_OFFSET) 179 180 #define ADF_C4XXX_WR_ICI_BB_FCLTHRESH(csr_base_addr, index, value) \ 181 ADF_CSR_WR(csr_base_addr, \ 182 (ADF_C4XXX_ICI_BB_FCLTHRESH_OFFSET + \ 183 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 184 value) 185 186 #define ADF_C4XXX_WR_ICE_BB_FCLTHRESH(csr_base_addr, index, value) \ 187 ADF_CSR_WR(csr_base_addr, \ 188 (ADF_C4XXX_ICE_BB_FCLTHRESH_OFFSET + \ 189 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 190 value) 191 192 #define ADF_C4XXX_BB_BEHTHRESH_OFFSET 0xBB8 193 #define ADF_C4XXX_BB_BELTHRESH_OFFSET 0xBBC 194 #define ADF_C4XXX_BEWIP_THRESH_OFFSET 0xDEC 195 #define ADF_C4XXX_CTPB_THRESH_OFFSET 0xDE8 196 #define ADF_C4XXX_CIRQ_OFFSET 0xDE4 197 #define ADF_C4XXX_Q2MEMAP_OFFSET 0xC04 198 199 /* IC_BB_BEHTHRESH register */ 200 #define ADF_C4XXX_ICI_BB_BEHTHRESH_OFFSET \ 201 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_BEHTHRESH_OFFSET) 202 203 #define ADF_C4XXX_ICE_BB_BEHTHRESH_OFFSET \ 204 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_BEHTHRESH_OFFSET) 205 206 /* IC_BB_BELTHRESH register */ 207 #define ADF_C4XXX_ICI_BB_BELTHRESH_OFFSET \ 208 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_BELTHRESH_OFFSET) 209 210 #define ADF_C4XXX_ICE_BB_BELTHRESH_OFFSET \ 211 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_BELTHRESH_OFFSET) 212 213 /* IC_BEWIP_THRESH register */ 214 #define ADF_C4XXX_ICI_BEWIP_THRESH_OFFSET \ 215 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BEWIP_THRESH_OFFSET) 216 217 #define ADF_C4XXX_ICE_BEWIP_THRESH_OFFSET \ 218 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BEWIP_THRESH_OFFSET) 219 220 /* IC_CTPB_THRESH register */ 221 #define ADF_C4XXX_ICI_CTPB_THRESH_OFFSET \ 222 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_CTPB_THRESH_OFFSET) 223 224 #define ADF_C4XXX_ICE_CTPB_THRESH_OFFSET \ 225 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_CTPB_THRESH_OFFSET) 226 227 /* ADF_C4XXX_ICI_CIRQ_OFFSET */ 228 #define ADF_C4XXX_ICI_CIRQ_OFFSET \ 229 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_CIRQ_OFFSET) 230 231 #define ADF_C4XXX_ICE_CIRQ_OFFSET \ 232 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_CIRQ_OFFSET) 233 234 /* IC_Q2MEMAP register */ 235 #define ADF_C4XXX_ICI_Q2MEMAP_OFFSET \ 236 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_Q2MEMAP_OFFSET) 237 238 #define ADF_C4XXX_ICE_Q2MEMAP_OFFSET \ 239 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_Q2MEMAP_OFFSET) 240 241 #define ADF_C4XXX_NEXT_Q2MEMAP_OFFSET 4 242 #define ADF_C4XXX_NUM_Q2MEMAP_REGISTERS 8 243 244 #define ADF_C4XXX_WR_CSR_ICI_Q2MEMAP(csr_base_addr, index, value) \ 245 ADF_CSR_WR(csr_base_addr, \ 246 (ADF_C4XXX_ICI_Q2MEMAP_OFFSET + \ 247 (index)*ADF_C4XXX_NEXT_Q2MEMAP_OFFSET), \ 248 value) 249 250 #define ADF_C4XXX_WR_CSR_ICE_Q2MEMAP(csr_base_addr, index, value) \ 251 ADF_CSR_WR(csr_base_addr, \ 252 (ADF_C4XXX_ICE_Q2MEMAP_OFFSET + \ 253 (index)*ADF_C4XXX_NEXT_Q2MEMAP_OFFSET), \ 254 value) 255 256 /* IC_PARSE_CTRL register */ 257 #define ADF_C4XXX_DEFAULT_KEY_LENGTH 21 258 #define ADF_C4XXX_DEFAULT_REL_ABS_OFFSET 1 259 #define ADF_C4XXX_DEFAULT_NUM_TUPLES 4 260 #define ADF_C4XXX_IC_PARSE_CTRL_OFFSET_DEFAULT_VALUE \ 261 ((ADF_C4XXX_DEFAULT_KEY_LENGTH << 4) | \ 262 (ADF_C4XXX_DEFAULT_REL_ABS_OFFSET << 3) | \ 263 (ADF_C4XXX_DEFAULT_NUM_TUPLES)) 264 265 /* Configuration parsing register definitions */ 266 #define ADF_C4XXX_IC_PARSE_CTRL_OFFSET (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB00) 267 268 /* Fixed data parsing register */ 269 #define ADF_C4XXX_IC_PARSE_FIXED_DATA(i) \ 270 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB04 + ((i)*4)) 271 #define ADF_C4XXX_DEFAULT_IC_PARSE_FIXED_DATA_0 0x32 272 273 /* Fixed length parsing register */ 274 #define ADF_C4XXX_IC_PARSE_FIXED_LENGTH \ 275 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB14) 276 #define ADF_C4XXX_DEFAULT_IC_PARSE_FIXED_LEN 0x0 277 278 /* IC_PARSE_IPV4 offset and length registers */ 279 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_0 \ 280 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB18) 281 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_1 \ 282 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB1C) 283 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_2 \ 284 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB20) 285 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_3 \ 286 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB24) 287 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_4 \ 288 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB28) 289 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_5 \ 290 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB2C) 291 292 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_0 \ 293 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB30) 294 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_1 \ 295 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB34) 296 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_2 \ 297 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB38) 298 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_3 \ 299 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB3C) 300 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_4 \ 301 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB40) 302 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_5 \ 303 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB44) 304 305 #define ADF_C4XXX_IPV4_OFFSET_0_PARSER_BASE 0x1 306 #define ADF_C4XXX_IPV4_OFFSET_0_OFFSET 0x0 307 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_0_VALUE \ 308 ((ADF_C4XXX_IPV4_OFFSET_0_PARSER_BASE << 29) | \ 309 ADF_C4XXX_IPV4_OFFSET_0_OFFSET) 310 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_0_VALUE 0 311 312 #define ADF_C4XXX_IPV4_OFFSET_1_PARSER_BASE 0x2 313 #define ADF_C4XXX_IPV4_OFFSET_1_OFFSET 0x0 314 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_1_VALUE \ 315 ((ADF_C4XXX_IPV4_OFFSET_1_PARSER_BASE << 29) | \ 316 ADF_C4XXX_IPV4_OFFSET_1_OFFSET) 317 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_1_VALUE 3 318 319 #define ADF_C4XXX_IPV4_OFFSET_2_PARSER_BASE 0x4 320 #define ADF_C4XXX_IPV4_OFFSET_2_OFFSET 0x10 321 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_2_VALUE \ 322 ((ADF_C4XXX_IPV4_OFFSET_2_PARSER_BASE << 29) | \ 323 ADF_C4XXX_IPV4_OFFSET_2_OFFSET) 324 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_2_VALUE 3 325 326 #define ADF_C4XXX_IPV4_OFFSET_3_PARSER_BASE 0x0 327 #define ADF_C4XXX_IPV4_OFFSET_3_OFFSET 0x0 328 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_3_VALUE \ 329 ((ADF_C4XXX_IPV4_OFFSET_3_PARSER_BASE << 29) | \ 330 ADF_C4XXX_IPV4_OFFSET_3_OFFSET) 331 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_3_VALUE 0 332 333 /* IC_PARSE_IPV6 offset and length registers */ 334 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_0 \ 335 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB48) 336 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_1 \ 337 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB4C) 338 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_2 \ 339 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB50) 340 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_3 \ 341 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB54) 342 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_4 \ 343 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB58) 344 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_5 \ 345 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB5C) 346 347 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_0 \ 348 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB60) 349 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_1 \ 350 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB64) 351 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_2 \ 352 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB68) 353 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_3 \ 354 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB6C) 355 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_4 \ 356 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB70) 357 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_5 \ 358 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB74) 359 360 #define ADF_C4XXX_IPV6_OFFSET_0_PARSER_BASE 0x1 361 #define ADF_C4XXX_IPV6_OFFSET_0_OFFSET 0x0 362 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_0_VALUE \ 363 ((ADF_C4XXX_IPV6_OFFSET_0_PARSER_BASE << 29) | \ 364 (ADF_C4XXX_IPV6_OFFSET_0_OFFSET)) 365 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_0_VALUE 0 366 367 #define ADF_C4XXX_IPV6_OFFSET_1_PARSER_BASE 0x2 368 #define ADF_C4XXX_IPV6_OFFSET_1_OFFSET 0x0 369 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_1_VALUE \ 370 ((ADF_C4XXX_IPV6_OFFSET_1_PARSER_BASE << 29) | \ 371 (ADF_C4XXX_IPV6_OFFSET_1_OFFSET)) 372 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_1_VALUE 3 373 374 #define ADF_C4XXX_IPV6_OFFSET_2_PARSER_BASE 0x4 375 #define ADF_C4XXX_IPV6_OFFSET_2_OFFSET 0x18 376 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_2_VALUE \ 377 ((ADF_C4XXX_IPV6_OFFSET_2_PARSER_BASE << 29) | \ 378 (ADF_C4XXX_IPV6_OFFSET_2_OFFSET)) 379 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_2_VALUE 0xF 380 381 #define ADF_C4XXX_IPV6_OFFSET_3_PARSER_BASE 0x0 382 #define ADF_C4XXX_IPV6_OFFSET_3_OFFSET 0x0 383 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_3_VALUE \ 384 ((ADF_C4XXX_IPV6_OFFSET_3_PARSER_BASE << 29) | \ 385 (ADF_C4XXX_IPV6_OFFSET_3_OFFSET)) 386 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_3_VALUE 0x0 387 388 /* error notification configuration registers */ 389 390 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_0 0xA00 391 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_1 0xA04 392 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_2 0xA08 393 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_3 0xA0C 394 #define ADF_C4XXX_IC_CD_CERR 0xA10 395 #define ADF_C4XXX_IC_CD_UERR 0xA14 396 397 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_0 0xF00 398 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_1 0xF04 399 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_2 0xF08 400 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_3 0xF0C 401 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_4 0xF10 402 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_5 0xF14 403 #define ADF_C4XXX_IC_PARSER_CERR 0xF18 404 #define ADF_C4XXX_IC_PARSER_UERR 0xF1C 405 #define ADF_C4XXX_IC_CTPB_CERR 0xF28 406 #define ADF_C4XXX_IC_CTPB_UERR 0xF2C 407 #define ADF_C4XXX_IC_CPPM_ERR_STAT 0xF3C 408 #define ADF_C4XXX_IC_CONGESTION_MGMT_INT 0xF58 409 410 #define ADF_C4XXX_IC_CPPT_ERR_STAT 0x704 411 #define ADF_C4XXX_IC_MAC_IM 0x10 412 413 #define ADF_C4XXX_CD_RF_PARITY_ERR_0_VAL 0x22222222 414 #define ADF_C4XXX_CD_RF_PARITY_ERR_1_VAL 0x22222323 415 #define ADF_C4XXX_CD_RF_PARITY_ERR_2_VAL 0x00022222 416 #define ADF_C4XXX_CD_RF_PARITY_ERR_3_VAL 0x00000000 417 #define ADF_C4XXX_CD_UERR_VAL 0x00000008 418 #define ADF_C4XXX_CD_CERR_VAL 0x00000008 419 #define ADF_C4XXX_PARSER_UERR_VAL 0x00100008 420 #define ADF_C4XXX_PARSER_CERR_VAL 0x00000008 421 #define ADF_C4XXX_INLN_RF_PARITY_ERR_0_VAL 0x33333333 422 #define ADF_C4XXX_INLN_RF_PARITY_ERR_1_VAL 0x33333333 423 #define ADF_C4XXX_INLN_RF_PARITY_ERR_2_VAL 0x33333333 424 #define ADF_C4XXX_INLN_RF_PARITY_ERR_3_VAL 0x22222222 425 #define ADF_C4XXX_INLN_RF_PARITY_ERR_4_VAL 0x22222222 426 #define ADF_C4XXX_INLN_RF_PARITY_ERR_5_VAL 0x00333232 427 #define ADF_C4XXX_CTPB_UERR_VAL 0x00000008 428 #define ADF_C4XXX_CTPB_CERR_VAL 0x00000008 429 #define ADF_C4XXX_CPPM_ERR_STAT_VAL 0x00007000 430 #define ADF_C4XXX_CPPT_ERR_STAT_VAL 0x000001C0 431 #define ADF_C4XXX_CONGESTION_MGMT_INI_VAL 0x00000001 432 #define ADF_C4XXX_MAC_IM_VAL 0x000000087FDC003E 433 434 /* parser ram ecc uerr */ 435 #define ADF_C4XXX_PARSER_UERR_INTR BIT(0) 436 /* multiple err */ 437 #define ADF_C4XXX_PARSER_MUL_UERR_INTR BIT(18) 438 #define ADF_C4XXX_PARSER_DESC_UERR_INTR_ENA BIT(20) 439 440 #define ADF_C4XXX_RF_PAR_ERR_BITS 32 441 #define ADF_C4XXX_MAX_STR_LEN 64 442 #define RF_PAR_MUL_MAP(bit_num) (((bit_num)-2) / 4) 443 #define RF_PAR_MAP(bit_num) (((bit_num)-3) / 4) 444 445 /* cd rf parity error 446 * BIT(2) rf parity mul 0 447 * BIT(3) rf parity 0 448 * BIT(10) rf parity mul 2 449 * BIT(11) rf parity 2 450 */ 451 #define ADF_C4XXX_CD_RF_PAR_ERR_1_INTR (BIT(2) | BIT(3) | BIT(10) | BIT(11)) 452 453 /* inln rf parity error 454 * BIT(2) rf parity mul 0 455 * BIT(3) rf parity 0 456 * BIT(6) rf parity mul 1 457 * BIT(7) rf parity 1 458 * BIT(10) rf parity mul 2 459 * BIT(11) rf parity 2 460 * BIT(14) rf parity mul 3 461 * BIT(15) rf parity 3 462 * BIT(18) rf parity mul 4 463 * BIT(19) rf parity 4 464 * BIT(22) rf parity mul 5 465 * BIT(23) rf parity 5 466 * BIT(26) rf parity mul 6 467 * BIT(27) rf parity 6 468 * BIT(30) rf parity mul 7 469 * BIT(31) rf parity 7 470 */ 471 #define ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR \ 472 (BIT(2) | BIT(3) | BIT(6) | BIT(7) | BIT(10) | BIT(11) | BIT(14) | \ 473 BIT(15) | BIT(18) | BIT(19) | BIT(22) | BIT(23) | BIT(26) | BIT(27) | \ 474 BIT(30) | BIT(31)) 475 #define ADF_C4XXX_INLN_RF_PAR_ERR_1_INTR ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR 476 #define ADF_C4XXX_INLN_RF_PAR_ERR_2_INTR ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR 477 #define ADF_C4XXX_INLN_RF_PAR_ERR_5_INTR \ 478 (BIT(6) | BIT(7) | BIT(14) | BIT(15) | BIT(18) | BIT(19) | BIT(22) | \ 479 BIT(23)) 480 481 /* Congestion mgmt events */ 482 #define ADF_C4XXX_CONGESTION_MGMT_CTPB_GLOBAL_CROSSED BIT(1) 483 #define ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_OUT BIT(2) 484 #define ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_IN BIT(3) 485 486 /* AEAD algorithm definitions in REG_SA_SCRATCH[0] register. 487 * Bits<6:5> are reserved for expansion. 488 */ 489 #define AES128_GCM BIT(0) 490 #define AES192_GCM BIT(1) 491 #define AES256_GCM BIT(2) 492 #define AES128_CCM BIT(3) 493 #define CHACHA20_POLY1305 BIT(4) 494 /* Cipher algorithm definitions in REG_SA_SCRATCH[0] register 495 * Bit<15> is reserved for expansion. 496 */ 497 #define CIPHER_NULL BIT(7) 498 #define AES128_CBC BIT(8) 499 #define AES192_CBC BIT(9) 500 #define AES256_CBC BIT(10) 501 #define AES128_CTR BIT(11) 502 #define AES192_CTR BIT(12) 503 #define AES256_CTR BIT(13) 504 #define _3DES_CBC BIT(14) 505 /* Authentication algorithm definitions in REG_SA_SCRATCH[0] register 506 * Bits<25:30> are reserved for expansion. 507 */ 508 #define HMAC_MD5_96 BIT(16) 509 #define HMAC_SHA1_96 BIT(17) 510 #define HMAC_SHA256_128 BIT(18) 511 #define HMAC_SHA384_192 BIT(19) 512 #define HMAC_SHA512_256 BIT(20) 513 #define AES_GMAC_AES_128 BIT(21) 514 #define AES_XCBC_MAC_96 BIT(22) 515 #define AES_CMAC_96 BIT(23) 516 #define AUTH_NULL BIT(24) 517 518 /* Algo group0:DEFAULT */ 519 #define ADF_C4XXX_DEFAULT_SUPPORTED_ALGORITHMS \ 520 (AES128_GCM | \ 521 (AES192_GCM | AES256_GCM | AES128_CCM | CHACHA20_POLY1305) | \ 522 (CIPHER_NULL | AES128_CBC | AES192_CBC | AES256_CBC) | \ 523 (AES128_CTR | AES192_CTR | AES256_CTR | _3DES_CBC) | \ 524 (HMAC_MD5_96 | HMAC_SHA1_96 | HMAC_SHA256_128) | \ 525 (HMAC_SHA384_192 | HMAC_SHA512_256 | AES_GMAC_AES_128) | \ 526 (AES_XCBC_MAC_96 | AES_CMAC_96 | AUTH_NULL)) 527 528 /* Algo group1 */ 529 #define ADF_C4XXX_SUPPORTED_ALGORITHMS_GROUP1 \ 530 (AES128_GCM | (AES256_GCM | CHACHA20_POLY1305)) 531 532 /* Supported crypto offload features in REG_SA_SCRATCH[2] register */ 533 #define ADF_C4XXX_IPSEC_ESP BIT(0) 534 #define ADF_C4XXX_IPSEC_AH BIT(1) 535 #define ADF_C4XXX_UDP_ENCAPSULATION BIT(2) 536 #define ADF_C4XXX_IPSEC_TUNNEL_MODE BIT(3) 537 #define ADF_C4XXX_IPSEC_TRANSPORT_MODE BIT(4) 538 #define ADF_C4XXX_IPSEC_EXT_SEQ_NUM BIT(5) 539 540 #define ADF_C4XXX_DEFAULT_CY_OFFLOAD_FEATURES \ 541 (ADF_C4XXX_IPSEC_ESP | \ 542 (ADF_C4XXX_UDP_ENCAPSULATION | ADF_C4XXX_IPSEC_TUNNEL_MODE) | \ 543 (ADF_C4XXX_IPSEC_TRANSPORT_MODE | ADF_C4XXX_IPSEC_EXT_SEQ_NUM)) 544 545 /* REG_SA_CTRL_LOCK default value */ 546 #define ADF_C4XXX_DEFAULT_SA_CTRL_LOCKOUT BIT(0) 547 548 /* SA ENTRY CTRL default values */ 549 #define ADF_C4XXX_DEFAULT_LU_KEY_LEN 21 550 551 /* Sa size for algo group0 */ 552 #define ADF_C4XXX_DEFAULT_SA_SIZE 6 553 554 /* Sa size for algo group1 */ 555 #define ADF_C4XXX_ALGO_GROUP1_SA_SIZE 2 556 557 /* SA size is based on 32byte granularity 558 * A value of zero indicates an SA size of 32 bytes 559 */ 560 #define ADF_C4XXX_SA_SIZE_IN_BYTES(sa_size) (((sa_size) + 1) * 32) 561 562 /* SA ENTRY CTRL register bit offsets */ 563 #define ADF_C4XXX_LU_KEY_LEN_BIT_OFFSET 5 564 565 /* REG_SA_FUNC_LIMITS default value */ 566 #define ADF_C4XXX_FUNC_LIMIT(accel_dev, sa_size) \ 567 (ADF_C4XXX_SADB_SIZE_IN_WORDS(accel_dev) / ((sa_size) + 1)) 568 569 /* REG_SA_INLINE_ENABLE bit definition */ 570 #define ADF_C4XXX_INLINE_ENABLED BIT(0) 571 572 /* REG_SA_INLINE_CAPABILITY bit definitions */ 573 #define ADF_C4XXX_INLINE_INGRESS_ENABLE BIT(0) 574 #define ADF_C4XXX_INLINE_EGRESS_ENABLE BIT(1) 575 #define ADF_C4XXX_INLINE_CAPABILITIES \ 576 (ADF_C4XXX_INLINE_INGRESS_ENABLE | ADF_C4XXX_INLINE_EGRESS_ENABLE) 577 578 /* Congestion management profile information */ 579 enum congest_mngt_profile_info { 580 CIRQ_CFG_1 = 0, 581 CIRQ_CFG_2, 582 CIRQ_CFG_3, 583 BEST_EFFORT_SINGLE_QUEUE, 584 BEST_EFFORT_8_QUEUES, 585 }; 586 587 /* IPsec Algo Group */ 588 enum ipsec_algo_group_info { 589 IPSEC_DEFAUL_ALGO_GROUP = 0, 590 IPSEC_ALGO_GROUP1, 591 IPSEC_ALGO_GROUP_DELIMITER 592 }; 593 594 int get_congestion_management_profile(struct adf_accel_dev *accel_dev, 595 u8 *profile); 596 int c4xxx_init_congestion_management(struct adf_accel_dev *accel_dev); 597 int c4xxx_init_debugfs_inline_dir(struct adf_accel_dev *accel_dev); 598 void c4xxx_exit_debugfs_inline_dir(struct adf_accel_dev *accel_dev); 599 #endif /* ADF_C4XXX_INLINE_H_ */
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