adf_dh895xcc_hw_data.c

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    1 /* SPDX-License-Identifier: BSD-3-Clause */
    2 /* Copyright(c) 2007-2022 Intel Corporation */
    3 /* $FreeBSD$ */
    4 #include "qat_freebsd.h"
    5 #include "adf_cfg.h"
    6 #include <adf_accel_devices.h>
    7 #include <adf_pf2vf_msg.h>
    8 #include <adf_common_drv.h>
    9 #include <adf_dev_err.h>
   10 #include <adf_gen2_hw_data.h>
   11 #include "adf_dh895xcc_hw_data.h"
   12 #include "icp_qat_hw.h"
   13 #include "adf_heartbeat.h"
   14 
   15 /* Worker thread to service arbiter mappings based on dev SKUs */
   16 static const u32 thrd_to_arb_map_sku4[] =
   17     { 0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666, 0x12222AAA, 0x11222222,
   18       0x12222AAA, 0x11222222, 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
   19 
   20 static const u32 thrd_to_arb_map_sku6[] =
   21     { 0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666, 0x12222AAA, 0x11222222,
   22       0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222 };
   23 
   24 static const u32 thrd_to_arb_map_sku3[] =
   25     { 0x00000888, 0x00000000, 0x00000888, 0x00000000, 0x00000888, 0x00000000,
   26       0x00000888, 0x00000000, 0x00000888, 0x00000000, 0x00000888, 0x00000000 };
   27 
   28 static u32 thrd_to_arb_map_gen[ADF_DH895XCC_MAX_ACCELENGINES] = { 0 };
   29 
   30 static struct adf_hw_device_class dh895xcc_class =
   31     {.name = ADF_DH895XCC_DEVICE_NAME, .type = DEV_DH895XCC, .instances = 0 };
   32 
   33 static u32
   34 get_accel_mask(struct adf_accel_dev *accel_dev)
   35 {
   36         device_t pdev = accel_dev->accel_pci_dev.pci_dev;
   37         u32 fuse;
   38 
   39         fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4);
   40 
   41         return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
   42             ADF_DH895XCC_ACCELERATORS_MASK;
   43 }
   44 
   45 static u32
   46 get_ae_mask(struct adf_accel_dev *accel_dev)
   47 {
   48         device_t pdev = accel_dev->accel_pci_dev.pci_dev;
   49         u32 fuse;
   50 
   51         fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4);
   52 
   53         return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK;
   54 }
   55 
   56 static uint32_t
   57 get_num_accels(struct adf_hw_device_data *self)
   58 {
   59         uint32_t i, ctr = 0;
   60 
   61         if (!self || !self->accel_mask)
   62                 return 0;
   63 
   64         for (i = 0; i < ADF_DH895XCC_MAX_ACCELERATORS; i++) {
   65                 if (self->accel_mask & (1 << i))
   66                         ctr++;
   67         }
   68         return ctr;
   69 }
   70 
   71 static uint32_t
   72 get_num_aes(struct adf_hw_device_data *self)
   73 {
   74         uint32_t i, ctr = 0;
   75 
   76         if (!self || !self->ae_mask)
   77                 return 0;
   78 
   79         for (i = 0; i < ADF_DH895XCC_MAX_ACCELENGINES; i++) {
   80                 if (self->ae_mask & (1 << i))
   81                         ctr++;
   82         }
   83         return ctr;
   84 }
   85 
   86 static uint32_t
   87 get_misc_bar_id(struct adf_hw_device_data *self)
   88 {
   89         return ADF_DH895XCC_PMISC_BAR;
   90 }
   91 
   92 static uint32_t
   93 get_etr_bar_id(struct adf_hw_device_data *self)
   94 {
   95         return ADF_DH895XCC_ETR_BAR;
   96 }
   97 
   98 static uint32_t
   99 get_sram_bar_id(struct adf_hw_device_data *self)
  100 {
  101         return ADF_DH895XCC_SRAM_BAR;
  102 }
  103 
  104 static enum dev_sku_info
  105 get_sku(struct adf_hw_device_data *self)
  106 {
  107         int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK) >>
  108             ADF_DH895XCC_FUSECTL_SKU_SHIFT;
  109 
  110         switch (sku) {
  111         case ADF_DH895XCC_FUSECTL_SKU_1:
  112                 return DEV_SKU_1;
  113         case ADF_DH895XCC_FUSECTL_SKU_2:
  114                 return DEV_SKU_2;
  115         case ADF_DH895XCC_FUSECTL_SKU_3:
  116                 return DEV_SKU_3;
  117         case ADF_DH895XCC_FUSECTL_SKU_4:
  118                 return DEV_SKU_4;
  119         default:
  120                 return DEV_SKU_UNKNOWN;
  121         }
  122         return DEV_SKU_UNKNOWN;
  123 }
  124 
  125 static void
  126 adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
  127                         u32 const **arb_map_config)
  128 {
  129         switch (accel_dev->accel_pci_dev.sku) {
  130         case DEV_SKU_1:
  131                 adf_cfg_gen_dispatch_arbiter(accel_dev,
  132                                              thrd_to_arb_map_sku4,
  133                                              thrd_to_arb_map_gen,
  134                                              ADF_DH895XCC_MAX_ACCELENGINES);
  135                 *arb_map_config = thrd_to_arb_map_gen;
  136                 break;
  137 
  138         case DEV_SKU_2:
  139         case DEV_SKU_4:
  140                 adf_cfg_gen_dispatch_arbiter(accel_dev,
  141                                              thrd_to_arb_map_sku6,
  142                                              thrd_to_arb_map_gen,
  143                                              ADF_DH895XCC_MAX_ACCELENGINES);
  144                 *arb_map_config = thrd_to_arb_map_gen;
  145                 break;
  146 
  147         case DEV_SKU_3:
  148                 adf_cfg_gen_dispatch_arbiter(accel_dev,
  149                                              thrd_to_arb_map_sku3,
  150                                              thrd_to_arb_map_gen,
  151                                              ADF_DH895XCC_MAX_ACCELENGINES);
  152                 *arb_map_config = thrd_to_arb_map_gen;
  153                 break;
  154 
  155         default:
  156                 device_printf(GET_DEV(accel_dev),
  157                               "The configuration doesn't match any SKU");
  158                 *arb_map_config = NULL;
  159         }
  160 }
  161 
  162 static uint32_t
  163 get_pf2vf_offset(uint32_t i)
  164 {
  165         return ADF_DH895XCC_PF2VF_OFFSET(i);
  166 }
  167 
  168 static uint32_t
  169 get_vintmsk_offset(uint32_t i)
  170 {
  171         return ADF_DH895XCC_VINTMSK_OFFSET(i);
  172 }
  173 
  174 static void
  175 get_arb_info(struct arb_info *arb_csrs_info)
  176 {
  177         arb_csrs_info->arbiter_offset = ADF_DH895XCC_ARB_OFFSET;
  178         arb_csrs_info->wrk_thd_2_srv_arb_map =
  179             ADF_DH895XCC_ARB_WRK_2_SER_MAP_OFFSET;
  180         arb_csrs_info->wrk_cfg_offset = ADF_DH895XCC_ARB_WQCFG_OFFSET;
  181 }
  182 
  183 static void
  184 get_admin_info(struct admin_info *admin_csrs_info)
  185 {
  186         admin_csrs_info->mailbox_offset = ADF_DH895XCC_MAILBOX_BASE_OFFSET;
  187         admin_csrs_info->admin_msg_ur = ADF_DH895XCC_ADMINMSGUR_OFFSET;
  188         admin_csrs_info->admin_msg_lr = ADF_DH895XCC_ADMINMSGLR_OFFSET;
  189 }
  190 
  191 static void
  192 get_errsou_offset(u32 *errsou3, u32 *errsou5)
  193 {
  194         *errsou3 = ADF_DH895XCC_ERRSOU3;
  195         *errsou5 = ADF_DH895XCC_ERRSOU5;
  196 }
  197 
  198 static u32
  199 get_clock_speed(struct adf_hw_device_data *self)
  200 {
  201         /* CPP clock is half high-speed clock */
  202         return self->clock_frequency / 2;
  203 }
  204 
  205 static void
  206 adf_enable_error_correction(struct adf_accel_dev *accel_dev)
  207 {
  208         struct adf_hw_device_data *hw_device = accel_dev->hw_device;
  209         struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
  210         struct resource *csr = misc_bar->virt_addr;
  211         unsigned int val, i;
  212         unsigned int mask;
  213 
  214         /* Enable Accel Engine error detection & correction */
  215         mask = hw_device->ae_mask;
  216         for (i = 0; mask; i++, mask >>= 1) {
  217                 if (!(mask & 1))
  218                         continue;
  219                 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
  220                 val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
  221                 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
  222                 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
  223                 val |= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR;
  224                 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
  225         }
  226 
  227         /* Enable shared memory error detection & correction */
  228         mask = hw_device->accel_mask;
  229         for (i = 0; mask; i++, mask >>= 1) {
  230                 if (!(mask & 1))
  231                         continue;
  232                 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
  233                 val |= ADF_DH895XCC_ERRSSMSH_EN;
  234                 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
  235                 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
  236                 val |= ADF_DH895XCC_ERRSSMSH_EN;
  237                 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
  238         }
  239 }
  240 
  241 static void
  242 adf_enable_ints(struct adf_accel_dev *accel_dev)
  243 {
  244         struct resource *addr;
  245 
  246         addr = (&GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR])->virt_addr;
  247 
  248         /* Enable bundle and misc interrupts */
  249         ADF_CSR_WR(addr,
  250                    ADF_DH895XCC_SMIAPF0_MASK_OFFSET,
  251                    accel_dev->u1.pf.vf_info ?
  252                        0 :
  253                        (1ULL << GET_MAX_BANKS(accel_dev)) - 1);
  254         ADF_CSR_WR(addr,
  255                    ADF_DH895XCC_SMIAPF1_MASK_OFFSET,
  256                    ADF_DH895XCC_SMIA1_MASK);
  257 }
  258 
  259 static u32
  260 get_ae_clock(struct adf_hw_device_data *self)
  261 {
  262         /*
  263          * Clock update interval is <16> ticks for dh895xcc.
  264          */
  265         return self->clock_frequency / 16;
  266 }
  267 
  268 static int
  269 get_storage_enabled(struct adf_accel_dev *accel_dev, u32 *storage_enabled)
  270 {
  271         char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
  272         char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
  273 
  274         strlcpy(key, ADF_STORAGE_FIRMWARE_ENABLED, sizeof(key));
  275         if (!adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC, key, val)) {
  276                 if (kstrtouint(val, 0, storage_enabled))
  277                         return -EFAULT;
  278         }
  279         return 0;
  280 }
  281 
  282 static u32
  283 dh895xcc_get_hw_cap(struct adf_accel_dev *accel_dev)
  284 {
  285         device_t pdev = accel_dev->accel_pci_dev.pci_dev;
  286         u32 legfuses;
  287         u32 capabilities;
  288 
  289         /* Read accelerator capabilities mask */
  290         legfuses = pci_read_config(pdev, ADF_DEVICE_LEGFUSE_OFFSET, 4);
  291         capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC +
  292             ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC +
  293             ICP_ACCEL_CAPABILITIES_CIPHER +
  294             ICP_ACCEL_CAPABILITIES_AUTHENTICATION +
  295             ICP_ACCEL_CAPABILITIES_COMPRESSION + ICP_ACCEL_CAPABILITIES_RAND +
  296             ICP_ACCEL_CAPABILITIES_HKDF + ICP_ACCEL_CAPABILITIES_ECEDMONT +
  297             ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN;
  298 
  299         if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE)
  300                 capabilities &= ~(ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
  301                                   ICP_ACCEL_CAPABILITIES_CIPHER |
  302                                   ICP_ACCEL_CAPABILITIES_HKDF |
  303                                   ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN);
  304         if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE)
  305                 capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
  306         if (legfuses & ICP_ACCEL_MASK_PKE_SLICE)
  307                 capabilities &= ~(ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
  308                                   ICP_ACCEL_CAPABILITIES_ECEDMONT);
  309         if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
  310                 capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
  311 
  312         return capabilities;
  313 }
  314 
  315 static const char *
  316 get_obj_name(struct adf_accel_dev *accel_dev,
  317              enum adf_accel_unit_services service)
  318 {
  319         return ADF_DH895XCC_AE_FW_NAME_CUSTOM1;
  320 }
  321 
  322 static u32
  323 get_objs_num(struct adf_accel_dev *accel_dev)
  324 {
  325         return 1;
  326 }
  327 
  328 static u32
  329 get_obj_cfg_ae_mask(struct adf_accel_dev *accel_dev,
  330                     enum adf_accel_unit_services services)
  331 {
  332         return accel_dev->hw_device->ae_mask;
  333 }
  334 
  335 void
  336 adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
  337 {
  338         hw_data->dev_class = &dh895xcc_class;
  339         hw_data->instance_id = dh895xcc_class.instances++;
  340         hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
  341         hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
  342         hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
  343         hw_data->num_logical_accel = 1;
  344         hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
  345         hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET;
  346         hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK;
  347         hw_data->alloc_irq = adf_isr_resource_alloc;
  348         hw_data->free_irq = adf_isr_resource_free;
  349         hw_data->enable_error_correction = adf_enable_error_correction;
  350         hw_data->print_err_registers = adf_print_err_registers;
  351         hw_data->get_accel_mask = get_accel_mask;
  352         hw_data->get_ae_mask = get_ae_mask;
  353         hw_data->get_num_accels = get_num_accels;
  354         hw_data->get_num_aes = get_num_aes;
  355         hw_data->get_etr_bar_id = get_etr_bar_id;
  356         hw_data->get_misc_bar_id = get_misc_bar_id;
  357         hw_data->get_pf2vf_offset = get_pf2vf_offset;
  358         hw_data->get_vintmsk_offset = get_vintmsk_offset;
  359         hw_data->get_arb_info = get_arb_info;
  360         hw_data->get_admin_info = get_admin_info;
  361         hw_data->get_errsou_offset = get_errsou_offset;
  362         hw_data->get_clock_speed = get_clock_speed;
  363         hw_data->get_sram_bar_id = get_sram_bar_id;
  364         hw_data->get_sku = get_sku;
  365         hw_data->heartbeat_ctr_num = ADF_NUM_HB_CNT_PER_AE;
  366         hw_data->fw_name = ADF_DH895XCC_FW;
  367         hw_data->fw_mmp_name = ADF_DH895XCC_MMP;
  368         hw_data->init_admin_comms = adf_init_admin_comms;
  369         hw_data->exit_admin_comms = adf_exit_admin_comms;
  370         hw_data->disable_iov = adf_disable_sriov;
  371         hw_data->send_admin_init = adf_send_admin_init;
  372         hw_data->init_arb = adf_init_gen2_arb;
  373         hw_data->exit_arb = adf_exit_arb;
  374         hw_data->get_arb_mapping = adf_get_arbiter_mapping;
  375         hw_data->enable_ints = adf_enable_ints;
  376         hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
  377         hw_data->disable_vf2pf_comms = adf_pf_disable_vf2pf_comms;
  378         hw_data->reset_device = adf_reset_sbr;
  379         hw_data->restore_device = adf_dev_restore;
  380         hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
  381         hw_data->get_accel_cap = dh895xcc_get_hw_cap;
  382         hw_data->get_heartbeat_status = adf_get_heartbeat_status;
  383         hw_data->get_ae_clock = get_ae_clock;
  384         hw_data->get_objs_num = get_objs_num;
  385         hw_data->get_obj_name = get_obj_name;
  386         hw_data->get_obj_cfg_ae_mask = get_obj_cfg_ae_mask;
  387         hw_data->clock_frequency = ADF_DH895XCC_AE_FREQ;
  388         hw_data->extended_dc_capabilities = 0;
  389         hw_data->get_storage_enabled = get_storage_enabled;
  390         hw_data->query_storage_cap = 1;
  391         hw_data->get_heartbeat_status = adf_get_heartbeat_status;
  392         hw_data->get_ae_clock = get_ae_clock;
  393         hw_data->storage_enable = 0;
  394         hw_data->get_fw_image_type = adf_cfg_get_fw_image_type;
  395         hw_data->config_device = adf_config_device;
  396         hw_data->get_ring_to_svc_map = adf_cfg_get_services_enabled;
  397         hw_data->set_asym_rings_mask = adf_cfg_set_asym_rings_mask;
  398         hw_data->ring_to_svc_map = ADF_DEFAULT_RING_TO_SRV_MAP;
  399         hw_data->pre_reset = adf_dev_pre_reset;
  400         hw_data->post_reset = adf_dev_post_reset;
  401 
  402         adf_gen2_init_hw_csr_info(&hw_data->csr_info);
  403 }
  404 
  405 void
  406 adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
  407 {
  408         hw_data->dev_class->instances--;
  409 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
