FreeBSD/Linux Kernel Cross Reference
sys/dev/qbus/dz_uba.c
1 /* $NetBSD: dz_uba.c,v 1.20 2003/12/13 23:02:33 ad Exp $ */
2 /*
3 * Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved.
4 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed at Ludd, University of
17 * Lule}, Sweden and its contributors.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: dz_uba.c,v 1.20 2003/12/13 23:02:33 ad Exp $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/ioctl.h>
39 #include <sys/tty.h>
40 #include <sys/proc.h>
41 #include <sys/buf.h>
42 #include <sys/conf.h>
43 #include <sys/file.h>
44 #include <sys/uio.h>
45 #include <sys/kernel.h>
46 #include <sys/syslog.h>
47 #include <sys/device.h>
48
49 #include <machine/bus.h>
50 #include <machine/pte.h>
51 #include <machine/trap.h>
52 #include <machine/scb.h>
53
54 #include <dev/qbus/ubavar.h>
55
56 #include <dev/dec/dzreg.h>
57 #include <dev/dec/dzvar.h>
58
59 #include "ioconf.h"
60
61 static int dz_uba_match __P((struct device *, struct cfdata *, void *));
62 static void dz_uba_attach __P((struct device *, struct device *, void *));
63
64 CFATTACH_DECL(dz_uba, sizeof(struct dz_softc),
65 dz_uba_match, dz_uba_attach, NULL, NULL);
66
67 /* Autoconfig handles: setup the controller to interrupt, */
68 /* then complete the housecleaning for full operation */
69
70 static int
71 dz_uba_match(parent, cf, aux)
72 struct device *parent;
73 struct cfdata *cf;
74 void *aux;
75 {
76 struct uba_attach_args *ua = aux;
77 bus_space_tag_t iot = ua->ua_iot;
78 bus_space_handle_t ioh = ua->ua_ioh;
79 int n;
80
81 iot = iot; /* Silly GCC */
82 /* Reset controller to initialize, enable TX interrupts */
83 /* to catch floating vector info elsewhere when completed */
84
85 bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_MSE | DZ_CSR_TXIE);
86 bus_space_write_1(iot, ioh, DZ_UBA_TCR, 1);
87
88 DELAY(100000); /* delay 1/10 second */
89
90 bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_RESET);
91
92 /* Now wait up to 3 seconds for reset/clear to complete. */
93
94 for (n = 0; n < 300; n++) {
95 DELAY(10000);
96 if ((bus_space_read_2(iot, ioh, DZ_UBA_CSR)&DZ_CSR_RESET) == 0)
97 break;
98 }
99
100 /* If the RESET did not clear after 3 seconds, */
101 /* the controller must be broken. */
102
103 if (n >= 300)
104 return (0);
105
106 /* Register the TX interrupt handler */
107
108
109 return (1);
110 }
111
112 static void
113 dz_uba_attach(parent, self, aux)
114 struct device *parent, *self;
115 void *aux;
116 {
117 struct dz_softc *sc = (void *)self;
118 struct uba_attach_args *ua = aux;
119
120 sc->sc_iot = ua->ua_iot;
121 sc->sc_ioh = ua->ua_ioh;
122
123 sc->sc_dr.dr_csr = DZ_UBA_CSR;
124 sc->sc_dr.dr_rbuf = DZ_UBA_RBUF;
125 sc->sc_dr.dr_dtr = DZ_UBA_DTR;
126 sc->sc_dr.dr_break = DZ_UBA_BREAK;
127 sc->sc_dr.dr_tbuf = DZ_UBA_TBUF;
128 sc->sc_dr.dr_tcr = DZ_UBA_TCR;
129 sc->sc_dr.dr_dcd = DZ_UBA_DCD;
130 sc->sc_dr.dr_ring = DZ_UBA_RING;
131
132 sc->sc_dr.dr_firstreg = DZ_UBA_FIRSTREG;
133 sc->sc_dr.dr_winsize = DZ_UBA_WINSIZE;
134
135 sc->sc_type = DZ_DZ;
136
137 /* Now register the TX & RX interrupt handlers */
138 uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
139 dzxint, sc, &sc->sc_tintrcnt);
140 uba_intr_establish(ua->ua_icookie, ua->ua_cvec - 4,
141 dzrint, sc, &sc->sc_rintrcnt);
142 uba_reset_establish(dzreset, self);
143
144 dzattach(sc, ua->ua_evcnt, -1);
145 }
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