The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/qbus/qdreg.h

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    1 /*      $NetBSD: qdreg.h,v 1.6 2003/08/07 16:31:16 agc Exp $    */
    2 /*-
    3  * Copyright (c) 1982, 1986 The Regents of the University of California.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. Neither the name of the University nor the names of its contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  *      @(#)qdreg.h     7.1 (Berkeley) 5/9/91
   31  */
   32 
   33 /************************************************************************
   34  *                                                                      *
   35  *                      Copyright (c) 1985, 1986 by                     *
   36  *              Digital Equipment Corporation, Maynard, MA              *
   37  *                      All rights reserved.                            *
   38  *                                                                      *
   39  *   This software is furnished under a license and may be used and     *
   40  *   copied  only  in accordance with the terms of such license and     *
   41  *   with the  inclusion  of  the  above  copyright  notice.   This     *
   42  *   software  or  any  other copies thereof may not be provided or     *
   43  *   otherwise made available to any other person.  No title to and     *
   44  *   ownership of the software is hereby transferred.                   *
   45  *                                                                      *
   46  *   The information in this software is subject to change  without     *
   47  *   notice  and should not be construed as a commitment by Digital     *
   48  *   Equipment Corporation.                                             *
   49  *                                                                      *
   50  *   Digital assumes no responsibility for the use  or  reliability     *
   51  *   of its software on equipment which is not supplied by Digital.     *
   52  *                                                                      *
   53  ************************************************************************/
   54 
   55 /* Dragon ADDER reg map */
   56 /* ADDER register bit definitions */
   57 /* Y_SCROLL_CONSTANT */
   58 
   59 #define SCROLL_ERASE            0x2000
   60 #define ADDER_SCROLL_DOWN       0x1000
   61 
   62 /* ADDER status and interrupt enable registers [1], [2], [3] */
   63 
   64 #define DISABLE                 0x0000
   65 #define PAUSE_COMPLETE          0x0001
   66 #define FRAME_SYNC              0x0002
   67 #define INIT_COMPLETE           0x0004
   68 #define RASTEROP_COMPLETE       0x0008
   69 
   70 #define ADDRESS_COMPLETE        0x0010
   71 #define RX_READY                0x0020
   72 #define TX_READY                0x0040
   73 #define ID_SCROLL_READY         0x0080
   74 
   75 #define TOP_CLIP                0x0100
   76 #define BOTTOM_CLIP             0x0200
   77 #define LEFT_CLIP               0x0400
   78 #define RIGHT_CLIP              0x0800
   79 #define NO_CLIP                 0x1000
   80 #define VSYNC                   0x2000
   81 
   82 /* ADDER command register [8], [10] */
   83 
   84 #define OCR_zero                0x0000
   85 #define Z_BLOCK0                0x0000
   86 #define OCRA                    0x0000
   87 #define OCRB                    0x0004
   88 #define RASTEROP                0x02c0
   89 #define PBT                     0x03c0
   90 #define BTPZ                    0x0bb0
   91 #define PTBZ                    0x07a0
   92 #define DTE                     0x0400
   93 #define S1E                     0x0800
   94 #define S2E                     0x1000
   95 #define VIPER_Z_LOAD            0x01A0
   96 #define ID_LOAD                 0x0100
   97 #define CANCEL                  0x0000
   98 #define LF_R1                   0x0000
   99 #define LF_R2                   0x0010
  100 #define LF_R3                   0x0020
  101 #define LF_R4                   0x0030
  102 
  103 /* ADDER rasterop mode register [9] */
  104 
  105 #define NORMAL                  0x0000
  106 #define LINEAR_PATTERN          0x0002
  107 #define X_FILL                  0x0003
  108 #define Y_FILL                  0x0007
  109 #define BASELINE                0x0008
  110 #define HOLE_ENABLE             0x0010
  111 #define SRC_1_INDEX_ENABLE      0x0020
  112 #define DST_INDEX_ENABLE        0x0040
  113 #define DST_WRITE_ENABLE        0x0080
  114 
  115 /* ADDER source 2 size register */
  116 
  117 #define NO_TILE                 0x0080
  118 
  119 /* External registers base addresses */
  120 
  121 #define CS_UPDATE_MASK          0x0060
  122 #define CS_SCROLL_MASK          0x0040
  123 
  124 /* VIPER registers */
  125 
  126 #define RESOLUTION_MODE         0x0080
  127 #define MEMORY_BUS_WIDTH        0x0081
  128 #define PLANE_ADDRESS           0x0083
  129 #define LU_FUNCTION_R1          0x0084
  130 #define LU_FUNCTION_R2          0x0085
  131 #define LU_FUNCTION_R3          0x0086
  132 #define LU_FUNCTION_R4          0x0087
  133 #define MASK_1                  0x0088
  134 #define MASK_2                  0x0089
  135 #define SOURCE                  0x008a
  136 #define SOURCE_Z                0x0000
  137 #define BACKGROUND_COLOR        0x008e
  138 #define BACKGROUND_COLOR_Z      0x000C
  139 #define FOREGROUND_COLOR        0x008f
  140 #define FOREGROUND_COLOR_Z      0x0004
  141 #define SRC1_OCR_A              0x0090
  142 #define SRC2_OCR_A              0x0091
  143 #define DST_OCR_A               0x0092
  144 #define SRC1_OCR_B              0x0094
  145 #define SRC2_OCR_B              0x0095
  146 #define DST_OCR_B               0x0096
  147 
  148 /* VIPER scroll registers */
  149 
  150 #define SCROLL_CONSTANT         0x0082
  151 #define SCROLL_FILL             0x008b
  152 #define SCROLL_FILL_Z           0x0008
  153 #define LEFT_SCROLL_MASK        0x008c
  154 #define RIGHT_SCROLL_MASK       0x008d
  155 
  156 /* VIPER register bit definitions */
  157 
  158 #define EXT_NONE                0x0000
  159 #define EXT_SOURCE              0x0001
  160 #define EXT_M1_M2               0x0002
  161 #define INT_NONE                0x0000
  162 #define INT_SOURCE              0x0004
  163 #define INT_M1_M2               0x0008
  164 #define ID                      0x0010
  165 #define NO_ID                   0x0000
  166 #define WAIT                    0x0020
  167 #define NO_WAIT                 0x0000
  168 #define BAR_SHIFT_DELAY         WAIT
  169 #define NO_BAR_SHIFT_DELAY      NO_WAIT
  170 
  171 
  172 /* VIPER logical function unit codes */
  173 
  174 #define LF_ZEROS                0x0000
  175 #define LF_D_XOR_S              0x0006
  176 #define LF_SOURCE               0x000A
  177 #define LF_D_OR_S               0x000E
  178 #define LF_ONES                 0x000F
  179 #define INV_M1_M2               0x0030
  180 #define FULL_SRC_RESOLUTION     0X00C0 /* makes second pass like first pass */
  181 
  182 /* VIPER scroll register [2] */
  183 
  184 #define SCROLL_DISABLE          0x0040
  185 #define SCROLL_ENABLE           0x0020
  186 #define VIPER_LEFT              0x0000
  187 #define VIPER_RIGHT             0x0010
  188 #define VIPER_UP                0x0040
  189 #define VIPER_DOWN              0x0000
  190 
  191 /* Adder scroll register */
  192 
  193 #define ADDER_UP                0x0000
  194 #define ADDER_DOWN              0x1000
  195 
  196 /* Misc scroll definitions */
  197 
  198 #define UP              0
  199 #define DOWN            1
  200 #define LEFT            2
  201 #define RIGHT           3
  202 #define NODIR           4
  203 #define SCROLL_VMAX     31
  204 #define SCROLL_HMAX     15
  205 #define NEW             2
  206 #define OLD             1
  207 #define BUSY            1
  208 #define DRAG            1
  209 #define SCROLL          0
  210 
  211 /* miscellaneous defines */
  212 
  213 #define ALL_PLANES      0xffffffff
  214 #define UNITY           0x1fff           /* Adder scale factor */
  215 #define MAX_SCREEN_X    1024
  216 #define MAX_SCREEN_Y    864
  217 #define FONT_HEIGHT     32
  218 
  219         struct adder {
  220 
  221             /* adder control registers */
  222 
  223             u_short register_address;   /* ADDER reg pntr for use by DGA */
  224             u_short request_enable;     /* DMA request enables */
  225             u_short interrupt_enable;   /* interrupt enables */
  226             u_short status;             /* ADDER status bits */
  227             u_short reserved1;          /* test function only */
  228             u_short spare1;             /* spare address (what else?) */
  229 
  230             u_short reserved2;          /* test function only */
  231             u_short id_data;            /* data path to I/D bus */
  232             u_short command;            /* ADDER chip command register */
  233             u_short rasterop_mode;      /* sets rasterop execution modes */
  234             u_short cmd;                /* duplicate path to above cmd reg */
  235             u_short reserved3;          /* test function only */
  236 
  237             /* scroll registers */
  238 
  239             u_short ID_scroll_data;     /* I/D bus scroll data */
  240             u_short ID_scroll_command;  /* I/D bus scroll command */
  241             u_short scroll_x_min;       /* X scroll min - left boundary */
  242             u_short scroll_x_max;       /* X scroll max - right boundary */
  243             u_short scroll_y_min;       /* Y scroll min - upper boundary */
  244             u_short scroll_y_max;       /* Y scroll max - lower boundary */
  245             u_short pause;              /* Y coord to set stat when scanned */
  246             u_short y_offset_pending;   /* vertical scroll control */
  247             u_short y_scroll_constant;
  248 
  249             /* update control registers */
  250 
  251             u_short x_index_pending;    /* x pending index */
  252             u_short y_index_pending;    /* y pending index */
  253             u_short x_index_new;        /* new x index */
  254             u_short y_index_new;                /* new y index */
  255             u_short x_index_old;                /* old x index */
  256             u_short y_index_old;                /* old y index */
  257             u_short x_clip_min;         /* left clipping boundary */
  258             u_short x_clip_max;         /* right clipping boundary */
  259             u_short y_clip_min;         /* upper clipping boundary */
  260             u_short y_clip_max;         /* lower clipping boundary */
  261             u_short spare2;             /* spare address (another!) */
  262 
  263             /* rasterop control registers */
  264 
  265             u_short source_1_dx;        /* source #1 x vector */
  266             u_short source_1_dy;        /* source #1 y vector*/
  267             u_short source_1_x;         /* source #1 x origin */
  268             u_short source_1_y;         /* source #1 y origin */
  269             u_short destination_x;      /* destination x origin */
  270             u_short destination_y;      /* destination y origin */
  271             u_short fast_dest_dx;       /* destination x fast vector */
  272             u_short fast_dest_dy;       /* destination y fast vector */
  273             u_short slow_dest_dx;       /* destination x slow vector */
  274             u_short slow_dest_dy;       /* destination y slow vector */
  275             u_short fast_scale;         /* scale factor for fast vector */
  276             u_short slow_scale;         /* scale factor for slow vector */
  277             u_short source_2_x;         /* source #2 x origin */
  278             u_short source_2_y;         /* source #2 y origin */
  279             u_short source_2_size;      /* source #2 height & width */
  280             u_short error_1;            /* error regs (?) */
  281             u_short error_2;
  282 
  283             /* screen format control registers */
  284 
  285             u_short y_scan_count_0;     /* y scan counts for vert timing */
  286             u_short y_scan_count_1;
  287             u_short y_scan_count_2;
  288             u_short y_scan_count_3;
  289             u_short x_scan_conf;        /* x scan configuration */
  290             u_short x_limit;
  291             u_short y_limit;
  292             u_short x_scan_count_0;     /* x scan count for horiz timing */
  293             u_short x_scan_count_1;
  294             u_short x_scan_count_2;
  295             u_short x_scan_count_3;
  296             u_short x_scan_count_4;
  297             u_short x_scan_count_5;
  298             u_short x_scan_count_6;
  299             u_short sync_phase_adj;     /* sync phase (horiz sync count) */
  300         };
  301 
  302 /*---------------------
  303 * DUART definitions */
  304 
  305         /* command definitions */
  306 
  307 #define EN_RCV          0x01
  308 #define DIS_RCV         0x02
  309 #define EN_XMT          0x04
  310 #define DIS_XMT         0x08
  311 #define RESET_M         0x10
  312 #define RESET_RCV       0x20
  313 #define RESET_XMT       0x30
  314 #define RESET_ERR       0x40
  315 #define RESET_BD        0x50
  316 #define START_BREAK     0x60
  317 #define STOP_BREAK      0x70
  318 
  319         /* interrupt bit definitions */
  320 
  321 #define EI_XMT_A        0x01
  322 #define EI_RCV_A        0x02
  323 #define EI_XMT_B        0x10
  324 #define EI_RCV_B        0x20
  325 
  326 #define XMT_RDY_A       0x01
  327 #define RCV_RDY_A       0x02
  328 #define XMT_RDY_B       0x10
  329 #define RCV_RDY_B       0x20
  330 
  331         /* status register bit definitions */
  332 
  333 #define RCV_RDY         0x01
  334 #define FIFO_FULL       0x02
  335 #define XMT_RDY         0x04
  336 #define XMT_EMT         0x08
  337 #define OVER_ERR        0x10
  338 #define ERR_PARITY      0x20
  339 #define FRAME_ERR       0x40
  340 #define RCVD_BREAK      0x80
  341 
  342 
  343         struct duart {
  344 
  345             /* channel A - LK201 */
  346 
  347             short modeA;                /* ch.A mode reg (read/write) */
  348             short statusA;              /* ch.A status reg (read) */
  349 #define clkselA statusA                 /* ch.A clock slect reg (write) */
  350             short cmdA;                 /* ch.A command reg (write) */
  351             short dataA;                /* rcv/xmt data ch.A (read/write) */
  352             short inchng;               /* input change state reg (read) */
  353 #define auxctl inchng                   /* auxiliary control reg (write) */
  354             short istatus;              /* interrupt status reg (read) */
  355 #define imask istatus                   /* interrupt mask reg (write) */
  356             short CThi;                 /* counter/timer hi byte (read) */
  357 #define CTRhi CThi                      /* counter/timer hi reg (write) */
  358             short CTlo;                 /* counter/timer lo byte (read) */
  359 #define CTRlo CTlo                      /* counter/timer lo reg (write) */
  360 
  361             /* channel B - pointing device */
  362 
  363             short modeB;                /* ch.B mode reg (read/write) */
  364             short statusB;              /* ch.B status reg (read) */
  365 #define clkselB statusB                 /* ch.B clock select reg (write) */
  366             short cmdB;                 /* ch.B command reg (write) */
  367             short dataB;                /* ch.B rcv/xmt data (read/write) */
  368             short rsrvd;
  369             short inport;               /* input port (read) */
  370 #define outconf inport                  /* output port config reg (write) */
  371             short strctr;               /* start counter command (read) */
  372 #define setbits setctr                  /* output bits set command (write) */
  373             short stpctr;               /* stop counter command (read) */
  374 #define resetbits stpctr                /* output bits reset cmd (write) */
  375 
  376 };

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