1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #ifndef __QCOM_CLK_RCG2_REG_H__
31 #define __QCOM_CLK_RCG2_REG_H__
32
33 #define QCOM_CLK_RCG2_CMD_REG 0x0
34 #define QCOM_CLK_RCG2_CMD_UPDATE (1U << 0)
35 #define QCOM_CLK_RCG2_CMD_ROOT_EN (1U << 1)
36 #define QCOM_CLK_RCG2_CMD_DIRTY_CFG (1U << 4)
37 #define QCOM_CLK_RCG2_CMD_DIRTY_N (1U << 5)
38 #define QCOM_CLK_RCG2_CMD_DIRTY_M (1U << 6)
39 #define QCOM_CLK_RCG2_CMD_DIRTY_D (1U << 7)
40 #define QCOM_CLK_RCG2_CMD_ROOT_OFF (1U << 31)
41
42 #define QCOM_CLK_RCG2_CFG_REG 0x4
43 #define QCOM_CLK_RCG2_CFG_SRC_DIV_SHIFT 0
44 #define QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT 8
45 #define QCOM_CLK_RCG2_CFG_SRC_SEL_MASK \
46 (0x7 << QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT)
47 #define QCOM_CLK_RCG2_CFG_MODE_SHIFT 12
48 #define QCOM_CLK_RCG2_CFG_MODE_MASK \
49 (0x3 << QCOM_CLK_RCG2_CFG_MODE_SHIFT)
50 #define QCOM_CLK_RCG2_CFG_MODE_DUAL_EDGE \
51 (0x2 << QCOM_CLK_RCG2_CFG_MODE_SHIFT)
52 #define QCOM_CLK_RCG2_CFG_HW_CLK_CTRL_MASK (1U << 20)
53
54 #define QCOM_CLK_RCG2_M_REG 0x8
55 #define QCOM_CLK_RCG2_N_REG 0xc
56 #define QCOM_CLK_RCG2_D_REG 0x10
57
58 #endif /* __QCOM_CLK_RCG2_REG_H__ */
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