FreeBSD/Linux Kernel Cross Reference
sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

     /*-
      * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
      *
      * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
      *
      * Redistribution and use in source and binary forms, with or without
      * modification, are permitted provided that the following conditions
      * are met:
      * 1. Redistributions of source code must retain the above copyright
     *    notice unmodified, this list of conditions, and the following
     *    disclaimer.
     * 2. Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    /* Driver for Qualcomm IPQ4018 clock and reset device */
    
    #include <sys/cdefs.h>
    __FBSDID("$FreeBSD$");
    
    #include <sys/param.h>
    #include <sys/kernel.h>
    #include <sys/malloc.h>
    #include <sys/module.h>
    #include <sys/sglist.h>
    #include <sys/random.h>
    #include <sys/stdatomic.h>
    #include <sys/mutex.h>
    
    #include <machine/bus.h>
    #include <machine/resource.h>
    #include <sys/bus.h>
    
    #include <dev/fdt/fdt_common.h>
    #include <dev/ofw/ofw_bus.h>
    #include <dev/ofw/ofw_bus_subr.h>
    
    #include <dev/extres/hwreset/hwreset.h>
    
    #include "hwreset_if.h"
    
    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
    
    #include "qcom_gcc_ipq4018_var.h"
    
    
    static const struct qcom_gcc_ipq4018_reset_entry gcc_ipq4019_reset_list[] = {
            [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
            [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
            [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
            [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
            [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
            [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
            [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
            [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
            [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
            [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
            [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
            [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
            [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
            [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
            [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
            [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
            [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
            [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
            [PCIE_AHB_ARES] = { 0x1d010, 10 },
            [PCIE_PWR_ARES] = { 0x1d010, 9 },
            [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
            [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
            [PCIE_PHY_ARES] = { 0x1d010, 6 },
            [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
            [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
            [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
            [PCIE_PIPE_ARES] = { 0x1d010, 2 },
            [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
            [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
            [ESS_RESET] = { 0x12008, 0},
            [GCC_BLSP1_BCR] = {0x01000, 0},
            [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
            [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
            [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
            [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
            [GCC_BIMC_BCR] = {0x04000, 0},
            [GCC_TLMM_BCR] = {0x05000, 0},
            [GCC_IMEM_BCR] = {0x0E000, 0},
            [GCC_ESS_BCR] = {0x12008, 0},
            [GCC_PRNG_BCR] = {0x13000, 0},
           [GCC_BOOT_ROM_BCR] = {0x13008, 0},
           [GCC_CRYPTO_BCR] = {0x16000, 0},
           [GCC_SDCC1_BCR] = {0x18000, 0},
           [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
           [GCC_AUDIO_BCR] = {0x1B008, 0},
           [GCC_QPIC_BCR] = {0x1C000, 0},
           [GCC_PCIE_BCR] = {0x1D000, 0},
           [GCC_USB2_BCR] = {0x1E008, 0},
           [GCC_USB2_PHY_BCR] = {0x1E018, 0},
           [GCC_USB3_BCR] = {0x1E024, 0},
           [GCC_USB3_PHY_BCR] = {0x1E034, 0},
           [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
           [GCC_PCNOC_BCR] = {0x2102C, 0},
           [GCC_DCD_BCR] = {0x21038, 0},
           [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
           [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
           [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
           [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
           [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
           [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
           [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
           [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
           [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
           [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
           [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
           [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
           [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
           [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
           [GCC_TCSR_BCR] = {0x22000, 0},
           [GCC_MPM_BCR] = {0x24000, 0},
           [GCC_SPDM_BCR] = {0x25000, 0},
   };
   
   int
   qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id, bool reset)
   {
           struct qcom_gcc_ipq4018_softc *sc;
           uint32_t reg;
   
           sc = device_get_softc(dev);
   
           if (id > nitems(gcc_ipq4019_reset_list)) {
                   device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
                   return (EINVAL);
           }
   
           mtx_lock(&sc->mtx);
           reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
           if (reset)
                   reg |= (1U << gcc_ipq4019_reset_list[id].bit);
           else
                   reg &= ~(1U << gcc_ipq4019_reset_list[id].bit);
           bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg);
           mtx_unlock(&sc->mtx);
           return (0);
   }
   
   int
   qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset)
   {
           struct qcom_gcc_ipq4018_softc *sc;
           uint32_t reg;
   
           sc = device_get_softc(dev);
   
           if (id > nitems(gcc_ipq4019_reset_list)) {
                   device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
                   return (EINVAL);
           }
           mtx_lock(&sc->mtx);
           reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
           if (reg & ((1U << gcc_ipq4019_reset_list[id].bit)))
                   *reset = true;
           else
                   *reset = false;
           mtx_unlock(&sc->mtx);
   
           device_printf(dev, "called; id=%d\n", id);
           return (0);
   }
   

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