1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #ifndef __QCOM_GCC_IPQ4018_VAR_H__
31 #define __QCOM_GCC_IPQ4018_VAR_H__
32
33 struct qcom_gcc_ipq4018_reset_entry {
34 uint32_t reg;
35 uint32_t bit;
36 };
37
38 struct qcom_gcc_ipq4018_softc {
39 device_t dev;
40 int reg_rid;
41 struct resource *reg;
42 struct mtx mtx;
43 struct clkdom *clkdom;
44 };
45
46 /*
47 * reset block
48 */
49 extern int qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id,
50 bool reset);
51 extern int qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id,
52 bool *reset);
53
54 /*
55 * clock block
56 */
57 extern int qcom_gcc_ipq4018_clock_read(device_t dev, bus_addr_t addr,
58 uint32_t *val);
59 extern int qcom_gcc_ipq4018_clock_write(device_t dev, bus_addr_t addr,
60 uint32_t val);
61 extern int qcom_gcc_ipq4018_clock_modify(device_t dev, bus_addr_t addr,
62 uint32_t clear_mask, uint32_t set_mask);
63 extern void qcom_gcc_ipq4018_clock_setup(struct qcom_gcc_ipq4018_softc *sc);
64 extern void qcom_gcc_ipq4018_clock_lock(device_t dev);
65 extern void qcom_gcc_ipq4018_clock_unlock(device_t dev);
66
67 #endif /* __QCOM_GCC_IPQ4018_VAR_H__ */
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