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sys/dev/qlnx/qlnxe/ecore_hsi_roce.h
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1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_ROCE__ 32 #define __ECORE_HSI_ROCE__ 33 /************************************************************************/ 34 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 35 /************************************************************************/ 36 #include "ecore_hsi_rdma.h" 37 /************************************************************************/ 38 /* Add include to common roce target for both eCore and protocol roce driver */ 39 /************************************************************************/ 40 #include "roce_common.h" 41 42 /* 43 * The roce storm context of Ystorm 44 */ 45 struct ystorm_roce_conn_st_ctx 46 { 47 struct regpair temp[2]; 48 }; 49 50 /* 51 * The roce storm context of Mstorm 52 */ 53 struct pstorm_roce_conn_st_ctx 54 { 55 struct regpair temp[16]; 56 }; 57 58 /* 59 * The roce storm context of Xstorm 60 */ 61 struct xstorm_roce_conn_st_ctx 62 { 63 struct regpair temp[24]; 64 }; 65 66 /* 67 * The roce storm context of Tstorm 68 */ 69 struct tstorm_roce_conn_st_ctx 70 { 71 struct regpair temp[30]; 72 }; 73 74 /* 75 * The roce storm context of Mstorm 76 */ 77 struct mstorm_roce_conn_st_ctx 78 { 79 struct regpair temp[6]; 80 }; 81 82 /* 83 * The roce storm context of Ystorm 84 */ 85 struct ustorm_roce_conn_st_ctx 86 { 87 struct regpair temp[12]; 88 }; 89 90 /* 91 * roce connection context 92 */ 93 struct e4_roce_conn_context 94 { 95 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 96 struct regpair ystorm_st_padding[2] /* padding */; 97 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 98 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 99 struct regpair xstorm_st_padding[2] /* padding */; 100 struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 101 struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 102 struct timers_context timer_context /* timer context */; 103 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 104 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 105 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 106 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 107 struct regpair ustorm_st_padding[2] /* padding */; 108 }; 109 110 /* 111 * roce connection context 112 */ 113 struct e5_roce_conn_context 114 { 115 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 116 struct regpair ystorm_st_padding[2] /* padding */; 117 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 118 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 119 struct regpair xstorm_st_padding[2] /* padding */; 120 struct e5_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 121 struct e5_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 122 struct timers_context timer_context /* timer context */; 123 struct e5_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 124 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 125 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 126 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 127 struct regpair ustorm_st_padding[2] /* padding */; 128 }; 129 130 /* 131 * roce create qp requester ramrod data 132 */ 133 struct roce_create_qp_req_ramrod_data 134 { 135 __le16 flags; 136 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 137 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 138 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 139 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 140 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 141 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 142 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 143 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 144 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 145 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 146 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 147 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 148 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 149 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 150 u8 max_ord; 151 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 152 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 153 u8 orq_num_pages; 154 __le16 p_key; 155 __le32 flow_label; 156 __le32 dst_qp_id; 157 __le32 ack_timeout_val; 158 __le32 initial_psn; 159 __le16 mtu; 160 __le16 pd; 161 __le16 sq_num_pages; 162 __le16 low_latency_phy_queue; 163 struct regpair sq_pbl_addr; 164 struct regpair orq_pbl_addr; 165 __le16 local_mac_addr[3] /* BE order */; 166 __le16 remote_mac_addr[3] /* BE order */; 167 __le16 vlan_id; 168 __le16 udp_src_port /* Only relevant in RRoCE */; 169 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 170 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 171 __le32 cq_cid; 172 struct regpair qp_handle_for_cqe; 173 struct regpair qp_handle_for_async; 174 u8 stats_counter_id /* Statistics counter ID to use */; 175 u8 reserved3[7]; 176 __le16 regular_latency_phy_queue; 177 __le16 dpi; 178 }; 179 180 /* 181 * roce create qp responder ramrod data 182 */ 183 struct roce_create_qp_resp_ramrod_data 184 { 185 __le32 flags; 186 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 187 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 188 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 189 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 190 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 191 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 192 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 193 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 194 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 195 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 196 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 197 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 198 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 199 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 200 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 201 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 202 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 203 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 204 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 205 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 206 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF 207 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17 208 __le16 xrc_domain /* SRC domain. Only applicable when xrc_flag is set */; 209 u8 max_ird; 210 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 211 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 212 u8 irq_num_pages; 213 __le16 p_key; 214 __le32 flow_label; 215 __le32 dst_qp_id; 216 u8 stats_counter_id /* Statistics counter ID to use */; 217 u8 reserved1; 218 __le16 mtu; 219 __le32 initial_psn; 220 __le16 pd; 221 __le16 rq_num_pages; 222 struct rdma_srq_id srq_id; 223 struct regpair rq_pbl_addr; 224 struct regpair irq_pbl_addr; 225 __le16 local_mac_addr[3] /* BE order */; 226 __le16 remote_mac_addr[3] /* BE order */; 227 __le16 vlan_id; 228 __le16 udp_src_port /* Only relevant in RRoCE */; 229 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 230 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 231 struct regpair qp_handle_for_cqe; 232 struct regpair qp_handle_for_async; 233 __le16 low_latency_phy_queue; 234 u8 reserved2[2]; 235 __le32 cq_cid; 236 __le16 regular_latency_phy_queue; 237 __le16 dpi; 238 }; 239 240 /* 241 * roce DCQCN received statistics 242 */ 243 struct roce_dcqcn_received_stats 244 { 245 struct regpair ecn_pkt_rcv /* The number of total packets with ECN indication received */; 246 struct regpair cnp_pkt_rcv /* The number of total RoCE packets with CNP opcode received */; 247 }; 248 249 /* 250 * roce DCQCN sent statistics 251 */ 252 struct roce_dcqcn_sent_stats 253 { 254 struct regpair cnp_pkt_sent /* The number of total RoCE packets with CNP opcode sent */; 255 }; 256 257 /* 258 * RoCE destroy qp requester output params 259 */ 260 struct roce_destroy_qp_req_output_params 261 { 262 __le32 num_bound_mw; 263 __le32 cq_prod /* Completion producer value at destroy QP */; 264 }; 265 266 /* 267 * RoCE destroy qp requester ramrod data 268 */ 269 struct roce_destroy_qp_req_ramrod_data 270 { 271 struct regpair output_params_addr; 272 }; 273 274 /* 275 * RoCE destroy qp responder output params 276 */ 277 struct roce_destroy_qp_resp_output_params 278 { 279 __le32 num_invalidated_mw; 280 __le32 cq_prod /* Completion producer value at destroy QP */; 281 }; 282 283 /* 284 * RoCE destroy qp responder ramrod data 285 */ 286 struct roce_destroy_qp_resp_ramrod_data 287 { 288 struct regpair output_params_addr; 289 }; 290 291 /* 292 * roce special events statistics 293 */ 294 struct roce_events_stats 295 { 296 __le16 silent_drops; 297 __le16 rnr_naks_sent; 298 __le32 retransmit_count; 299 __le32 icrc_error_count; 300 __le32 reserved; 301 }; 302 303 /* 304 * ROCE slow path EQ cmd IDs 305 */ 306 enum roce_event_opcode 307 { 308 ROCE_EVENT_CREATE_QP=11, 309 ROCE_EVENT_MODIFY_QP, 310 ROCE_EVENT_QUERY_QP, 311 ROCE_EVENT_DESTROY_QP, 312 ROCE_EVENT_CREATE_UD_QP, 313 ROCE_EVENT_DESTROY_UD_QP, 314 MAX_ROCE_EVENT_OPCODE 315 }; 316 317 /* 318 * roce func init ramrod data 319 */ 320 struct roce_init_func_params 321 { 322 u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */; 323 u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */; 324 u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */; 325 u8 reserved; 326 __le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */; 327 }; 328 329 /* 330 * roce func init ramrod data 331 */ 332 struct roce_init_func_ramrod_data 333 { 334 struct rdma_init_func_ramrod_data rdma; 335 struct roce_init_func_params roce; 336 }; 337 338 /* 339 * roce modify qp requester ramrod data 340 */ 341 struct roce_modify_qp_req_ramrod_data 342 { 343 __le16 flags; 344 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 345 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 346 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 347 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 348 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 349 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 350 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 351 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 352 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 353 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 354 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 355 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 356 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 357 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 358 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 359 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 360 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 361 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 362 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 363 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 364 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 365 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 366 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 367 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13 368 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 369 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 370 u8 fields; 371 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 372 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 373 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 374 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 375 u8 max_ord; 376 u8 traffic_class; 377 u8 hop_limit; 378 __le16 p_key; 379 __le32 flow_label; 380 __le32 ack_timeout_val; 381 __le16 mtu; 382 __le16 reserved2; 383 __le32 reserved3[2]; 384 __le16 low_latency_phy_queue; 385 __le16 regular_latency_phy_queue; 386 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 387 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 388 }; 389 390 /* 391 * roce modify qp responder ramrod data 392 */ 393 struct roce_modify_qp_resp_ramrod_data 394 { 395 __le16 flags; 396 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 397 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 398 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 399 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 400 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 401 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 402 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 403 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 404 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 405 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 406 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 407 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 408 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 409 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 410 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 411 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 412 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 413 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 414 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 415 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 416 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 417 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10 418 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F 419 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 420 u8 fields; 421 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 422 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 423 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 424 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 425 u8 max_ird; 426 u8 traffic_class; 427 u8 hop_limit; 428 __le16 p_key; 429 __le32 flow_label; 430 __le16 mtu; 431 __le16 low_latency_phy_queue; 432 __le16 regular_latency_phy_queue; 433 u8 reserved2[6]; 434 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 435 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 436 }; 437 438 /* 439 * RoCE query qp requester output params 440 */ 441 struct roce_query_qp_req_output_params 442 { 443 __le32 psn /* send next psn */; 444 __le32 flags; 445 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 446 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 447 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 448 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 449 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 450 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 451 }; 452 453 /* 454 * RoCE query qp requester ramrod data 455 */ 456 struct roce_query_qp_req_ramrod_data 457 { 458 struct regpair output_params_addr; 459 }; 460 461 /* 462 * RoCE query qp responder output params 463 */ 464 struct roce_query_qp_resp_output_params 465 { 466 __le32 psn /* send next psn */; 467 __le32 err_flag; 468 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 469 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 470 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 471 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 472 }; 473 474 /* 475 * RoCE query qp responder ramrod data 476 */ 477 struct roce_query_qp_resp_ramrod_data 478 { 479 struct regpair output_params_addr; 480 }; 481 482 /* 483 * ROCE ramrod command IDs 484 */ 485 enum roce_ramrod_cmd_id 486 { 487 ROCE_RAMROD_CREATE_QP=11, 488 ROCE_RAMROD_MODIFY_QP, 489 ROCE_RAMROD_QUERY_QP, 490 ROCE_RAMROD_DESTROY_QP, 491 ROCE_RAMROD_CREATE_UD_QP, 492 ROCE_RAMROD_DESTROY_UD_QP, 493 MAX_ROCE_RAMROD_CMD_ID 494 }; 495 496 struct e4_mstorm_roce_req_conn_ag_ctx 497 { 498 u8 byte0 /* cdu_validation */; 499 u8 byte1 /* state */; 500 u8 flags0; 501 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 502 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 503 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 504 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 505 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 506 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 507 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 508 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 509 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 510 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 511 u8 flags1; 512 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 513 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 514 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 515 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 516 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 517 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 518 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 519 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 520 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 521 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 522 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 523 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 524 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 525 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 526 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 527 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 528 __le16 word0 /* word0 */; 529 __le16 word1 /* word1 */; 530 __le32 reg0 /* reg0 */; 531 __le32 reg1 /* reg1 */; 532 }; 533 534 struct e4_mstorm_roce_resp_conn_ag_ctx 535 { 536 u8 byte0 /* cdu_validation */; 537 u8 byte1 /* state */; 538 u8 flags0; 539 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 540 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 541 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 542 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 543 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 544 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 545 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 546 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 547 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 548 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 549 u8 flags1; 550 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 551 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 552 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 553 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 554 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 555 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 556 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 557 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 558 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 559 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 560 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 561 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 562 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 563 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 564 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 565 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 566 __le16 word0 /* word0 */; 567 __le16 word1 /* word1 */; 568 __le32 reg0 /* reg0 */; 569 __le32 reg1 /* reg1 */; 570 }; 571 572 struct e4_tstorm_roce_req_conn_ag_ctx 573 { 574 u8 reserved0 /* cdu_validation */; 575 u8 state /* state */; 576 u8 flags0; 577 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 578 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 579 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 580 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 581 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 582 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 583 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 584 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 585 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 586 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 587 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 588 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 589 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 590 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 591 u8 flags1; 592 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 593 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 594 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 595 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 596 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 597 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 598 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 599 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 600 u8 flags2; 601 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 602 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 603 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 604 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 605 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 606 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 607 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 608 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 609 u8 flags3; 610 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 611 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 612 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 613 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 614 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 615 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 616 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 617 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 619 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 620 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 621 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 622 u8 flags4; 623 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 624 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 625 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 626 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 627 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 628 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 629 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 630 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 631 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 632 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 633 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 634 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 635 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 636 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 637 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 638 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 639 u8 flags5; 640 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 641 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 642 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 643 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 644 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 645 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 646 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 647 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 648 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 649 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 650 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 651 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 652 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 653 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 654 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 655 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 656 __le32 reg0 /* reg0 */; 657 __le32 snd_nxt_psn /* reg1 */; 658 __le32 snd_max_psn /* reg2 */; 659 __le32 orq_prod /* reg3 */; 660 __le32 reg4 /* reg4 */; 661 __le32 reg5 /* reg5 */; 662 __le32 reg6 /* reg6 */; 663 __le32 reg7 /* reg7 */; 664 __le32 reg8 /* reg8 */; 665 u8 tx_cqe_error_type /* byte2 */; 666 u8 orq_cache_idx /* byte3 */; 667 __le16 snd_sq_cons_th /* word0 */; 668 u8 byte4 /* byte4 */; 669 u8 byte5 /* byte5 */; 670 __le16 snd_sq_cons /* word1 */; 671 __le16 conn_dpi /* conn_dpi */; 672 __le16 word3 /* word3 */; 673 __le32 reg9 /* reg9 */; 674 __le32 reg10 /* reg10 */; 675 }; 676 677 struct e4_tstorm_roce_resp_conn_ag_ctx 678 { 679 u8 byte0 /* cdu_validation */; 680 u8 state /* state */; 681 u8 flags0; 682 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 683 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 684 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 685 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 686 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 687 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 688 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 689 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 690 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 691 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 692 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 693 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 694 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 695 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 696 u8 flags1; 697 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 698 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 699 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 700 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 701 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 702 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 703 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 704 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 705 u8 flags2; 706 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 707 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 708 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 709 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 710 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 711 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 712 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 713 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 714 u8 flags3; 715 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 716 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 717 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 718 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 719 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 720 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 721 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 722 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 723 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 724 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 725 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 726 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 727 u8 flags4; 728 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 729 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 730 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 731 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 732 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 733 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 734 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 735 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 736 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 737 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 738 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 739 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 740 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 741 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 742 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 743 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 744 u8 flags5; 745 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 746 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 747 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 748 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 749 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 750 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 751 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 752 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 753 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 754 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 755 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 756 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 757 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 758 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 759 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 760 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 761 __le32 psn_and_rxmit_id_echo /* reg0 */; 762 __le32 reg1 /* reg1 */; 763 __le32 reg2 /* reg2 */; 764 __le32 reg3 /* reg3 */; 765 __le32 reg4 /* reg4 */; 766 __le32 reg5 /* reg5 */; 767 __le32 reg6 /* reg6 */; 768 __le32 reg7 /* reg7 */; 769 __le32 reg8 /* reg8 */; 770 u8 tx_async_error_type /* byte2 */; 771 u8 byte3 /* byte3 */; 772 __le16 rq_cons /* word0 */; 773 u8 byte4 /* byte4 */; 774 u8 byte5 /* byte5 */; 775 __le16 rq_prod /* word1 */; 776 __le16 conn_dpi /* conn_dpi */; 777 __le16 irq_cons /* word3 */; 778 __le32 num_invlidated_mw /* reg9 */; 779 __le32 reg10 /* reg10 */; 780 }; 781 782 struct e4_ustorm_roce_req_conn_ag_ctx 783 { 784 u8 byte0 /* cdu_validation */; 785 u8 byte1 /* state */; 786 u8 flags0; 787 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 788 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 789 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 790 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 791 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 792 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 793 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 794 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 795 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 796 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 797 u8 flags1; 798 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 799 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 800 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 801 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 802 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 803 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 804 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 805 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 806 u8 flags2; 807 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 808 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 809 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 810 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 811 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 812 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 813 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 814 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 815 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 816 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 817 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 818 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 819 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 820 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 821 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 822 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 823 u8 flags3; 824 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 825 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 826 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 827 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 828 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 829 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 830 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 831 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 832 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 833 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 834 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 835 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 836 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 837 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 838 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 839 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 840 u8 byte2 /* byte2 */; 841 u8 byte3 /* byte3 */; 842 __le16 word0 /* conn_dpi */; 843 __le16 word1 /* word1 */; 844 __le32 reg0 /* reg0 */; 845 __le32 reg1 /* reg1 */; 846 __le32 reg2 /* reg2 */; 847 __le32 reg3 /* reg3 */; 848 __le16 word2 /* word2 */; 849 __le16 word3 /* word3 */; 850 }; 851 852 struct e4_ustorm_roce_resp_conn_ag_ctx 853 { 854 u8 byte0 /* cdu_validation */; 855 u8 byte1 /* state */; 856 u8 flags0; 857 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 858 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 859 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 860 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 861 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 862 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 863 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 864 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 865 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 866 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 867 u8 flags1; 868 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 869 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 870 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 871 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 872 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 873 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 874 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 875 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 876 u8 flags2; 877 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 878 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 879 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 880 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 881 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 882 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 883 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 884 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 885 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 886 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 887 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 888 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 889 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 890 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 891 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 892 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 893 u8 flags3; 894 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 895 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 896 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 897 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 898 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 899 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 900 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 901 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 902 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 903 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 904 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 905 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 906 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 907 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 908 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 909 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 910 u8 byte2 /* byte2 */; 911 u8 byte3 /* byte3 */; 912 __le16 word0 /* conn_dpi */; 913 __le16 word1 /* word1 */; 914 __le32 reg0 /* reg0 */; 915 __le32 reg1 /* reg1 */; 916 __le32 reg2 /* reg2 */; 917 __le32 reg3 /* reg3 */; 918 __le16 word2 /* word2 */; 919 __le16 word3 /* word3 */; 920 }; 921 922 struct e4_xstorm_roce_req_conn_ag_ctx 923 { 924 u8 reserved0 /* cdu_validation */; 925 u8 state /* state */; 926 u8 flags0; 927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 941 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 943 u8 flags1; 944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 958 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 960 u8 flags2; 961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 969 u8 flags3; 970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 976 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 977 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 978 u8 flags4; 979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 987 u8 flags5; 988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 990 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 993 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 994 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 996 u8 flags6; 997 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 1001 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1002 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 1003 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 1005 u8 flags7; 1006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1007 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 1008 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1009 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 1010 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1011 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1012 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1013 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 1014 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1015 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 1016 u8 flags8; 1017 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1018 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 1019 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1020 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 1021 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1022 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 1023 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1024 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1025 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1026 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 1027 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1028 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1029 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1030 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 1031 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1032 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 1033 u8 flags9; 1034 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1035 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 1036 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1037 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 1038 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1039 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 1040 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1041 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 1042 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1043 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 1044 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1045 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 1046 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1047 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 1048 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1049 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 1050 u8 flags10; 1051 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1052 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 1053 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1054 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 1055 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1056 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 1057 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1058 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 1059 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1060 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1061 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1062 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 1063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 1065 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1066 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 1067 u8 flags11; 1068 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1069 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 1070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 1072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1073 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 1074 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1075 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 1076 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1077 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 1078 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1079 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 1080 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1081 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1082 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1083 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 1084 u8 flags12; 1085 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1086 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 1087 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1088 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 1089 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1090 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1091 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1092 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1093 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1094 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 1095 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1096 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 1097 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1098 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 1099 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1100 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 1101 u8 flags13; 1102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1103 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 1104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 1106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1109 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1112 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1113 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1114 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1115 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1116 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1117 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1118 u8 flags14; 1119 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1120 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 1121 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1122 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 1123 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1124 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1125 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1126 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 1127 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1128 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1129 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1130 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 1131 u8 byte2 /* byte2 */; 1132 __le16 physical_q0 /* physical_q0 */; 1133 __le16 word1 /* physical_q1 */; 1134 __le16 sq_cmp_cons /* physical_q2 */; 1135 __le16 sq_cons /* word3 */; 1136 __le16 sq_prod /* word4 */; 1137 __le16 word5 /* word5 */; 1138 __le16 conn_dpi /* conn_dpi */; 1139 u8 byte3 /* byte3 */; 1140 u8 byte4 /* byte4 */; 1141 u8 byte5 /* byte5 */; 1142 u8 byte6 /* byte6 */; 1143 __le32 lsn /* reg0 */; 1144 __le32 ssn /* reg1 */; 1145 __le32 snd_una_psn /* reg2 */; 1146 __le32 snd_nxt_psn /* reg3 */; 1147 __le32 reg4 /* reg4 */; 1148 __le32 orq_cons_th /* cf_array0 */; 1149 __le32 orq_cons /* cf_array1 */; 1150 }; 1151 1152 struct e4_xstorm_roce_resp_conn_ag_ctx 1153 { 1154 u8 reserved0 /* cdu_validation */; 1155 u8 state /* state */; 1156 u8 flags0; 1157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 1161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 1163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 1167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 1168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 1169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 1171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1172 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 1173 u8 flags1; 1174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 1176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 1178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 1180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 1182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 1184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 1186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 1187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 1188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1189 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1190 u8 flags2; 1191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 1193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 1195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 1197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 1199 u8 flags3; 1200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 1201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 1202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 1204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 1205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 1206 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1207 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1208 u8 flags4; 1209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 1211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 1213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 1215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 1217 u8 flags5; 1218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 1220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1221 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 1222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1223 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 1224 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1225 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 1226 u8 flags6; 1227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1228 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 1229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 1231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1232 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 1233 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 1235 u8 flags7; 1236 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 1238 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1239 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 1240 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1241 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1242 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1243 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 1244 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1245 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 1246 u8 flags8; 1247 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1248 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 1249 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1250 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 1251 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 1252 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 1253 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1254 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1255 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 1256 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 1257 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1258 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1259 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1260 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 1261 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1262 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 1263 u8 flags9; 1264 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1265 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 1266 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1267 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 1268 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1269 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 1270 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1271 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 1272 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1273 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 1274 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1275 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 1276 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1277 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 1278 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1279 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 1280 u8 flags10; 1281 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1282 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 1283 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1284 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 1285 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1286 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 1287 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1288 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 1289 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1290 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1291 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 1293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 1295 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1296 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 1297 u8 flags11; 1298 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 1300 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 1302 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1303 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 1304 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1305 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 1306 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1307 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 1308 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1309 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 1310 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1311 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1312 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1313 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 1314 u8 flags12; 1315 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule10en */ 1316 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 1317 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1318 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 1319 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1320 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1321 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1322 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1323 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1324 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 1325 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1326 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 1327 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 1329 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1330 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 1331 u8 flags13; 1332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 1334 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 1336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1338 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1344 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1345 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1346 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1347 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1348 u8 flags14; 1349 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1350 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 1351 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1352 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 1353 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 1354 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 1355 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 1356 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 1357 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1358 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 1359 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 1360 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 1361 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1362 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 1363 u8 byte2 /* byte2 */; 1364 __le16 physical_q0 /* physical_q0 */; 1365 __le16 irq_prod_shadow /* physical_q1 */; 1366 __le16 word2 /* physical_q2 */; 1367 __le16 irq_cons /* word3 */; 1368 __le16 irq_prod /* word4 */; 1369 __le16 e5_reserved1 /* word5 */; 1370 __le16 conn_dpi /* conn_dpi */; 1371 u8 rxmit_opcode /* byte3 */; 1372 u8 byte4 /* byte4 */; 1373 u8 byte5 /* byte5 */; 1374 u8 byte6 /* byte6 */; 1375 __le32 rxmit_psn_and_id /* reg0 */; 1376 __le32 rxmit_bytes_length /* reg1 */; 1377 __le32 psn /* reg2 */; 1378 __le32 reg3 /* reg3 */; 1379 __le32 reg4 /* reg4 */; 1380 __le32 reg5 /* cf_array0 */; 1381 __le32 msn_and_syndrome /* cf_array1 */; 1382 }; 1383 1384 struct e4_ystorm_roce_req_conn_ag_ctx 1385 { 1386 u8 byte0 /* cdu_validation */; 1387 u8 byte1 /* state */; 1388 u8 flags0; 1389 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1390 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1391 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1392 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1393 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1394 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1395 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1396 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1397 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1398 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1399 u8 flags1; 1400 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1401 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1402 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1403 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1404 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1405 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1406 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1407 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1408 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1409 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1410 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1411 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1412 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1413 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1414 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1415 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1416 u8 byte2 /* byte2 */; 1417 u8 byte3 /* byte3 */; 1418 __le16 word0 /* word0 */; 1419 __le32 reg0 /* reg0 */; 1420 __le32 reg1 /* reg1 */; 1421 __le16 word1 /* word1 */; 1422 __le16 word2 /* word2 */; 1423 __le16 word3 /* word3 */; 1424 __le16 word4 /* word4 */; 1425 __le32 reg2 /* reg2 */; 1426 __le32 reg3 /* reg3 */; 1427 }; 1428 1429 struct e4_ystorm_roce_resp_conn_ag_ctx 1430 { 1431 u8 byte0 /* cdu_validation */; 1432 u8 byte1 /* state */; 1433 u8 flags0; 1434 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1435 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1436 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1437 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1438 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1439 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1440 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1441 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1442 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1443 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1444 u8 flags1; 1445 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1446 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1447 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1448 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1449 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1450 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1451 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1452 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1453 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1454 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1455 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1456 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1457 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1458 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1459 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1460 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1461 u8 byte2 /* byte2 */; 1462 u8 byte3 /* byte3 */; 1463 __le16 word0 /* word0 */; 1464 __le32 reg0 /* reg0 */; 1465 __le32 reg1 /* reg1 */; 1466 __le16 word1 /* word1 */; 1467 __le16 word2 /* word2 */; 1468 __le16 word3 /* word3 */; 1469 __le16 word4 /* word4 */; 1470 __le32 reg2 /* reg2 */; 1471 __le32 reg3 /* reg3 */; 1472 }; 1473 1474 struct E5XstormRoceConnAgCtxDqExtLdPart 1475 { 1476 u8 reserved0 /* cdu_validation */; 1477 u8 state_and_core_id /* state_and_core_id */; 1478 u8 flags0; 1479 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1480 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1481 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1482 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1483 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1484 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1485 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1486 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1487 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1488 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1489 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1490 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1491 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1492 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1493 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1494 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1495 u8 flags1; 1496 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1497 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1498 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1499 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1500 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 1501 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 1502 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1503 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1504 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 1505 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1506 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */ 1507 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1508 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_MASK 0x1 /* bit14 */ 1509 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_SHIFT 6 1510 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1511 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 1512 u8 flags2; 1513 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1514 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1515 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1516 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1517 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1518 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1519 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1520 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1521 u8 flags3; 1522 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 1523 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_SHIFT 0 1524 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1525 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_SHIFT 2 1526 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 1527 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_SHIFT 4 1528 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1529 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 1530 u8 flags4; 1531 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1532 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1533 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1534 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1535 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1536 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1537 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1538 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1539 u8 flags5; 1540 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1541 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1542 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1543 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1544 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 1545 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_SHIFT 4 1546 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1547 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1548 u8 flags6; 1549 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 1550 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 1551 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 1552 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 1553 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 1554 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 1555 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 1556 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 1557 u8 flags7; 1558 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 1559 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 1560 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 1561 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 1562 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1563 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1564 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1565 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1566 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1567 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1568 u8 flags8; 1569 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1570 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1571 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1572 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1573 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1574 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_SHIFT 2 1575 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1576 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_SHIFT 3 1577 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1578 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_SHIFT 4 1579 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1580 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 1581 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1582 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1583 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1584 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1585 u8 flags9; 1586 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1587 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1588 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1589 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1590 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1591 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1592 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1593 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1594 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1595 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_SHIFT 4 1596 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1597 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1598 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 1599 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 1600 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1601 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 1602 u8 flags10; 1603 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 1604 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 1605 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 1606 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 1607 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 1608 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 1609 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 1610 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 1611 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1612 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1613 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 1614 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 1615 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 1616 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 1617 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 1618 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 1619 u8 flags11; 1620 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 1621 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 1622 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 1623 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 1624 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 1625 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 1626 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1627 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1628 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1629 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1630 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1631 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_SHIFT 5 1632 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1633 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1634 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1635 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1636 u8 flags12; 1637 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1638 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_SHIFT 0 1639 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1640 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1641 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1642 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1643 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1644 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1645 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1646 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_SHIFT 4 1647 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1648 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1649 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1650 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_SHIFT 6 1651 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1652 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_SHIFT 7 1653 u8 flags13; 1654 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1655 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1656 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1657 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1658 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1659 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1660 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1661 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1662 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1663 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1664 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1665 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1666 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1667 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1668 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1669 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1670 u8 flags14; 1671 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1672 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_SHIFT 0 1673 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 1674 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 1675 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1676 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 1677 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 1678 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 1679 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1680 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1681 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 1682 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 1683 u8 byte2 /* byte2 */; 1684 __le16 physical_q0 /* physical_q0 */; 1685 __le16 word1 /* physical_q1 */; 1686 __le16 sq_cmp_cons /* physical_q2 */; 1687 __le16 sq_cons /* word3 */; 1688 __le16 sq_prod /* word4 */; 1689 __le16 word5 /* word5 */; 1690 __le16 conn_dpi /* conn_dpi */; 1691 u8 byte3 /* byte3 */; 1692 u8 byte4 /* byte4 */; 1693 u8 byte5 /* byte5 */; 1694 u8 byte6 /* byte6 */; 1695 __le32 lsn /* reg0 */; 1696 __le32 ssn /* reg1 */; 1697 __le32 snd_una_psn /* reg2 */; 1698 __le32 snd_nxt_psn /* reg3 */; 1699 __le32 reg4 /* reg4 */; 1700 __le32 orq_cons_th /* cf_array0 */; 1701 __le32 orq_cons /* cf_array1 */; 1702 u8 flags15; 1703 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_MASK 0x1 /* bit22 */ 1704 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_SHIFT 0 1705 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_MASK 0x1 /* bit23 */ 1706 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_SHIFT 1 1707 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_MASK 0x1 /* bit24 */ 1708 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_SHIFT 2 1709 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_MASK 0x3 /* cf24 */ 1710 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_SHIFT 3 1711 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_MASK 0x1 /* cf24en */ 1712 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_SHIFT 5 1713 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_MASK 0x1 /* rule26en */ 1714 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_SHIFT 6 1715 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_MASK 0x1 /* rule27en */ 1716 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_SHIFT 7 1717 u8 byte7 /* byte7 */; 1718 __le16 word7 /* word7 */; 1719 __le16 word8 /* word8 */; 1720 __le16 word9 /* word9 */; 1721 __le16 word10 /* word10 */; 1722 __le16 tx_rdma_edpm_usg_cnt /* word11 */; 1723 __le32 reg7 /* reg7 */; 1724 __le32 reg8 /* reg8 */; 1725 __le32 reg9 /* reg9 */; 1726 u8 byte8 /* byte8 */; 1727 u8 byte9 /* byte9 */; 1728 u8 byte10 /* byte10 */; 1729 u8 byte11 /* byte11 */; 1730 u8 byte12 /* byte12 */; 1731 u8 byte13 /* byte13 */; 1732 u8 byte14 /* byte14 */; 1733 u8 byte15 /* byte15 */; 1734 __le32 reg10 /* reg10 */; 1735 __le32 reg11 /* reg11 */; 1736 __le32 reg12 /* reg12 */; 1737 __le32 reg13 /* reg13 */; 1738 }; 1739 1740 struct e5_mstorm_roce_req_conn_ag_ctx 1741 { 1742 u8 byte0 /* cdu_validation */; 1743 u8 byte1 /* state_and_core_id */; 1744 u8 flags0; 1745 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1746 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1747 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1748 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1749 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1750 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1751 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1752 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1753 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1754 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1755 u8 flags1; 1756 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1757 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1758 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1759 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1760 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1761 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1762 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1763 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1764 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1765 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1766 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1767 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1768 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1769 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1770 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1771 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1772 __le16 word0 /* word0 */; 1773 __le16 word1 /* word1 */; 1774 __le32 reg0 /* reg0 */; 1775 __le32 reg1 /* reg1 */; 1776 }; 1777 1778 struct e5_mstorm_roce_resp_conn_ag_ctx 1779 { 1780 u8 byte0 /* cdu_validation */; 1781 u8 byte1 /* state_and_core_id */; 1782 u8 flags0; 1783 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1784 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1785 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1786 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1787 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1788 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1789 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1790 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1791 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1792 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1793 u8 flags1; 1794 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1795 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1796 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1797 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1798 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1799 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1800 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1801 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1802 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1803 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1804 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1805 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1806 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1807 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1808 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1809 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1810 __le16 word0 /* word0 */; 1811 __le16 word1 /* word1 */; 1812 __le32 reg0 /* reg0 */; 1813 __le32 reg1 /* reg1 */; 1814 }; 1815 1816 struct e5_tstorm_roce_req_conn_ag_ctx 1817 { 1818 u8 reserved0 /* cdu_validation */; 1819 u8 state_and_core_id /* state_and_core_id */; 1820 u8 flags0; 1821 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1822 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1823 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 1824 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 1825 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 1826 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 1827 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1828 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 1829 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1830 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1831 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 1832 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 1833 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 1834 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 1835 u8 flags1; 1836 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1837 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 1838 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 1839 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 1840 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1841 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1842 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1843 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1844 u8 flags2; 1845 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1846 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1847 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 1848 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 1849 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 1850 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 1851 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 1852 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 1853 u8 flags3; 1854 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 1855 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 1856 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 1857 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 1858 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1859 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 1860 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1861 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 1862 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 1863 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 1864 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1865 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1866 u8 flags4; 1867 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1868 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1869 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1870 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1871 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 1872 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 1873 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 1874 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 1875 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 1876 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 1877 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 1878 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 1879 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 1880 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 1881 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1882 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 1883 u8 flags5; 1884 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1885 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 1886 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1887 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 1888 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1889 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 1890 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1891 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 1892 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1893 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 1894 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 1895 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 1896 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1897 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 1898 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1899 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 1900 u8 flags6; 1901 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1902 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1903 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1904 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1905 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1906 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1907 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1908 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1909 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1910 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1911 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1912 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1913 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1914 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1915 u8 tx_cqe_error_type /* byte2 */; 1916 __le16 snd_sq_cons_th /* word0 */; 1917 __le32 reg0 /* reg0 */; 1918 __le32 snd_nxt_psn /* reg1 */; 1919 __le32 snd_max_psn /* reg2 */; 1920 __le32 orq_prod /* reg3 */; 1921 __le32 reg4 /* reg4 */; 1922 __le32 reg5 /* reg5 */; 1923 __le32 reg6 /* reg6 */; 1924 __le32 reg7 /* reg7 */; 1925 __le32 reg8 /* reg8 */; 1926 u8 orq_cache_idx /* byte3 */; 1927 u8 byte4 /* byte4 */; 1928 u8 byte5 /* byte5 */; 1929 u8 e4_reserved8 /* byte6 */; 1930 __le16 snd_sq_cons /* word1 */; 1931 __le16 word2 /* conn_dpi */; 1932 __le32 reg9 /* reg9 */; 1933 __le16 word3 /* word3 */; 1934 __le16 e4_reserved9 /* word4 */; 1935 }; 1936 1937 struct e5_tstorm_roce_resp_conn_ag_ctx 1938 { 1939 u8 byte0 /* cdu_validation */; 1940 u8 state_and_core_id /* state_and_core_id */; 1941 u8 flags0; 1942 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1943 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1944 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 1945 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 1946 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1947 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 1948 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1949 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 1950 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1951 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1952 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1953 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 1954 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1955 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 1956 u8 flags1; 1957 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 1958 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 1959 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 1960 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 1961 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1962 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 1963 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1964 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1965 u8 flags2; 1966 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1967 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1968 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1969 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 1970 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1971 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 1972 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1973 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 1974 u8 flags3; 1975 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1976 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 1977 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1978 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 1979 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1980 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 1981 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 1982 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 1983 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 1984 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 1985 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1986 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 1987 u8 flags4; 1988 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1989 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1990 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1991 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1992 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1993 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 1994 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1995 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 1996 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1997 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 1998 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1999 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 2000 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2001 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 2002 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2003 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2004 u8 flags5; 2005 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2006 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2007 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2008 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2009 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2010 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2011 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2012 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2013 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2014 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2015 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 2016 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 2017 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2018 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2019 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2020 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2021 u8 flags6; 2022 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 2023 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2024 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 2025 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2026 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 2027 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2028 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 2029 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2030 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 2031 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2032 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 2033 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2034 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 2035 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2036 u8 tx_async_error_type /* byte2 */; 2037 __le16 rq_cons /* word0 */; 2038 __le32 psn_and_rxmit_id_echo /* reg0 */; 2039 __le32 reg1 /* reg1 */; 2040 __le32 reg2 /* reg2 */; 2041 __le32 reg3 /* reg3 */; 2042 __le32 reg4 /* reg4 */; 2043 __le32 reg5 /* reg5 */; 2044 __le32 reg6 /* reg6 */; 2045 __le32 reg7 /* reg7 */; 2046 __le32 reg8 /* reg8 */; 2047 u8 byte3 /* byte3 */; 2048 u8 byte4 /* byte4 */; 2049 u8 byte5 /* byte5 */; 2050 u8 e4_reserved8 /* byte6 */; 2051 __le16 rq_prod /* word1 */; 2052 __le16 conn_dpi /* conn_dpi */; 2053 __le32 num_invlidated_mw /* reg9 */; 2054 __le16 irq_cons /* word3 */; 2055 __le16 e4_reserved9 /* word4 */; 2056 }; 2057 2058 struct e5_ustorm_roce_req_conn_ag_ctx 2059 { 2060 u8 byte0 /* cdu_validation */; 2061 u8 byte1 /* state_and_core_id */; 2062 u8 flags0; 2063 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2064 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2065 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2066 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2067 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2068 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2069 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2070 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2071 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2072 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2073 u8 flags1; 2074 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2075 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 2076 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2077 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 2078 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2079 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 2080 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2081 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 2082 u8 flags2; 2083 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2084 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2085 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2086 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2087 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2088 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2089 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2090 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 2091 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2092 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 2093 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2094 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 2095 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2096 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 2097 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2098 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 2099 u8 flags3; 2100 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2101 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 2102 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2103 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 2104 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2105 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 2106 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2107 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 2108 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2109 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 2110 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2111 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 2112 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2113 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 2114 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2115 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 2116 u8 flags4; 2117 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2118 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2119 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2120 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2121 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2122 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2123 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2124 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2125 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2126 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2127 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2128 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2129 u8 byte2 /* byte2 */; 2130 __le16 word0 /* conn_dpi */; 2131 __le16 word1 /* word1 */; 2132 __le32 reg0 /* reg0 */; 2133 __le32 reg1 /* reg1 */; 2134 __le32 reg2 /* reg2 */; 2135 __le32 reg3 /* reg3 */; 2136 __le16 word2 /* word2 */; 2137 __le16 word3 /* word3 */; 2138 }; 2139 2140 struct e5_ustorm_roce_resp_conn_ag_ctx 2141 { 2142 u8 byte0 /* cdu_validation */; 2143 u8 byte1 /* state_and_core_id */; 2144 u8 flags0; 2145 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2146 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2147 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2148 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2149 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2150 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2151 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2152 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2153 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2154 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2155 u8 flags1; 2156 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2157 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 2158 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2159 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 2160 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2161 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 2162 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2163 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 2164 u8 flags2; 2165 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2166 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2167 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2168 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2169 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2170 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2171 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2172 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 2173 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2174 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 2175 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2176 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 2177 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2178 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 2179 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2180 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2181 u8 flags3; 2182 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2183 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2184 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2185 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2186 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2187 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2188 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2189 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2190 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2191 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2192 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2193 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 2194 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2195 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2196 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2197 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2198 u8 flags4; 2199 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2200 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2201 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2202 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2203 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2204 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2205 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2206 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2207 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2208 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2209 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2210 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2211 u8 byte2 /* byte2 */; 2212 __le16 word0 /* conn_dpi */; 2213 __le16 word1 /* word1 */; 2214 __le32 reg0 /* reg0 */; 2215 __le32 reg1 /* reg1 */; 2216 __le32 reg2 /* reg2 */; 2217 __le32 reg3 /* reg3 */; 2218 __le16 word2 /* word2 */; 2219 __le16 word3 /* word3 */; 2220 }; 2221 2222 struct e5_xstorm_roce_req_conn_ag_ctx 2223 { 2224 u8 reserved0 /* cdu_validation */; 2225 u8 state_and_core_id /* state_and_core_id */; 2226 u8 flags0; 2227 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2228 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2229 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2230 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 2231 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2232 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 2233 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2234 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2235 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2236 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 2237 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2238 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 2239 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2240 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 2241 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2242 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 2243 u8 flags1; 2244 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2245 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 2246 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2247 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 2248 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2249 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 2250 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2251 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 2252 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2253 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 2254 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2255 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 2256 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2257 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2258 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2259 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2260 u8 flags2; 2261 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2262 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 2263 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2264 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 2265 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2266 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 2267 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2268 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 2269 u8 flags3; 2270 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 2271 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 2272 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2273 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2274 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 2275 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 2276 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2277 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2278 u8 flags4; 2279 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2280 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 2281 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2282 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 2283 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2284 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 2285 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2286 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 2287 u8 flags5; 2288 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2289 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 2290 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2291 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 2292 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 2293 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 2294 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2295 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 2296 u8 flags6; 2297 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2298 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 2299 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2300 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 2301 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2302 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 2303 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2304 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 2305 u8 flags7; 2306 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2307 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 2308 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2309 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 2310 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2311 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2312 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2313 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 2314 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2315 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 2316 u8 flags8; 2317 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2318 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 2319 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2320 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 2321 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 2322 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 2323 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2324 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2325 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 2326 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 2327 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2328 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2329 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2330 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 2331 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2332 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 2333 u8 flags9; 2334 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2335 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 2336 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2337 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 2338 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2339 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 2340 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2341 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 2342 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 2343 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 2344 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2345 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 2346 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2347 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 2348 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2349 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 2350 u8 flags10; 2351 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2352 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 2353 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2354 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 2355 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2356 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 2357 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2358 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 2359 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2360 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2361 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2362 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 2363 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2364 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 2365 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2366 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 2367 u8 flags11; 2368 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2369 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 2370 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2371 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 2372 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2373 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 2374 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2375 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 2376 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2377 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 2378 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 2379 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 2380 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2381 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2382 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2383 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 2384 u8 flags12; 2385 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 2386 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 2387 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2388 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 2389 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2390 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2391 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2392 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2393 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 2394 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 2395 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2396 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 2397 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 2398 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 2399 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 2400 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 2401 u8 flags13; 2402 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2403 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 2404 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2405 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 2406 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2407 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2408 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2409 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2410 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2411 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2412 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2413 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2414 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2415 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2416 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2417 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2418 u8 flags14; 2419 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 2420 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 2421 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2422 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 2423 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2424 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2425 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2426 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 2427 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2428 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2429 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2430 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 2431 u8 byte2 /* byte2 */; 2432 __le16 physical_q0 /* physical_q0 */; 2433 __le16 word1 /* physical_q1 */; 2434 __le16 sq_cmp_cons /* physical_q2 */; 2435 __le16 sq_cons /* word3 */; 2436 __le16 sq_prod /* word4 */; 2437 __le16 word5 /* word5 */; 2438 __le16 conn_dpi /* conn_dpi */; 2439 u8 byte3 /* byte3 */; 2440 u8 byte4 /* byte4 */; 2441 u8 byte5 /* byte5 */; 2442 u8 byte6 /* byte6 */; 2443 __le32 lsn /* reg0 */; 2444 __le32 ssn /* reg1 */; 2445 __le32 snd_una_psn /* reg2 */; 2446 __le32 snd_nxt_psn /* reg3 */; 2447 __le32 reg4 /* reg4 */; 2448 __le32 orq_cons_th /* cf_array0 */; 2449 __le32 orq_cons /* cf_array1 */; 2450 }; 2451 2452 struct e5_xstorm_roce_resp_conn_ag_ctx 2453 { 2454 u8 reserved0 /* cdu_validation */; 2455 u8 state_and_core_id /* state_and_core_id */; 2456 u8 flags0; 2457 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2458 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2459 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2460 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 2461 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2462 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 2463 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2464 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2465 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2466 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 2467 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2468 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 2469 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2470 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 2471 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2472 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 2473 u8 flags1; 2474 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2475 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 2476 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2477 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 2478 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2479 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 2480 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2481 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 2482 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2483 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 2484 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2485 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 2486 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2487 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2488 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2489 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2490 u8 flags2; 2491 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2492 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 2493 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2494 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 2495 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2496 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 2497 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2498 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 2499 u8 flags3; 2500 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 2501 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 2502 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2503 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2504 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 2505 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 2506 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2507 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2508 u8 flags4; 2509 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2510 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 2511 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2512 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 2513 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2514 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 2515 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2516 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 2517 u8 flags5; 2518 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2519 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 2520 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2521 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 2522 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2523 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 2524 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2525 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 2526 u8 flags6; 2527 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2528 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 2529 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2530 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 2531 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2532 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 2533 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2534 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 2535 u8 flags7; 2536 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2537 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 2538 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2539 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 2540 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2541 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2542 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2543 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 2544 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2545 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 2546 u8 flags8; 2547 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2548 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 2549 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2550 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 2551 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 2552 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 2553 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2554 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2555 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 2556 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 2557 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2558 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2559 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2560 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 2561 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2562 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 2563 u8 flags9; 2564 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2565 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 2566 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2567 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 2568 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2569 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 2570 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2571 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 2572 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2573 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 2574 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2575 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 2576 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2577 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 2578 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2579 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 2580 u8 flags10; 2581 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2582 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 2583 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2584 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 2585 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2586 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 2587 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2588 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 2589 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2590 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2591 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2592 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 2593 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2594 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 2595 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2596 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 2597 u8 flags11; 2598 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2599 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 2600 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2601 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 2602 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2603 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 2604 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2605 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 2606 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2607 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 2608 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2609 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 2610 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2611 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2612 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2613 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 2614 u8 flags12; 2615 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2616 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 2617 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule11en */ 2618 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 2619 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2620 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2621 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2622 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2623 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2624 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 2625 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2626 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 2627 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2628 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 2629 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2630 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 2631 u8 flags13; 2632 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2633 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 2634 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2635 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 2636 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2637 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2638 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2639 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2640 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2641 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2642 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2643 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2644 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2645 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2646 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2647 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2648 u8 flags14; 2649 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 2650 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 2651 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2652 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 2653 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 2654 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 2655 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 2656 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 2657 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 2658 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 2659 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 2660 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 2661 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2662 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 2663 u8 byte2 /* byte2 */; 2664 __le16 physical_q0 /* physical_q0 */; 2665 __le16 word1 /* physical_q1 */; 2666 __le16 irq_prod /* physical_q2 */; 2667 __le16 word3 /* word3 */; 2668 __le16 word4 /* word4 */; 2669 __le16 ack_cons /* word5 */; 2670 __le16 irq_cons /* conn_dpi */; 2671 u8 rxmit_opcode /* byte3 */; 2672 u8 byte4 /* byte4 */; 2673 u8 byte5 /* byte5 */; 2674 u8 byte6 /* byte6 */; 2675 __le32 rxmit_psn_and_id /* reg0 */; 2676 __le32 rxmit_bytes_length /* reg1 */; 2677 __le32 psn /* reg2 */; 2678 __le32 reg3 /* reg3 */; 2679 __le32 reg4 /* reg4 */; 2680 __le32 reg5 /* cf_array0 */; 2681 __le32 msn_and_syndrome /* cf_array1 */; 2682 }; 2683 2684 struct e5_ystorm_roce_req_conn_ag_ctx 2685 { 2686 u8 byte0 /* cdu_validation */; 2687 u8 byte1 /* state_and_core_id */; 2688 u8 flags0; 2689 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2690 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2691 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2692 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2693 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2694 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2695 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2696 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2697 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2698 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2699 u8 flags1; 2700 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2701 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2702 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2703 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2704 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2705 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2706 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2707 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 2708 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2709 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 2710 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2711 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 2712 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2713 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 2714 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2715 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 2716 u8 byte2 /* byte2 */; 2717 u8 byte3 /* byte3 */; 2718 __le16 word0 /* word0 */; 2719 __le32 reg0 /* reg0 */; 2720 __le32 reg1 /* reg1 */; 2721 __le16 word1 /* word1 */; 2722 __le16 word2 /* word2 */; 2723 __le16 word3 /* word3 */; 2724 __le16 word4 /* word4 */; 2725 __le32 reg2 /* reg2 */; 2726 __le32 reg3 /* reg3 */; 2727 }; 2728 2729 struct e5_ystorm_roce_resp_conn_ag_ctx 2730 { 2731 u8 byte0 /* cdu_validation */; 2732 u8 byte1 /* state_and_core_id */; 2733 u8 flags0; 2734 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2735 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2736 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2737 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2738 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2739 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2740 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2741 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2742 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2743 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2744 u8 flags1; 2745 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2746 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2747 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2748 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2749 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2750 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2751 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2752 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 2753 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2754 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 2755 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2756 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 2757 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2758 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 2759 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2760 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 2761 u8 byte2 /* byte2 */; 2762 u8 byte3 /* byte3 */; 2763 __le16 word0 /* word0 */; 2764 __le32 reg0 /* reg0 */; 2765 __le32 reg1 /* reg1 */; 2766 __le16 word1 /* word1 */; 2767 __le16 word2 /* word2 */; 2768 __le16 word3 /* word3 */; 2769 __le16 word4 /* word4 */; 2770 __le32 reg2 /* reg2 */; 2771 __le32 reg3 /* reg3 */; 2772 }; 2773 2774 /* 2775 * Roce doorbell data 2776 */ 2777 enum roce_flavor 2778 { 2779 PLAIN_ROCE /* RoCE v1 */, 2780 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */, 2781 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */, 2782 MAX_ROCE_FLAVOR 2783 }; 2784 2785 #endif /* __ECORE_HSI_ROCE__ */
Cache object: f74d119d180d832c7c0d6eccebe2abc3
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