The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/qlnx/qlnxe/ecore_init_ops.h

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    1 /*
    2  * Copyright (c) 2017-2018 Cavium, Inc. 
    3  * All rights reserved.
    4  *
    5  *  Redistribution and use in source and binary forms, with or without
    6  *  modification, are permitted provided that the following conditions
    7  *  are met:
    8  *
    9  *  1. Redistributions of source code must retain the above copyright
   10  *     notice, this list of conditions and the following disclaimer.
   11  *  2. Redistributions in binary form must reproduce the above copyright
   12  *     notice, this list of conditions and the following disclaimer in the
   13  *     documentation and/or other materials provided with the distribution.
   14  *
   15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   25  *  POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  *
   29  */
   30 
   31 #ifndef __ECORE_INIT_OPS__
   32 #define __ECORE_INIT_OPS__
   33 
   34 #include "ecore.h"
   35 
   36 /**
   37  * @brief ecore_init_iro_array - init iro_arr.
   38  *
   39  *
   40  * @param p_dev
   41  */
   42 void ecore_init_iro_array(struct ecore_dev *p_dev);
   43 
   44 /**
   45  * @brief ecore_init_run - Run the init-sequence.
   46  *
   47  *
   48  * @param p_hwfn
   49  * @param p_ptt
   50  * @param phase 
   51  * @param phase_id 
   52  * @param modes
   53  * @return _ecore_status_t
   54  */
   55 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
   56                                     struct ecore_ptt  *p_ptt,
   57                                     int               phase,
   58                                     int               phase_id,
   59                                     int               modes);
   60 
   61 /**
   62  * @brief ecore_init_hwfn_allocate - Allocate RT array, Store 'values' ptrs.
   63  *
   64  *
   65  * @param p_hwfn
   66  *
   67  * @return _ecore_status_t
   68  */
   69 enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn);
   70 
   71 /**
   72  * @brief ecore_init_hwfn_deallocate
   73  *
   74  *
   75  * @param p_hwfn
   76  */
   77 void ecore_init_free(struct ecore_hwfn *p_hwfn);
   78 
   79 /**
   80  * @brief ecore_init_clear_rt_data - Clears the runtime init array.
   81  *
   82  *
   83  * @param p_hwfn
   84  */
   85 void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn);
   86 
   87 /**
   88  * @brief ecore_init_store_rt_reg - Store a configuration value in the RT array.
   89  *
   90  *
   91  * @param p_hwfn
   92  * @param rt_offset
   93  * @param val
   94  */
   95 void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn,
   96                              u32                rt_offset,
   97                              u32                val);
   98 
   99 #define STORE_RT_REG(hwfn, offset, val)                         \
  100         ecore_init_store_rt_reg(hwfn, offset, val)
  101 
  102 #define OVERWRITE_RT_REG(hwfn, offset, val)                     \
  103         ecore_init_store_rt_reg(hwfn, offset, val)
  104 
  105 /**
  106 * @brief
  107 *
  108 *
  109 * @param p_hwfn
  110 * @param rt_offset
  111 * @param val
  112 * @param size
  113 */
  114 
  115 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
  116                              u32               rt_offset,
  117                              u32               *val,
  118                              osal_size_t       size);
  119 
  120 #define STORE_RT_REG_AGG(hwfn, offset, val)                     \
  121         ecore_init_store_rt_agg(hwfn, offset, (u32*)&val, sizeof(val))
  122 
  123 /**
  124  * @brief 
  125  *      Initialize GTT global windows and set admin window
  126  *      related params of GTT/PTT to default values. 
  127  * 
  128  * @param p_hwfn 
  129  */
  130 void ecore_gtt_init(struct ecore_hwfn *p_hwfn,
  131                     struct ecore_ptt *p_ptt);
  132 #endif /* __ECORE_INIT_OPS__ */

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