The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/qlnx/qlnxe/ecore_sp_commands.h

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    1 /*
    2  * Copyright (c) 2017-2018 Cavium, Inc. 
    3  * All rights reserved.
    4  *
    5  *  Redistribution and use in source and binary forms, with or without
    6  *  modification, are permitted provided that the following conditions
    7  *  are met:
    8  *
    9  *  1. Redistributions of source code must retain the above copyright
   10  *     notice, this list of conditions and the following disclaimer.
   11  *  2. Redistributions in binary form must reproduce the above copyright
   12  *     notice, this list of conditions and the following disclaimer in the
   13  *     documentation and/or other materials provided with the distribution.
   14  *
   15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   25  *  POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  *
   29  */
   30 
   31 #ifndef __ECORE_SP_COMMANDS_H__
   32 #define __ECORE_SP_COMMANDS_H__
   33 
   34 #include "ecore.h"
   35 #include "ecore_spq.h"
   36 #include "ecore_sp_api.h"
   37 
   38 #define ECORE_SP_EQ_COMPLETION  0x01
   39 #define ECORE_SP_CQE_COMPLETION 0x02
   40 
   41 struct ecore_sp_init_data {
   42         /* The CID and FID aren't necessarily derived from hwfn,
   43          * e.g., in IOV scenarios. CID might defer between SPQ and
   44          * other elements.
   45          */
   46         u32                             cid;
   47         u16                             opaque_fid;
   48 
   49         /* Information regarding operation upon sending & completion */
   50         enum spq_mode                   comp_mode;
   51         struct ecore_spq_comp_cb        *p_comp_data;
   52 
   53 };
   54 
   55 /**
   56  * @brief Acquire and initialize and SPQ entry for a given ramrod.
   57  *
   58  * @param p_hwfn
   59  * @param pp_ent - will be filled with a pointer to an entry upon success
   60  * @param cmd - dependent upon protocol
   61  * @param protocol
   62  * @param p_data - various configuration required for ramrod
   63  *
   64  * @return ECORE_SUCCESS upon success, otherwise failure.
   65  */
   66 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
   67                                            struct ecore_spq_entry **pp_ent,
   68                                            u8 cmd,
   69                                            u8 protocol,
   70                                            struct ecore_sp_init_data *p_data);
   71 
   72 /**
   73  * @brief ecore_sp_pf_start - PF Function Start Ramrod
   74  *
   75  * This ramrod is sent to initialize a physical function (PF). It will
   76  * configure the function related parameters and write its completion to the
   77  * event ring specified in the parameters.
   78  *
   79  * Ramrods complete on the common event ring for the PF. This ring is
   80  * allocated by the driver on host memory and its parameters are written
   81  * to the internal RAM of the UStorm by the Function Start Ramrod.
   82  *
   83  * @param p_hwfn
   84  * @param p_ptt
   85  * @param p_tunn - pf start tunneling configuration
   86  * @param allow_npar_tx_switch - npar tx switching to be used
   87  *        for vports configured for tx-switching.
   88  *
   89  * @return enum _ecore_status_t
   90  */
   91 
   92 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
   93                                        struct ecore_ptt *p_ptt,
   94                                        struct ecore_tunnel_info *p_tunn,
   95                                        bool allow_npar_tx_switch);
   96 
   97 /**
   98  * @brief ecore_sp_pf_update - PF Function Update Ramrod
   99  *
  100  * This ramrod updates function-related parameters. Every parameter can be
  101  * updated independently, according to configuration flags.
  102  *
  103  * @note Final phase API.
  104  *
  105  * @param p_hwfn
  106  *
  107  * @return enum _ecore_status_t
  108  */
  109 
  110 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn);
  111 
  112 /**
  113  * @brief ecore_sp_pf_stop - PF Function Stop Ramrod
  114  *
  115  * This ramrod is sent to close a Physical Function (PF). It is the last ramrod
  116  * sent and the last completion written to the PFs Event Ring. This ramrod also
  117  * deletes the context for the Slowhwfn connection on this PF.
  118  *
  119  * @note Not required for first packet.
  120  *
  121  * @param p_hwfn
  122  *
  123  * @return enum _ecore_status_t
  124  */
  125 
  126 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn);
  127 
  128 /**
  129  * @brief ecore_sp_heartbeat_ramrod - Send empty Ramrod
  130  *
  131  * @param p_hwfn
  132  *
  133  * @return enum _ecore_status_t
  134  */
  135 
  136 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn);
  137 
  138 struct ecore_rl_update_params {
  139         u8 qcn_update_param_flg;
  140         u8 dcqcn_update_param_flg;
  141         u8 rl_init_flg;
  142         u8 rl_start_flg;
  143         u8 rl_stop_flg;
  144         u8 rl_id_first;
  145         u8 rl_id_last;
  146         u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */
  147         u32 rl_bc_rate; /* Byte Counter Limit */
  148         u32 rl_max_rate; /* Maximum rate in Mbps resolution */
  149         u32 rl_r_ai; /* Active increase rate */
  150         u32 rl_r_hai; /* Hyper active increase rate */
  151         u32 dcqcn_gd; /* DCQCN Alpha update gain */
  152         u32 dcqcn_k_us; /* DCQCN Alpha update interval */
  153         u32 dcqcn_timeuot_us;
  154         u32 qcn_timeuot_us;
  155 };
  156 
  157 /**
  158  * @brief ecore_sp_rl_update - Update rate limiters
  159  *
  160  * @param p_hwfn
  161  * @param params
  162  *
  163  * @return enum _ecore_status_t
  164  */
  165 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
  166                                         struct ecore_rl_update_params *params);
  167 
  168 /**
  169  * @brief ecore_sp_pf_update_stag - PF STAG value update Ramrod
  170  *
  171  * @param p_hwfn
  172  *
  173  * @return enum _ecore_status_t
  174  */
  175 
  176 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn);
  177 
  178 /**
  179  * @brief ecore_sp_pf_update_ufp - PF ufp update Ramrod
  180  *
  181  * @param p_hwfn
  182  *
  183  * @return enum _ecore_status_t
  184  */
  185 enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn);
  186 
  187 #endif /*__ECORE_SP_COMMANDS_H__*/

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