Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/qlnx/qlnxe/nvm_cfg.h
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1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 /**************************************************************************** 32 * 33 * Name: nvm_cfg.h 34 * 35 * Description: NVM config file - Generated file from nvm cfg excel. 36 * DO NOT MODIFY !!! 37 * 38 * Created: 12/4/2017 39 * 40 ****************************************************************************/ 41 42 #ifndef NVM_CFG_H 43 #define NVM_CFG_H 44 45 #define NVM_CFG_version 0x83306 46 47 #define NVM_CFG_new_option_seq 26 48 49 #define NVM_CFG_removed_option_seq 2 50 51 #define NVM_CFG_updated_value_seq 5 52 53 struct nvm_cfg_mac_address 54 { 55 u32 mac_addr_hi; 56 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 57 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 58 u32 mac_addr_lo; 59 }; 60 61 /****************************************** 62 * nvm_cfg1 structs 63 ******************************************/ 64 struct nvm_cfg1_glob 65 { 66 u32 generic_cont0; /* 0x0 */ 67 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F 68 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 69 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 70 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 71 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 72 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 73 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 74 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 75 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 76 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 77 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 78 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 79 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 80 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 81 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 82 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 83 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 84 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 85 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 86 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 87 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 88 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 89 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 90 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 91 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 92 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 93 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 94 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 95 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 96 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 97 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 98 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 99 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000 100 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 101 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0 102 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 103 u32 engineering_change[3]; /* 0x4 */ 104 u32 manufacturing_id; /* 0x10 */ 105 u32 serial_number[4]; /* 0x14 */ 106 u32 pcie_cfg; /* 0x24 */ 107 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 108 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 109 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 110 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 111 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 112 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 113 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 114 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 115 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 116 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 117 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 118 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 119 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 120 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 121 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 122 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 123 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 124 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 125 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 126 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 127 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 128 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 129 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 130 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 131 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 132 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 133 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 134 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 135 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 136 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 137 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 138 /* Set the duration, in seconds, fan failure signal should be 139 sampled */ 140 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 141 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 142 u32 mgmt_traffic; /* 0x28 */ 143 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 144 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 145 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE 146 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 147 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 148 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 149 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 150 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 151 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 152 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 153 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 154 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 155 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 156 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 157 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 158 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 159 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 160 /* Indicates whether external thermal sonsor is available */ 161 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 162 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 163 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 164 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 165 u32 core_cfg; /* 0x2C */ 166 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 167 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 168 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 169 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 170 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 171 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 172 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 173 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 174 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 175 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 176 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 177 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 178 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 179 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 180 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 181 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 182 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 183 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 184 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 185 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 186 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 187 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 188 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 189 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 190 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 191 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 192 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 193 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 194 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 195 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 196 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 197 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 198 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 199 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 200 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 201 #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000 202 #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31 203 #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0 204 #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1 205 u32 e_lane_cfg1; /* 0x30 */ 206 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 207 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 208 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 209 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 210 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 211 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 212 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 213 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 214 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 215 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 216 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 217 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 218 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 219 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 220 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 221 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 222 u32 e_lane_cfg2; /* 0x34 */ 223 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 224 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 225 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 226 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 227 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 228 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 229 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 230 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 231 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 232 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 233 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 234 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 235 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 236 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 237 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 238 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 239 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 240 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 241 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 242 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 243 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 244 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 245 #define NVM_CFG1_GLOB_NCSI_OFFSET 12 246 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 247 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 248 /* Maximum advertised pcie link width */ 249 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 250 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 251 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 252 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 253 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 254 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 255 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 256 /* ASPM L1 mode */ 257 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 258 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 259 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 260 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 261 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 262 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 263 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 264 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 265 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 266 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 267 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 268 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 269 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 270 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 271 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 272 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 273 /* Set the PLDM sensor modes */ 274 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 275 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 276 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 277 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 278 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 279 /* Enable VDM interface */ 280 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000 281 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30 282 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0 283 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1 284 /* ROL enable */ 285 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 286 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 287 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 288 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 289 u32 f_lane_cfg1; /* 0x38 */ 290 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 291 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 292 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 293 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 294 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 295 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 296 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 297 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 298 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 299 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 300 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 301 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 302 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 303 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 304 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 305 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 306 u32 f_lane_cfg2; /* 0x3C */ 307 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 308 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 309 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 310 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 311 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 312 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 313 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 314 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 315 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 316 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 317 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 318 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 319 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 320 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 321 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 322 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 323 /* Control the period between two successive checks */ 324 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 325 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 326 /* Set shutdown temperature */ 327 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 328 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 329 /* Set max. count for over operational temperature */ 330 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 331 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 332 u32 mps10_preemphasis; /* 0x40 */ 333 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 334 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 335 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 336 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 337 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 338 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 339 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 340 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 341 u32 mps10_driver_current; /* 0x44 */ 342 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 343 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 344 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 345 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 346 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 347 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 348 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 349 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 350 u32 mps25_preemphasis; /* 0x48 */ 351 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 352 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 353 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 354 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 355 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 356 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 357 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 358 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 359 u32 mps25_driver_current; /* 0x4C */ 360 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 361 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 362 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 363 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 364 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 365 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 366 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 367 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 368 u32 pci_id; /* 0x50 */ 369 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF 370 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 371 /* Set caution temperature */ 372 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK 0x00FF0000 373 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_OFFSET 16 374 /* Set external thermal sensor I2C address */ 375 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 376 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 377 u32 pci_subsys_id; /* 0x54 */ 378 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF 379 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 380 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 381 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 382 u32 bar; /* 0x58 */ 383 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F 384 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 385 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 386 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 387 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 388 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 389 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 390 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 391 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 392 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 393 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 394 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 395 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA 396 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB 397 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC 398 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD 399 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE 400 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF 401 /* BB VF BAR2 size */ 402 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 403 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 404 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 405 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 406 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 407 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 408 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 409 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 410 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 411 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 412 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 413 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 414 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA 415 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB 416 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC 417 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD 418 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE 419 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF 420 /* BB BAR2 size (global) */ 421 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 422 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 423 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 424 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 425 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 426 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 427 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 428 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 429 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 430 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 431 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 432 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 433 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA 434 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB 435 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC 436 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD 437 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE 438 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF 439 /* Set the duration, in seconds, fan failure signal should be 440 sampled */ 441 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 442 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 443 /* This field defines the board total budget for bar2 when disabled 444 the regular bar size is used. */ 445 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 446 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 447 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 448 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 449 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 450 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 451 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 452 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 453 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 454 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 455 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 456 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 457 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA 458 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB 459 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC 460 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD 461 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE 462 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF 463 /* Enable/Disable Crash dump triggers */ 464 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 465 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 466 u32 mps10_txfir_main; /* 0x5C */ 467 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 468 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 469 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 470 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 471 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 472 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 473 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 474 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 475 u32 mps10_txfir_post; /* 0x60 */ 476 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 477 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 478 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 479 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 480 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 481 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 482 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 483 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 484 u32 mps25_txfir_main; /* 0x64 */ 485 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 486 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 487 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 488 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 489 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 490 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 491 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 492 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 493 u32 mps25_txfir_post; /* 0x68 */ 494 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 495 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 496 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 497 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 498 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 499 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 500 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 501 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 502 u32 manufacture_ver; /* 0x6C */ 503 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F 504 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 505 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 506 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 507 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 508 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 509 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 510 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 511 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 512 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 513 /* Select package id method */ 514 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 515 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 516 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 517 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 518 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 519 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 520 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 521 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 522 u32 manufacture_time; /* 0x70 */ 523 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F 524 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 525 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 526 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 527 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 528 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 529 /* Max MSIX for Ethernet in default mode */ 530 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 531 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 532 /* PF Mapping */ 533 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 534 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 535 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 536 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 537 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 538 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 539 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 540 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 541 /* Enable/Disable PCIE Relaxed Ordering */ 542 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_MASK 0x40000000 543 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_OFFSET 30 544 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_DISABLED 0x0 545 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_ENABLED 0x1 546 u32 led_global_settings; /* 0x74 */ 547 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F 548 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 549 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 550 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 551 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 552 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 553 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 554 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 555 /* Max. continues operating temperature */ 556 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 557 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 558 /* GPIO which triggers run-time port swap according to the map 559 specified in option 205 */ 560 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 561 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 565 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 566 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 567 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 568 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 569 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 570 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 571 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 572 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA 573 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB 574 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC 575 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD 576 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE 577 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF 578 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 579 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 580 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 581 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 582 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 583 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 584 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 585 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 586 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 587 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 588 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A 589 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B 590 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C 591 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D 592 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E 593 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F 594 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 595 u32 generic_cont1; /* 0x78 */ 596 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF 597 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 598 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 599 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 600 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 601 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 602 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 603 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 604 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 605 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 606 /* Enable option 195 - Overriding the PCIe Preset value */ 607 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 608 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 609 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 610 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 611 /* PCIe Preset value - applies only if option 194 is enabled */ 612 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 613 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 614 /* Port mapping to be used when the run-time GPIO for port-swap is 615 defined and set. */ 616 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 617 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 618 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 619 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 620 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 621 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 622 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 623 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 624 u32 mbi_version; /* 0x7C */ 625 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 626 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 627 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 628 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 629 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 630 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 631 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event 632 occurred */ 633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 640 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 641 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 642 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 643 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 644 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 645 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA 646 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB 647 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC 648 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD 649 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE 650 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF 651 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 652 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 653 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 654 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 655 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 656 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 657 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 658 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 659 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 660 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 661 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A 662 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B 663 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C 664 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D 665 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E 666 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F 667 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 668 u32 mbi_date; /* 0x80 */ 669 u32 misc_sig; /* 0x84 */ 670 /* Define the GPIO mapping to switch i2c mux */ 671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF 672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 680 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 681 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 682 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 683 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 684 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 685 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA 686 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB 687 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC 688 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD 689 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE 690 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF 691 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 692 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 693 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 694 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 695 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 696 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 697 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 698 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 699 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 700 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 701 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A 702 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B 703 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C 704 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D 705 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E 706 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F 707 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 708 /* Interrupt signal used for SMBus/I2C management interface 709 710 0 = Interrupt event occurred 711 1 = Normal 712 */ 713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 714 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 719 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 720 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 721 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 722 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 723 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 724 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 725 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA 726 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB 727 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC 728 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD 729 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE 730 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF 731 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 732 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 733 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 734 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 735 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 736 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 737 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 738 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 739 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 740 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 741 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A 742 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B 743 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C 744 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D 745 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E 746 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F 747 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 748 /* Set aLOM FAN on GPIO */ 749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 750 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 755 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 756 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 757 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 758 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 759 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 760 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 761 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA 762 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB 763 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC 764 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD 765 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE 766 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF 767 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 768 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 769 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 770 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 771 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 772 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 773 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 774 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 775 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 776 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 777 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A 778 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B 779 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C 780 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D 781 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E 782 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F 783 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 784 u32 device_capabilities; /* 0x88 */ 785 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 786 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 787 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 788 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 789 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 790 u32 power_dissipated; /* 0x8C */ 791 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF 792 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 793 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 794 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 795 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 796 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 797 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 798 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 799 u32 power_consumed; /* 0x90 */ 800 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF 801 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 802 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 803 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 804 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 805 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 806 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 807 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 808 u32 efi_version; /* 0x94 */ 809 u32 multi_network_modes_capability; /* 0x98 */ 810 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 811 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 812 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 813 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 814 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 815 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 816 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 817 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80 818 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 819 u32 nvm_cfg_version; /* 0x9C */ 820 u32 nvm_cfg_new_option_seq; /* 0xA0 */ 821 u32 nvm_cfg_removed_option_seq; /* 0xA4 */ 822 u32 nvm_cfg_updated_value_seq; /* 0xA8 */ 823 u32 extended_serial_number[8]; /* 0xAC */ 824 u32 oem1_number[8]; /* 0xCC */ 825 u32 oem2_number[8]; /* 0xEC */ 826 u32 mps25_active_txfir_pre; /* 0x10C */ 827 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF 828 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 829 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 830 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 831 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 832 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 833 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 834 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 835 u32 mps25_active_txfir_main; /* 0x110 */ 836 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF 837 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 838 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 839 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 840 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 841 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 842 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 843 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 844 u32 mps25_active_txfir_post; /* 0x114 */ 845 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF 846 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 847 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 848 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 849 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 850 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 851 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 852 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 853 u32 features; /* 0x118 */ 854 /* Set the Aux Fan on temperature */ 855 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF 856 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 857 /* Set NC-SI package ID */ 858 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 859 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 862 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 863 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 864 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 865 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 866 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 867 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 868 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 869 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 870 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA 871 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB 872 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC 873 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD 874 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE 875 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF 876 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 877 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 878 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 879 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 880 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 881 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 882 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 883 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 884 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 885 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 886 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A 887 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B 888 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C 889 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D 890 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E 891 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F 892 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 893 /* PMBUS Clock GPIO */ 894 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 895 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 898 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 899 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 900 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 901 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 902 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 903 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 904 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 905 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 906 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA 907 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB 908 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC 909 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD 910 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE 911 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF 912 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 913 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 914 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 915 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 916 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 917 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 918 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 919 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 920 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 921 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 922 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A 923 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B 924 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C 925 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D 926 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E 927 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F 928 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 929 /* PMBUS Data GPIO */ 930 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 931 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 934 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 935 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 936 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 937 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 938 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 939 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 940 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 941 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 942 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA 943 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB 944 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC 945 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD 946 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE 947 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF 948 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 949 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 950 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 951 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 952 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 953 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 954 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 955 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 956 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 957 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 958 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A 959 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B 960 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C 961 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D 962 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E 963 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F 964 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 965 u32 tx_rx_eq_25g_hlpc; /* 0x11C */ 966 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF 967 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 968 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 969 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 970 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 971 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 972 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 973 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 974 u32 tx_rx_eq_25g_llpc; /* 0x120 */ 975 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF 976 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 977 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 978 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 979 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 980 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 981 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 982 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 983 u32 tx_rx_eq_25g_ac; /* 0x124 */ 984 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF 985 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 986 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 987 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 988 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 989 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 990 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 991 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 992 u32 tx_rx_eq_10g_pc; /* 0x128 */ 993 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF 994 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 995 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 996 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 997 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 998 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 999 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 1000 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 1001 u32 tx_rx_eq_10g_ac; /* 0x12C */ 1002 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF 1003 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 1004 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 1005 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 1006 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 1007 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 1008 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 1009 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 1010 u32 tx_rx_eq_1g; /* 0x130 */ 1011 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF 1012 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 1013 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 1014 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 1015 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 1016 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 1017 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 1018 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 1019 u32 tx_rx_eq_25g_bt; /* 0x134 */ 1020 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF 1021 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 1022 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 1023 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 1024 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 1025 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 1026 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 1027 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 1028 u32 tx_rx_eq_10g_bt; /* 0x138 */ 1029 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF 1030 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 1031 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 1032 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 1033 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 1034 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 1035 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 1036 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 1037 u32 generic_cont4; /* 0x13C */ 1038 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF 1039 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 1042 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 1043 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 1044 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 1045 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 1046 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 1047 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 1048 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 1049 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 1050 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA 1051 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB 1052 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC 1053 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD 1054 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE 1055 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF 1056 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 1057 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 1058 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 1059 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 1060 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 1061 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 1062 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 1063 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 1064 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 1065 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 1066 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A 1067 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B 1068 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C 1069 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D 1070 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E 1071 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F 1072 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 1073 u32 preboot_debug_mode_std; /* 0x140 */ 1074 u32 preboot_debug_mode_ext; /* 0x144 */ 1075 u32 ext_phy_cfg1; /* 0x148 */ 1076 /* Ext PHY MDI pair swap value */ 1077 #define NVM_CFG1_GLOB_RESERVED_244_MASK 0x0000FFFF 1078 #define NVM_CFG1_GLOB_RESERVED_244_OFFSET 0 1079 u32 clocks; /* 0x14C */ 1080 /* Sets core clock frequency */ 1081 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK 0x000000FF 1082 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET 0 1083 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT 0x0 1084 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375 0x1 1085 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350 0x2 1086 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325 0x3 1087 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300 0x4 1088 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280 0x5 1089 /* Sets MAC clock frequency */ 1090 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK 0x0000FF00 1091 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_OFFSET 8 1092 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT 0x0 1093 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782 0x1 1094 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516 0x2 1095 /* Sets storm clock frequency */ 1096 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK 0x00FF0000 1097 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_OFFSET 16 1098 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT 0x0 1099 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200 0x1 1100 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000 0x2 1101 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900 0x3 1102 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100 0x4 1103 u32 reserved[54]; /* 0x150 */ 1104 }; 1105 1106 struct nvm_cfg1_path 1107 { 1108 u32 reserved[1]; /* 0x0 */ 1109 }; 1110 1111 struct nvm_cfg1_port 1112 { 1113 u32 reserved__m_relocated_to_option_123; /* 0x0 */ 1114 u32 reserved__m_relocated_to_option_124; /* 0x4 */ 1115 u32 generic_cont0; /* 0x8 */ 1116 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF 1117 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 1118 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 1119 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 1120 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 1121 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 1122 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 1123 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 1124 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 1125 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 1126 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 1127 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 1128 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA 1129 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB 1130 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC 1131 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD 1132 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE 1133 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF 1134 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 1135 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 1136 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 1137 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 1138 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 1139 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 1140 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 1141 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 1142 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 1143 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 1144 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 1145 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 1146 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 1147 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 1148 /* GPIO for HW reset the PHY. In case it is the same for all ports, 1149 need to set same value for all ports */ 1150 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 1151 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 1152 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 1153 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 1154 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 1155 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 1156 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 1157 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 1158 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 1159 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 1160 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 1161 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 1162 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA 1163 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB 1164 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC 1165 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD 1166 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE 1167 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF 1168 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 1169 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 1170 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 1171 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 1172 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 1173 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 1174 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 1175 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 1176 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 1177 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 1178 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A 1179 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B 1180 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C 1181 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D 1182 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E 1183 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F 1184 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 1185 u32 pcie_cfg; /* 0xC */ 1186 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 1187 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 1188 u32 features; /* 0x10 */ 1189 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 1190 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 1191 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 1192 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 1193 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 1194 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 1195 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 1196 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 1197 u32 speed_cap_mask; /* 0x14 */ 1198 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1199 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1200 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1201 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1202 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1203 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1204 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1205 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1206 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1207 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1208 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1209 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1210 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1211 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1212 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1213 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1214 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1215 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1216 u32 link_settings; /* 0x18 */ 1217 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 1218 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 1219 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 1220 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 1221 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 1222 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3 1223 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 1224 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 1225 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 1226 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 1227 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 1228 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 1229 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 1230 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 1231 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 1232 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 1233 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 1234 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 1235 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 1236 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 1237 #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3 1238 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 1239 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 1240 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 1241 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 1242 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 1243 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 1244 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 1245 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 1246 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 1247 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 1248 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 1249 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 1250 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 1251 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 1252 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 1253 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 1254 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 1255 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 1256 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 1257 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 1258 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 1259 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 1260 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 1261 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 1262 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 1263 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 1264 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 1265 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 1266 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 1267 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 1268 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 1269 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 1270 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 1271 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 1272 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 1273 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 1274 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 1275 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 1276 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 1277 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 1278 u32 phy_cfg; /* 0x1C */ 1279 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF 1280 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 1281 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 1282 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 1283 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 1284 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 1285 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 1286 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 1287 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 1288 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 1289 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 1290 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 1291 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 1292 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 1293 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 1294 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB 1295 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC 1296 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 1297 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 1298 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 1299 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 1300 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 1301 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 1302 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 1303 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 1304 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 1305 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 1306 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 1307 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 1308 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 1309 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 1310 u32 mgmt_traffic; /* 0x20 */ 1311 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F 1312 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 1313 u32 ext_phy; /* 0x24 */ 1314 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF 1315 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 1316 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 1317 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 1318 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2 1319 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 1320 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 1321 /* EEE power saving mode */ 1322 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 1323 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 1324 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 1325 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 1326 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 1327 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 1328 u32 mba_cfg1; /* 0x28 */ 1329 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 1330 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 1331 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 1332 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 1333 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 1334 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 1335 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 1336 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 1337 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 1338 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 1339 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 1340 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 1341 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 1342 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 1343 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 1344 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 1345 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 1346 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 1347 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 1348 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 1349 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 1350 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 1351 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 1352 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3 1353 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 1354 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 1355 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 1356 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 1357 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 1358 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 1359 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000 1360 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 1361 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0 1362 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 1363 u32 mba_cfg2; /* 0x2C */ 1364 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF 1365 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 1366 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 1367 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 1368 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 1369 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 1370 u32 vf_cfg; /* 0x30 */ 1371 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF 1372 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 1373 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 1374 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 1375 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ 1376 u32 led_port_settings; /* 0x3C */ 1377 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF 1378 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 1379 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 1380 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 1381 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 1382 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 1383 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 1384 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 1385 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 1386 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 1387 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 1388 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 1389 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 1390 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 1391 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 1392 /* UID LED Blink Mode Settings */ 1393 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_MASK 0x0F000000 1394 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_OFFSET 24 1395 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_ACTIVITY_LED 0x1 1396 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED0 0x2 1397 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED1 0x4 1398 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED2 0x8 1399 u32 transceiver_00; /* 0x40 */ 1400 /* Define for mapping of transceiver signal module absent */ 1401 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF 1402 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 1403 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 1404 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 1405 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 1406 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 1407 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 1408 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 1409 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 1410 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 1411 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 1412 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 1413 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA 1414 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB 1415 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC 1416 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD 1417 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE 1418 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF 1419 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 1420 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 1421 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 1422 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 1423 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 1424 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 1425 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 1426 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 1427 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 1428 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 1429 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A 1430 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B 1431 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C 1432 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D 1433 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E 1434 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F 1435 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 1436 /* Define the GPIO mux settings to switch i2c mux to this port */ 1437 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 1438 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 1439 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 1440 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 1441 u32 device_ids; /* 0x44 */ 1442 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF 1443 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 1444 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 1445 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 1446 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 1447 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 1448 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 1449 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 1450 u32 board_cfg; /* 0x48 */ 1451 /* This field defines the board technology 1452 (backpane,transceiver,external PHY) */ 1453 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 1454 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 1455 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 1456 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 1457 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 1458 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 1459 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 1460 /* This field defines the GPIO mapped to tx_disable signal in SFP */ 1461 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 1462 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 1463 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 1464 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 1465 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 1466 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 1467 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 1468 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 1469 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 1470 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 1471 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 1472 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 1473 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA 1474 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB 1475 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC 1476 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD 1477 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE 1478 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF 1479 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 1480 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 1481 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 1482 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 1483 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 1484 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 1485 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 1486 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 1487 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 1488 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 1489 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A 1490 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B 1491 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C 1492 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D 1493 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E 1494 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F 1495 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 1496 u32 mnm_10g_cap; /* 0x4C */ 1497 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1498 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1499 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1500 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1501 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1502 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1503 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1504 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1505 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1506 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1507 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1508 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1509 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1510 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1511 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1512 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1513 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1514 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1515 u32 mnm_10g_ctrl; /* 0x50 */ 1516 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F 1517 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 1518 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 1519 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 1520 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 1521 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3 1522 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 1523 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 1524 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 1525 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 1526 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 1527 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 1528 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 1529 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 1530 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 1531 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3 1532 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 1533 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 1534 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 1535 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 1536 /* This field defines the board technology 1537 (backpane,transceiver,external PHY) */ 1538 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 1539 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 1540 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 1541 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 1542 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 1543 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 1544 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 1545 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1546 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 1547 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 1548 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 1549 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 1550 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 1551 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 1552 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 1553 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB 1554 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC 1555 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 1556 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 1557 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 1558 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 1559 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 1560 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 1561 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 1562 u32 mnm_10g_misc; /* 0x54 */ 1563 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 1564 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 1565 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 1566 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 1567 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 1568 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 1569 u32 mnm_25g_cap; /* 0x58 */ 1570 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1571 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1572 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1573 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1574 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1575 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1576 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1577 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1578 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1579 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1580 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1581 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1582 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1583 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1584 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1585 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1586 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1587 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1588 u32 mnm_25g_ctrl; /* 0x5C */ 1589 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F 1590 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 1591 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 1592 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 1593 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 1594 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3 1595 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 1596 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 1597 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 1598 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 1599 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 1600 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 1601 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 1602 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 1603 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 1604 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3 1605 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 1606 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 1607 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 1608 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 1609 /* This field defines the board technology 1610 (backpane,transceiver,external PHY) */ 1611 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 1612 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 1613 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 1614 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 1615 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 1616 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 1617 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 1618 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1619 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 1620 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 1621 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 1622 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 1623 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 1624 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 1625 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 1626 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB 1627 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC 1628 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 1629 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 1630 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 1631 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 1632 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 1633 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 1634 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 1635 u32 mnm_25g_misc; /* 0x60 */ 1636 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 1637 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 1638 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 1639 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 1640 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 1641 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 1642 u32 mnm_40g_cap; /* 0x64 */ 1643 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1644 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1645 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1646 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1647 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1648 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1649 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1650 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1651 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1652 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1653 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1654 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1655 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1656 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1657 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1658 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1659 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1660 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1661 u32 mnm_40g_ctrl; /* 0x68 */ 1662 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F 1663 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 1664 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 1665 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 1666 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 1667 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3 1668 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 1669 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 1670 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 1671 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 1672 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 1673 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 1674 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 1675 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 1676 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 1677 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3 1678 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 1679 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 1680 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 1681 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 1682 /* This field defines the board technology 1683 (backpane,transceiver,external PHY) */ 1684 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 1685 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 1686 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 1687 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 1688 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 1689 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 1690 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 1691 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1692 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 1693 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 1694 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 1695 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 1696 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 1697 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 1698 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 1699 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB 1700 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC 1701 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 1702 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 1703 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 1704 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 1705 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 1706 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 1707 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 1708 u32 mnm_40g_misc; /* 0x6C */ 1709 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 1710 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 1711 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 1712 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 1713 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 1714 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 1715 u32 mnm_50g_cap; /* 0x70 */ 1716 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1717 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1718 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1719 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1720 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1721 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1722 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1723 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1724 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1725 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1726 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1727 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1728 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1729 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1730 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1731 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1732 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1733 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1734 u32 mnm_50g_ctrl; /* 0x74 */ 1735 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F 1736 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 1737 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 1738 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 1739 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 1740 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3 1741 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 1742 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 1743 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 1744 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 1745 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 1746 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 1747 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 1748 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 1749 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 1750 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3 1751 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 1752 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 1753 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 1754 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 1755 /* This field defines the board technology 1756 (backpane,transceiver,external PHY) */ 1757 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 1758 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 1759 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 1760 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 1761 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 1762 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 1763 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 1764 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1765 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 1766 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 1767 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 1768 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 1769 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 1770 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 1771 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 1772 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB 1773 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC 1774 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 1775 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 1776 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 1777 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 1778 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 1779 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 1780 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 1781 u32 mnm_50g_misc; /* 0x78 */ 1782 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 1783 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 1784 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 1785 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 1786 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 1787 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 1788 u32 mnm_100g_cap; /* 0x7C */ 1789 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF 1790 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 1791 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 1792 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 1793 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4 1794 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 1795 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 1796 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 1797 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 1798 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000 1799 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 1800 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 1801 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 1802 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4 1803 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 1804 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 1805 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 1806 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 1807 u32 mnm_100g_ctrl; /* 0x80 */ 1808 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F 1809 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 1810 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 1811 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 1812 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 1813 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3 1814 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 1815 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 1816 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 1817 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 1818 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 1819 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 1820 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 1821 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 1822 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 1823 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3 1824 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 1825 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 1826 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 1827 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 1828 /* This field defines the board technology 1829 (backpane,transceiver,external PHY) */ 1830 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 1831 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 1832 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 1833 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 1834 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 1835 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 1836 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 1837 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1838 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 1839 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 1840 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 1841 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 1842 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 1843 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 1844 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 1845 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB 1846 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC 1847 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 1848 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 1849 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 1850 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 1851 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 1852 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 1853 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 1854 u32 mnm_100g_misc; /* 0x84 */ 1855 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 1856 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 1857 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 1858 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 1859 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 1860 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 1861 u32 temperature; /* 0x88 */ 1862 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF 1863 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 1864 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00 1865 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 1866 u32 ext_phy_cfg1; /* 0x8C */ 1867 /* Ext PHY MDI pair swap value */ 1868 #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF 1869 #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0 1870 u32 reserved[114]; /* 0x90 */ 1871 }; 1872 1873 struct nvm_cfg1_func 1874 { 1875 struct nvm_cfg_mac_address mac_address; /* 0x0 */ 1876 u32 rsrv1; /* 0x8 */ 1877 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF 1878 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 1879 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 1880 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 1881 u32 rsrv2; /* 0xC */ 1882 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF 1883 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 1884 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 1885 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 1886 u32 device_id; /* 0x10 */ 1887 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF 1888 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 1889 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 1890 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 1891 u32 cmn_cfg; /* 0x14 */ 1892 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 1893 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 1894 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 1895 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 1896 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 1897 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 1898 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 1899 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 1900 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 1901 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 1902 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 1903 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 1904 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 1905 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 1906 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 1907 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 1908 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 1909 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 1910 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 1911 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 1912 u32 pci_cfg; /* 0x18 */ 1913 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F 1914 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 1915 /* AH VF BAR2 size */ 1916 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 1917 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 1918 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 1919 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 1920 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 1921 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 1922 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 1923 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 1924 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 1925 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 1926 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 1927 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 1928 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA 1929 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB 1930 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC 1931 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD 1932 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE 1933 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF 1934 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 1935 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 1936 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 1937 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 1938 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 1939 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 1940 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 1941 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 1942 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 1943 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 1944 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 1945 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 1946 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA 1947 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB 1948 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC 1949 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD 1950 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE 1951 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF 1952 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 1953 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 1954 /* Hide function in npar mode */ 1955 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 1956 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 1957 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 1958 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 1959 /* AH BAR2 size (per function) */ 1960 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 1961 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 1962 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 1963 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 1964 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 1965 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 1966 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 1967 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 1968 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA 1969 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB 1970 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC 1971 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD 1972 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE 1973 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF 1974 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ 1975 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ 1976 u32 preboot_generic_cfg; /* 0x2C */ 1977 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF 1978 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 1979 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 1980 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 1981 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 1982 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 1983 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 1984 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 1985 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 1986 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 1987 u32 features; /* 0x30 */ 1988 /* RDMA protocol enablement */ 1989 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003 1990 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0 1991 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0 1992 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1 1993 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2 1994 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3 1995 u32 reserved[7]; /* 0x34 */ 1996 }; 1997 1998 struct nvm_cfg1 1999 { 2000 struct nvm_cfg1_glob glob; /* 0x0 */ 2001 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ 2002 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ 2003 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ 2004 }; 2005 2006 /****************************************** 2007 * nvm_cfg structs 2008 ******************************************/ 2009 2010 struct board_info 2011 { 2012 u16 vendor_id; 2013 u16 eth_did_suffix; 2014 u16 sub_vendor_id; 2015 u16 sub_device_id; 2016 char *board_name; 2017 char *friendly_name; 2018 }; 2019 2020 enum nvm_cfg_sections 2021 { 2022 NVM_CFG_SECTION_NVM_CFG1, 2023 NVM_CFG_SECTION_MAX 2024 }; 2025 2026 struct nvm_cfg 2027 { 2028 u32 num_sections; 2029 u32 sections_offset[NVM_CFG_SECTION_MAX]; 2030 struct nvm_cfg1 cfg1; 2031 }; 2032 2033 #endif /* NVM_CFG_H */
Cache object: c1c4a6d06aa24f40486aa9a227db926e
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