nvm_map.h

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    1 /*
    2  * Copyright (c) 2017-2018 Cavium, Inc. 
    3  * All rights reserved.
    4  *
    5  *  Redistribution and use in source and binary forms, with or without
    6  *  modification, are permitted provided that the following conditions
    7  *  are met:
    8  *
    9  *  1. Redistributions of source code must retain the above copyright
   10  *     notice, this list of conditions and the following disclaimer.
   11  *  2. Redistributions in binary form must reproduce the above copyright
   12  *     notice, this list of conditions and the following disclaimer in the
   13  *     documentation and/or other materials provided with the distribution.
   14  *
   15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   25  *  POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  *
   29  */
   30 
   31 /****************************************************************************
   32  * Name:        nvm_map.h
   33  *
   34  * Description: Everest NVRAM map
   35  *
   36  ****************************************************************************/
   37 
   38 #ifndef NVM_MAP_H
   39 #define NVM_MAP_H
   40 
   41 #define CRC_MAGIC_VALUE                     0xDEBB20E3
   42 #define CRC32_POLYNOMIAL                    0xEDB88320
   43 #define _KB(x) (x*1024)
   44 #define _MB(x) (_KB(x)*1024)
   45 #define NVM_CRC_SIZE                            (sizeof(u32))
   46 enum nvm_sw_arbitrator {
   47         NVM_SW_ARB_HOST,
   48         NVM_SW_ARB_MCP,
   49         NVM_SW_ARB_UART,
   50         NVM_SW_ARB_RESERVED
   51 };
   52 
   53 /****************************************************************************
   54  * Boot Strap Region                                                        *
   55  ****************************************************************************/
   56 struct legacy_bootstrap_region {
   57         u32 magic_value;        /* a pattern not likely to occur randomly */
   58 #define NVM_MAGIC_VALUE          0x669955aa
   59         u32 sram_start_addr;    /* where to locate LIM code (byte addr) */
   60         u32 code_len;           /* boot code length (in dwords) */
   61         u32 code_start_addr;    /* location of code on media (media byte addr) */
   62         u32 crc;                /* 32-bit CRC */
   63 };
   64 
   65 /****************************************************************************
   66  * Directories Region                                                       *
   67  ****************************************************************************/
   68 struct nvm_code_entry {
   69         u32 image_type;         /* Image type */
   70         u32 nvm_start_addr;     /* NVM address of the image */
   71         u32 len;                /* Include CRC */
   72         u32 sram_start_addr;    /* Where to load the image on the scratchpad */
   73         u32 sram_run_addr;      /* Relevant in case of MIM only */
   74 };
   75 
   76 enum nvm_image_type {
   77         NVM_TYPE_TIM1       = 0x01,
   78         NVM_TYPE_TIM2       = 0x02,
   79         NVM_TYPE_MIM1       = 0x03,
   80         NVM_TYPE_MIM2       = 0x04,
   81         NVM_TYPE_MBA        = 0x05,
   82         NVM_TYPE_MODULES_PN = 0x06,
   83         NVM_TYPE_VPD        = 0x07,
   84         NVM_TYPE_MFW_TRACE1 = 0x08,
   85         NVM_TYPE_MFW_TRACE2 = 0x09,
   86         NVM_TYPE_NVM_CFG1   = 0x0a,
   87         NVM_TYPE_L2B        = 0x0b,
   88         NVM_TYPE_DIR1       = 0x0c,
   89         NVM_TYPE_EAGLE_FW1  = 0x0d,
   90         NVM_TYPE_FALCON_FW1 = 0x0e,
   91         NVM_TYPE_PCIE_FW1   = 0x0f,
   92         NVM_TYPE_HW_SET     = 0x10,
   93         NVM_TYPE_LIM        = 0x11,
   94         NVM_TYPE_AVS_FW1    = 0x12,
   95         NVM_TYPE_DIR2       = 0x13,
   96         NVM_TYPE_CCM        = 0x14,
   97         NVM_TYPE_EAGLE_FW2  = 0x15,
   98         NVM_TYPE_FALCON_FW2 = 0x16,
   99         NVM_TYPE_PCIE_FW2   = 0x17,
  100         NVM_TYPE_AVS_FW2    = 0x18,
  101         NVM_TYPE_INIT_HW    = 0x19,
  102         NVM_TYPE_DEFAULT_CFG= 0x1a,
  103         NVM_TYPE_MDUMP      = 0x1b,
  104         NVM_TYPE_NVM_META   = 0x1c,
  105         NVM_TYPE_ISCSI_CFG  = 0x1d,
  106         NVM_TYPE_FCOE_CFG   = 0x1f,
  107         NVM_TYPE_ETH_PHY_FW1 = 0x20,
  108         NVM_TYPE_ETH_PHY_FW2 = 0x21,
  109         NVM_TYPE_BDN        = 0x22,
  110         NVM_TYPE_8485X_PHY_FW = 0x23,
  111         NVM_TYPE_PUB_KEY    = 0x24,
  112         NVM_TYPE_RECOVERY   = 0x25,
  113         NVM_TYPE_PLDM       = 0x26,
  114         NVM_TYPE_UPK1       = 0x27,
  115         NVM_TYPE_UPK2       = 0x28,
  116         NVM_TYPE_MASTER_KC  = 0x29,
  117         NVM_TYPE_BACKUP_KC  = 0x2a,
  118         NVM_TYPE_ROM_TEST   = 0xf0,
  119         NVM_TYPE_MAX,
  120 };
  121 
  122 #ifdef DEFINE_IMAGE_TABLE
  123 struct image_map {
  124         char name[32];
  125         char option[32];
  126         u32 image_type;
  127 };
  128 
  129 struct image_map g_image_table[] = {
  130         {"TIM1",        "-tim1",    NVM_TYPE_TIM1},
  131         {"TIM2",        "-tim2",    NVM_TYPE_TIM2},
  132         {"MIM1",        "-mim1",    NVM_TYPE_MIM1},
  133         {"MIM2",        "-mim2",    NVM_TYPE_MIM2},
  134         {"MBA",         "-mba",     NVM_TYPE_MBA},
  135         {"OPT_MODULES", "-optm",    NVM_TYPE_MODULES_PN},
  136         {"VPD",         "-vpd",     NVM_TYPE_VPD},
  137         {"MFW_TRACE1",  "-mfwt1",   NVM_TYPE_MFW_TRACE1},
  138         {"MFW_TRACE2",  "-mfwt2",   NVM_TYPE_MFW_TRACE2},
  139         {"NVM_CFG1",    "-cfg",     NVM_TYPE_NVM_CFG1},
  140         {"L2B",         "-l2b",     NVM_TYPE_L2B},
  141         {"DIR1",        "-dir1",    NVM_TYPE_DIR1},
  142         {"EAGLE_FW1",   "-eagle1",  NVM_TYPE_EAGLE_FW1},
  143         {"FALCON_FW1",  "-falcon1", NVM_TYPE_FALCON_FW1},
  144         {"PCIE_FW1",    "-pcie1",   NVM_TYPE_PCIE_FW1},
  145         {"HW_SET",      "-hw_set",  NVM_TYPE_HW_SET},
  146         {"LIM",         "-lim",     NVM_TYPE_LIM},
  147         {"AVS_FW1",     "-avs1",    NVM_TYPE_AVS_FW1},
  148         {"DIR2",        "-dir2",    NVM_TYPE_DIR2},
  149         {"CCM",         "-ccm",     NVM_TYPE_CCM},
  150         {"EAGLE_FW2",   "-eagle2",  NVM_TYPE_EAGLE_FW2},
  151         {"FALCON_FW2",  "-falcon2", NVM_TYPE_FALCON_FW2},
  152         {"PCIE_FW2",    "-pcie2",   NVM_TYPE_PCIE_FW2},
  153         {"AVS_FW2",     "-avs2",    NVM_TYPE_AVS_FW2},
  154         {"INIT_HW",     "-init_hw", NVM_TYPE_INIT_HW},
  155         {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG},
  156         {"CRASH_DUMP",  "-mdump",   NVM_TYPE_MDUMP},
  157         {"META",            "-meta",    NVM_TYPE_NVM_META},
  158         {"ISCSI_CFG",   "-iscsi_cfg", NVM_TYPE_ISCSI_CFG},
  159         {"FCOE_CFG",    "-fcoe_cfg",NVM_TYPE_FCOE_CFG},
  160         {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1},
  161         {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2},
  162         {"BDN",         "-bdn",     NVM_TYPE_BDN},
  163         {"PK",          "-pk",      NVM_TYPE_PUB_KEY},
  164         {"RECOVERY",    "-recovery",NVM_TYPE_RECOVERY},
  165         {"PLDM",        "-pldm",    NVM_TYPE_PLDM},
  166         {"UPK1",        "-upk1",    NVM_TYPE_UPK1},
  167         {"UPK2",        "-upk2",    NVM_TYPE_UPK2},
  168         {"ROMTEST",     "-romtest" ,NVM_TYPE_ROM_TEST},
  169         {"MASTER_KC",   "-kc"      ,NVM_TYPE_MASTER_KC},
  170         {"BACKUP_KC",   ""         ,NVM_TYPE_BACKUP_KC}
  171 };
  172 
  173 #define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map))
  174 
  175 #endif  /* #ifdef DEFINE_IMAGE_TABLE */
  176 #define MAX_NVM_DIR_ENTRIES 150
  177 /* Note: The has given 150 possible entries since anyway each file captures at least one page. */
  178 
  179 struct nvm_dir_meta {
  180         u32 dir_id;
  181         u32 nvm_dir_addr;
  182         u32 num_images;
  183         u32 next_mfw_to_run;
  184 };
  185 
  186 struct nvm_dir {
  187         s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */
  188 #define NVM_DIR_NEXT_MFW_MASK   0x00000001
  189 #define NVM_DIR_SEQ_MASK        0xfffffffe
  190 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
  191 #define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \
  192         do { \
  193                 _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \
  194         } while (0)
  195 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
  196 
  197         u32 num_images;
  198         u32 rsrv;
  199         struct nvm_code_entry code[1];  /* Up to MAX_NVM_DIR_ENTRIES */
  200 };
  201 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE)
  202 
  203 struct nvm_vpd_image {
  204         u32 format_revision;
  205 #define VPD_IMAGE_VERSION        1
  206 
  207         /* This array length depends on the number of VPD fields */
  208         u8 vpd_data[1];
  209 };
  210 
  211 /****************************************************************************
  212  * NVRAM FULL MAP                                                           *
  213  ****************************************************************************/
  214 #define DIR_ID_1    (0)
  215 #define DIR_ID_2    (1)
  216 #define MAX_DIR_IDS (2)
  217 
  218 #define MFW_BUNDLE_1    (0)
  219 #define MFW_BUNDLE_2    (1)
  220 #define MAX_MFW_BUNDLES (2)
  221 
  222 #define FLASH_PAGE_SIZE 0x1000
  223 #define NVM_DIR_MAX_SIZE    (FLASH_PAGE_SIZE)           /* 4Kb */
  224 #define LEGACY_ASIC_MIM_MAX_SIZE        (_KB(1200))     /* 1.2Mb - E4*/
  225 #define NG_ASIC_MIM_MAX_SIZE            (_MB(2))        /* 2Mb - E5 */
  226 
  227 #define FPGA_MIM_MAX_SIZE   (0x3E000)                   /* 250Kb */
  228 
  229 /* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page.
  230  * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it.
  231  */
  232 #define LIM_MAX_SIZE        ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE)
  233 #define LIM_OFFSET          (NVM_OFFSET(lim_image))
  234 #define NVM_RSV_SIZE            (44)
  235 #define GET_MIM_MAX_SIZE(is_asic, is_e4) ((!is_asic) ? FPGA_MIM_MAX_SIZE : ((is_e4) ?  LEGACY_ASIC_MIM_MAX_SIZE : NG_ASIC_MIM_MAX_SIZE))
  236 #define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ?GET_MIM_MAX_SIZE(is_asic, is_e4) : 0))
  237 #define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4) (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(is_asic, is_e4)*2)
  238 
  239 #define EMUL_NVM_FIXED_AREA_SIZE() (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(0, 0))
  240 
  241 #define E5_MASTER_KEY_CHAIN_ADDR 0x1000
  242 #define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000)
  243 
  244 union nvm_dir_union {
  245         struct nvm_dir dir;
  246         u8 page[FLASH_PAGE_SIZE];
  247 };
  248 
  249 /*          E4            Address                                 E5            Address  
  250  *  +-------------------+ 0x000000                     *  +-------------------+ 0x000000                 
  251  *  |    Bootstrap:     |                              *  |                   |                          
  252  *  | magic_number      |                              *  |                   |                          
  253  *  | sram_start_addr   |                              *  |                   |                          
  254  *  | code_len          |                              *  |                   |                          
  255  *  | code_start_addr   |                              *  |                   |                          
  256  *  | crc               |                              *  |                   |                          
  257  *  +-------------------+ 0x000014                     *  |                   |                          
  258  *  | rsrv              |                              *  | rsrv              |                          
  259  *  +-------------------+ 0x000040                     *  +-------------------+ 0x001000                 
  260  *  | LIM               |                              *  | Master Key Chain  |                          
  261  *  +-------------------+ 0x002000                     *  +-------------------+ 0x002000                 
  262  *  | Dir1              |                              *  | Dir1              |                          
  263  *  +-------------------+ 0x003000                     *  +-------------------+ 0x003000                 
  264  *  | Dir2              |                              *  | Dir2              |                          
  265  *  +-------------------+ 0x004000                     *  +-------------------+ 0x004000                 
  266  *  | MIM1              |                              *  | MIM1              |                          
  267  *  +-------------------+ 0x130000                     *  +-------------------+ 0x130000                 
  268  *  | MIM2              |                              *  | MIM2              |                          
  269  *  +-------------------+ 0x25C000                     *  +-------------------+ 0x25C000                 
  270  *  | Rest Images:      |                              *  | Rest Images:      |                          
  271  *  | TIM1/2            |                              *  | TIM1/2            |                          
  272  *  | MFW_TRACE1/2      |                              *  | MFW_TRACE1/2      |                          
  273  *  | Eagle/Falcon FW   |                              *  | Eagle/Falcon FW   |                          
  274  *  | PCIE/AVS FW       |                              *  | PCIE/AVS FW       |                          
  275  *  | MBA/CCM/L2B       |                              *  | MBA/CCM/L2B       |                          
  276  *  | VPD               |                              *  | VPD               |                          
  277  *  | optic_modules     |                              *  +-------------------+ Flash end - 0x1000       
  278  *  |  ...              |                              *  | Backup Key Chain  |                          
  279  *  +-------------------+ 0x400000                     *  +-------------------+ Flash end                
  280 */                                                                                                       
  281 struct nvm_image {                                                                                       
  282 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
  283                                                 /* NVM Offset  (size) */
  284         struct legacy_bootstrap_region bootstrap;       /* 0x000000 (0x000014) */
  285         u8 rsrv[NVM_RSV_SIZE];                  /* 0x000014 (0x00002c) */
  286         u8 lim_image[LIM_MAX_SIZE];             /* 0x000040 (0x001fc0) */
  287         union nvm_dir_union dir[MAX_MFW_BUNDLES];       /* 0x002000 (0x001000)x2 */
  288         /* MIM1_IMAGE                              0x004000 (0x12c000) */
  289         /* MIM2_IMAGE                              0x130000 (0x12c000) */
  290 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
  291 };                              /* 0x134 */
  292 
  293 #define NVM_OFFSET(f)       ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f))))
  294 
  295 struct hw_set_info {
  296         u32 reg_type;
  297 #define GRC_REG_TYPE 1
  298 #define PHY_REG_TYPE 2
  299 #define PCI_REG_TYPE 4
  300 
  301         u32 bank_num;
  302         u32 pf_num;
  303         u32 operation;
  304 #define READ_OP     1
  305 #define WRITE_OP    2
  306 #define RMW_SET_OP  3
  307 #define RMW_CLR_OP  4
  308 
  309         u32 reg_addr;
  310         u32 reg_data;
  311 
  312         u32 reset_type;
  313 #define POR_RESET_TYPE  (1 << 0)
  314 #define HARD_RESET_TYPE (1 << 1)
  315 #define CORE_RESET_TYPE (1 << 2)
  316 #define MCP_RESET_TYPE  (1 << 3)
  317 #define PERSET_ASSERT   (1 << 4)
  318 #define PERSET_DEASSERT (1 << 5)
  319 
  320 };
  321 
  322 struct hw_set_image {
  323         u32 format_version;
  324 #define HW_SET_IMAGE_VERSION        1
  325         u32 no_hw_sets;
  326         /* This array length depends on the no_hw_sets */
  327         struct hw_set_info hw_sets[1];
  328 };
  329 
  330 #endif                          //NVM_MAP_H
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FreeBSD/Linux Kernel Cross Reference sys/dev/qlnx/qlnxe/nvm_map.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/qlnx/qlnxe/nvm_map.h
