Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/qlnx/qlnxr/qlnxr_roce.h
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1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __QLNXR_ROCE_H__ 32 #define __QLNXR_ROCE_H__ 33 34 /* 35 * roce completion notification queue element 36 */ 37 struct roce_cnqe { 38 struct regpair cq_handle; 39 }; 40 41 struct roce_cqe_responder { 42 struct regpair srq_wr_id; 43 struct regpair qp_handle; 44 __le32 imm_data_or_inv_r_Key; 45 __le32 length; 46 __le32 reserved0; 47 __le16 rq_cons; 48 u8 flags; 49 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 50 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0 51 #define ROCE_CQE_RESPONDER_TYPE_MASK 0x3 52 #define ROCE_CQE_RESPONDER_TYPE_SHIFT 1 53 #define ROCE_CQE_RESPONDER_INV_FLG_MASK 0x1 54 #define ROCE_CQE_RESPONDER_INV_FLG_SHIFT 3 55 #define ROCE_CQE_RESPONDER_IMM_FLG_MASK 0x1 56 #define ROCE_CQE_RESPONDER_IMM_FLG_SHIFT 4 57 #define ROCE_CQE_RESPONDER_RDMA_FLG_MASK 0x1 58 #define ROCE_CQE_RESPONDER_RDMA_FLG_SHIFT 5 59 #define ROCE_CQE_RESPONDER_RESERVED2_MASK 0x3 60 #define ROCE_CQE_RESPONDER_RESERVED2_SHIFT 6 61 u8 status; 62 }; 63 64 struct roce_cqe_requester { 65 __le16 sq_cons; 66 __le16 reserved0; 67 __le32 reserved1; 68 struct regpair qp_handle; 69 struct regpair reserved2; 70 __le32 reserved3; 71 __le16 reserved4; 72 u8 flags; 73 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1 74 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0 75 #define ROCE_CQE_REQUESTER_TYPE_MASK 0x3 76 #define ROCE_CQE_REQUESTER_TYPE_SHIFT 1 77 #define ROCE_CQE_REQUESTER_RESERVED5_MASK 0x1F 78 #define ROCE_CQE_REQUESTER_RESERVED5_SHIFT 3 79 u8 status; 80 }; 81 82 struct roce_cqe_common { 83 struct regpair reserved0; 84 struct regpair qp_handle; 85 __le16 reserved1[7]; 86 u8 flags; 87 #define ROCE_CQE_COMMON_TOGGLE_BIT_MASK 0x1 88 #define ROCE_CQE_COMMON_TOGGLE_BIT_SHIFT 0 89 #define ROCE_CQE_COMMON_TYPE_MASK 0x3 90 #define ROCE_CQE_COMMON_TYPE_SHIFT 1 91 #define ROCE_CQE_COMMON_RESERVED2_MASK 0x1F 92 #define ROCE_CQE_COMMON_RESERVED2_SHIFT 3 93 u8 status; 94 }; 95 96 /* 97 * roce completion queue element 98 */ 99 union roce_cqe { 100 struct roce_cqe_responder resp; 101 struct roce_cqe_requester req; 102 struct roce_cqe_common cmn; 103 }; 104 105 /* 106 * CQE requester status enumeration 107 */ 108 enum roce_cqe_requester_status_enum { 109 ROCE_CQE_REQ_STS_OK, 110 ROCE_CQE_REQ_STS_BAD_RESPONSE_ERR, 111 ROCE_CQE_REQ_STS_LOCAL_LENGTH_ERR, 112 ROCE_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR, 113 ROCE_CQE_REQ_STS_LOCAL_PROTECTION_ERR, 114 ROCE_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR, 115 ROCE_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR, 116 ROCE_CQE_REQ_STS_REMOTE_ACCESS_ERR, 117 ROCE_CQE_REQ_STS_REMOTE_OPERATION_ERR, 118 ROCE_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR, 119 ROCE_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR, 120 ROCE_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR, 121 MAX_ROCE_CQE_REQUESTER_STATUS_ENUM 122 }; 123 124 /* 125 * CQE responder status enumeration 126 */ 127 enum roce_cqe_responder_status_enum { 128 ROCE_CQE_RESP_STS_OK, 129 ROCE_CQE_RESP_STS_LOCAL_ACCESS_ERR, 130 ROCE_CQE_RESP_STS_LOCAL_LENGTH_ERR, 131 ROCE_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR, 132 ROCE_CQE_RESP_STS_LOCAL_PROTECTION_ERR, 133 ROCE_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR, 134 ROCE_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR, 135 ROCE_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR, 136 MAX_ROCE_CQE_RESPONDER_STATUS_ENUM 137 }; 138 139 /* 140 * CQE type enumeration 141 */ 142 enum roce_cqe_type { 143 ROCE_CQE_TYPE_REQUESTER, 144 ROCE_CQE_TYPE_RESPONDER_RQ, 145 ROCE_CQE_TYPE_RESPONDER_SRQ, 146 ROCE_CQE_TYPE_INVALID, 147 MAX_ROCE_CQE_TYPE 148 }; 149 150 /* 151 * memory window type enumeration 152 */ 153 enum roce_mw_type { 154 ROCE_MW_TYPE_1, 155 ROCE_MW_TYPE_2A, 156 MAX_ROCE_MW_TYPE 157 }; 158 159 struct roce_rq_sge { 160 struct regpair addr; 161 __le32 length; 162 __le32 flags; 163 #define ROCE_RQ_SGE_L_KEY_MASK 0x3FFFFFF 164 #define ROCE_RQ_SGE_L_KEY_SHIFT 0 165 #define ROCE_RQ_SGE_NUM_SGES_MASK 0x7 166 #define ROCE_RQ_SGE_NUM_SGES_SHIFT 26 167 #define ROCE_RQ_SGE_RESERVED0_MASK 0x7 168 #define ROCE_RQ_SGE_RESERVED0_SHIFT 29 169 }; 170 171 struct roce_sq_atomic_wqe { 172 struct regpair remote_va; 173 __le32 xrc_srq; 174 u8 req_type; 175 u8 flags; 176 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1 177 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0 178 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1 179 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT 1 180 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1 181 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT 2 182 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1 183 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_SHIFT 3 184 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1 185 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT 4 186 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_MASK 0x7 187 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_SHIFT 5 188 u8 reserved1; 189 u8 prev_wqe_size; 190 struct regpair swap_data; 191 __le32 r_key; 192 __le32 reserved2; 193 struct regpair cmp_data; 194 struct regpair reserved3; 195 }; 196 197 /* 198 * First element (16 bytes) of atomic wqe 199 */ 200 struct roce_sq_atomic_wqe_1st { 201 struct regpair remote_va; 202 __le32 xrc_srq; 203 u8 req_type; 204 u8 flags; 205 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1 206 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0 207 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1 208 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT 1 209 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1 210 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2 211 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1 212 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT 3 213 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1 214 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT 4 215 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7 216 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT 5 217 u8 reserved1; 218 u8 prev_wqe_size; 219 }; 220 221 /* 222 * Second element (16 bytes) of atomic wqe 223 */ 224 struct roce_sq_atomic_wqe_2nd { 225 struct regpair swap_data; 226 __le32 r_key; 227 __le32 reserved2; 228 }; 229 230 /* 231 * Third element (16 bytes) of atomic wqe 232 */ 233 struct roce_sq_atomic_wqe_3rd { 234 struct regpair cmp_data; 235 struct regpair reserved3; 236 }; 237 238 struct roce_sq_bind_wqe { 239 struct regpair addr; 240 __le32 l_key; 241 u8 req_type; 242 u8 flags; 243 #define ROCE_SQ_BIND_WQE_COMP_FLG_MASK 0x1 244 #define ROCE_SQ_BIND_WQE_COMP_FLG_SHIFT 0 245 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1 246 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT 1 247 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1 248 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2 249 #define ROCE_SQ_BIND_WQE_SE_FLG_MASK 0x1 250 #define ROCE_SQ_BIND_WQE_SE_FLG_SHIFT 3 251 #define ROCE_SQ_BIND_WQE_INLINE_FLG_MASK 0x1 252 #define ROCE_SQ_BIND_WQE_INLINE_FLG_SHIFT 4 253 #define ROCE_SQ_BIND_WQE_RESERVED0_MASK 0x7 254 #define ROCE_SQ_BIND_WQE_RESERVED0_SHIFT 5 255 u8 access_ctrl; 256 #define ROCE_SQ_BIND_WQE_REMOTE_READ_MASK 0x1 257 #define ROCE_SQ_BIND_WQE_REMOTE_READ_SHIFT 0 258 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1 259 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_SHIFT 1 260 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1 261 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2 262 #define ROCE_SQ_BIND_WQE_LOCAL_READ_MASK 0x1 263 #define ROCE_SQ_BIND_WQE_LOCAL_READ_SHIFT 3 264 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1 265 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_SHIFT 4 266 #define ROCE_SQ_BIND_WQE_RESERVED1_MASK 0x7 267 #define ROCE_SQ_BIND_WQE_RESERVED1_SHIFT 5 268 u8 prev_wqe_size; 269 u8 bind_ctrl; 270 #define ROCE_SQ_BIND_WQE_ZERO_BASED_MASK 0x1 271 #define ROCE_SQ_BIND_WQE_ZERO_BASED_SHIFT 0 272 #define ROCE_SQ_BIND_WQE_MW_TYPE_MASK 0x1 273 #define ROCE_SQ_BIND_WQE_MW_TYPE_SHIFT 1 274 #define ROCE_SQ_BIND_WQE_RESERVED2_MASK 0x3F 275 #define ROCE_SQ_BIND_WQE_RESERVED2_SHIFT 2 276 u8 reserved3[2]; 277 u8 length_hi; 278 __le32 length_lo; 279 __le32 parent_l_key; 280 __le32 reserved6; 281 }; 282 283 /* 284 * First element (16 bytes) of bind wqe 285 */ 286 struct roce_sq_bind_wqe_1st { 287 struct regpair addr; 288 __le32 l_key; 289 u8 req_type; 290 u8 flags; 291 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1 292 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0 293 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 294 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 295 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 296 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 297 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1 298 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_SHIFT 3 299 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1 300 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT 4 301 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7 302 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_SHIFT 5 303 u8 access_ctrl; 304 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_MASK 0x1 305 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_SHIFT 0 306 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_MASK 0x1 307 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_SHIFT 1 308 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_MASK 0x1 309 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_SHIFT 2 310 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_MASK 0x1 311 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_SHIFT 3 312 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_MASK 0x1 313 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_SHIFT 4 314 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_MASK 0x7 315 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_SHIFT 5 316 u8 prev_wqe_size; 317 }; 318 319 /* 320 * Second element (16 bytes) of bind wqe 321 */ 322 struct roce_sq_bind_wqe_2nd { 323 u8 bind_ctrl; 324 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1 325 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0 326 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_MASK 0x1 327 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_SHIFT 1 328 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x3F 329 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_SHIFT 2 330 u8 reserved3[2]; 331 u8 length_hi; 332 __le32 length_lo; 333 __le32 parent_l_key; 334 __le32 reserved6; 335 }; 336 337 /* 338 * Structure with only the SQ WQE common fields. Size is of one SQ element (16B) 339 */ 340 struct roce_sq_common_wqe { 341 __le32 reserved1[3]; 342 u8 req_type; 343 u8 flags; 344 #define ROCE_SQ_COMMON_WQE_COMP_FLG_MASK 0x1 345 #define ROCE_SQ_COMMON_WQE_COMP_FLG_SHIFT 0 346 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1 347 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT 1 348 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1 349 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2 350 #define ROCE_SQ_COMMON_WQE_SE_FLG_MASK 0x1 351 #define ROCE_SQ_COMMON_WQE_SE_FLG_SHIFT 3 352 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1 353 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_SHIFT 4 354 #define ROCE_SQ_COMMON_WQE_RESERVED0_MASK 0x7 355 #define ROCE_SQ_COMMON_WQE_RESERVED0_SHIFT 5 356 u8 reserved2; 357 u8 prev_wqe_size; 358 }; 359 360 struct roce_sq_fmr_wqe { 361 struct regpair addr; 362 __le32 l_key; 363 u8 req_type; 364 u8 flags; 365 #define ROCE_SQ_FMR_WQE_COMP_FLG_MASK 0x1 366 #define ROCE_SQ_FMR_WQE_COMP_FLG_SHIFT 0 367 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1 368 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT 1 369 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1 370 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT 2 371 #define ROCE_SQ_FMR_WQE_SE_FLG_MASK 0x1 372 #define ROCE_SQ_FMR_WQE_SE_FLG_SHIFT 3 373 #define ROCE_SQ_FMR_WQE_INLINE_FLG_MASK 0x1 374 #define ROCE_SQ_FMR_WQE_INLINE_FLG_SHIFT 4 375 #define ROCE_SQ_FMR_WQE_RESERVED0_MASK 0x7 376 #define ROCE_SQ_FMR_WQE_RESERVED0_SHIFT 5 377 u8 access_ctrl; 378 #define ROCE_SQ_FMR_WQE_REMOTE_READ_MASK 0x1 379 #define ROCE_SQ_FMR_WQE_REMOTE_READ_SHIFT 0 380 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1 381 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_SHIFT 1 382 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1 383 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT 2 384 #define ROCE_SQ_FMR_WQE_LOCAL_READ_MASK 0x1 385 #define ROCE_SQ_FMR_WQE_LOCAL_READ_SHIFT 3 386 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1 387 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_SHIFT 4 388 #define ROCE_SQ_FMR_WQE_RESERVED1_MASK 0x7 389 #define ROCE_SQ_FMR_WQE_RESERVED1_SHIFT 5 390 u8 prev_wqe_size; 391 u8 fmr_ctrl; 392 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F 393 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0 394 #define ROCE_SQ_FMR_WQE_ZERO_BASED_MASK 0x1 395 #define ROCE_SQ_FMR_WQE_ZERO_BASED_SHIFT 5 396 #define ROCE_SQ_FMR_WQE_BIND_EN_MASK 0x1 397 #define ROCE_SQ_FMR_WQE_BIND_EN_SHIFT 6 398 #define ROCE_SQ_FMR_WQE_RESERVED2_MASK 0x1 399 #define ROCE_SQ_FMR_WQE_RESERVED2_SHIFT 7 400 u8 reserved3[2]; 401 u8 length_hi; 402 __le32 length_lo; 403 struct regpair pbl_addr; 404 }; 405 406 /* 407 * First element (16 bytes) of fmr wqe 408 */ 409 struct roce_sq_fmr_wqe_1st { 410 struct regpair addr; 411 __le32 l_key; 412 u8 req_type; 413 u8 flags; 414 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1 415 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0 416 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1 417 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT 1 418 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1 419 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT 2 420 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1 421 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_SHIFT 3 422 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1 423 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT 4 424 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x7 425 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_SHIFT 5 426 u8 access_ctrl; 427 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_MASK 0x1 428 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_SHIFT 0 429 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_MASK 0x1 430 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_SHIFT 1 431 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_MASK 0x1 432 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_SHIFT 2 433 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_MASK 0x1 434 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_SHIFT 3 435 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_MASK 0x1 436 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_SHIFT 4 437 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_MASK 0x7 438 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_SHIFT 5 439 u8 prev_wqe_size; 440 }; 441 442 /* 443 * Second element (16 bytes) of fmr wqe 444 */ 445 struct roce_sq_fmr_wqe_2nd { 446 u8 fmr_ctrl; 447 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F 448 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0 449 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1 450 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT 5 451 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1 452 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_SHIFT 6 453 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x1 454 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_SHIFT 7 455 u8 reserved3[2]; 456 u8 length_hi; 457 __le32 length_lo; 458 struct regpair pbl_addr; 459 }; 460 461 struct roce_sq_local_inv_wqe { 462 struct regpair reserved; 463 __le32 inv_l_key; 464 u8 req_type; 465 u8 flags; 466 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1 467 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0 468 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1 469 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT 1 470 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1 471 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT 2 472 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1 473 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT 3 474 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1 475 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT 4 476 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x7 477 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT 5 478 u8 reserved1; 479 u8 prev_wqe_size; 480 }; 481 482 struct roce_sq_rdma_wqe { 483 __le32 imm_data; 484 __le32 length; 485 __le32 xrc_srq; 486 u8 req_type; 487 u8 flags; 488 #define ROCE_SQ_RDMA_WQE_COMP_FLG_MASK 0x1 489 #define ROCE_SQ_RDMA_WQE_COMP_FLG_SHIFT 0 490 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1 491 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1 492 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1 493 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2 494 #define ROCE_SQ_RDMA_WQE_SE_FLG_MASK 0x1 495 #define ROCE_SQ_RDMA_WQE_SE_FLG_SHIFT 3 496 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1 497 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4 498 #define ROCE_SQ_RDMA_WQE_RESERVED0_MASK 0x7 499 #define ROCE_SQ_RDMA_WQE_RESERVED0_SHIFT 5 500 u8 wqe_size; 501 u8 prev_wqe_size; 502 struct regpair remote_va; 503 __le32 r_key; 504 __le32 reserved1; 505 }; 506 507 /* 508 * First element (16 bytes) of rdma wqe 509 */ 510 struct roce_sq_rdma_wqe_1st { 511 __le32 imm_data; 512 __le32 length; 513 __le32 xrc_srq; 514 u8 req_type; 515 u8 flags; 516 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1 517 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0 518 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1 519 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT 1 520 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1 521 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT 2 522 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1 523 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT 3 524 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1 525 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4 526 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x7 527 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 5 528 u8 wqe_size; 529 u8 prev_wqe_size; 530 }; 531 532 /* 533 * Second element (16 bytes) of rdma wqe 534 */ 535 struct roce_sq_rdma_wqe_2nd { 536 struct regpair remote_va; 537 __le32 r_key; 538 __le32 reserved1; 539 }; 540 541 /* 542 * SQ WQE req type enumeration 543 */ 544 enum roce_sq_req_type { 545 ROCE_SQ_REQ_TYPE_SEND, 546 ROCE_SQ_REQ_TYPE_SEND_WITH_IMM, 547 ROCE_SQ_REQ_TYPE_SEND_WITH_INVALIDATE, 548 ROCE_SQ_REQ_TYPE_RDMA_WR, 549 ROCE_SQ_REQ_TYPE_RDMA_WR_WITH_IMM, 550 ROCE_SQ_REQ_TYPE_RDMA_RD, 551 ROCE_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP, 552 ROCE_SQ_REQ_TYPE_ATOMIC_ADD, 553 ROCE_SQ_REQ_TYPE_LOCAL_INVALIDATE, 554 ROCE_SQ_REQ_TYPE_FAST_MR, 555 ROCE_SQ_REQ_TYPE_BIND, 556 ROCE_SQ_REQ_TYPE_INVALID, 557 MAX_ROCE_SQ_REQ_TYPE 558 }; 559 560 struct roce_sq_send_wqe { 561 __le32 inv_key_or_imm_data; 562 __le32 length; 563 __le32 xrc_srq; 564 u8 req_type; 565 u8 flags; 566 #define ROCE_SQ_SEND_WQE_COMP_FLG_MASK 0x1 567 #define ROCE_SQ_SEND_WQE_COMP_FLG_SHIFT 0 568 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1 569 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT 1 570 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1 571 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT 2 572 #define ROCE_SQ_SEND_WQE_SE_FLG_MASK 0x1 573 #define ROCE_SQ_SEND_WQE_SE_FLG_SHIFT 3 574 #define ROCE_SQ_SEND_WQE_INLINE_FLG_MASK 0x1 575 #define ROCE_SQ_SEND_WQE_INLINE_FLG_SHIFT 4 576 #define ROCE_SQ_SEND_WQE_RESERVED0_MASK 0x7 577 #define ROCE_SQ_SEND_WQE_RESERVED0_SHIFT 5 578 u8 wqe_size; 579 u8 prev_wqe_size; 580 }; 581 582 struct roce_sq_sge { 583 __le32 length; 584 struct regpair addr; 585 __le32 l_key; 586 }; 587 588 struct roce_srq_prod { 589 __le16 prod; 590 }; 591 592 struct roce_srq_sge { 593 struct regpair addr; 594 __le32 length; 595 __le32 l_key; 596 struct regpair wr_id; 597 u8 flags; 598 #define ROCE_SRQ_SGE_NUM_SGES_MASK 0x3 599 #define ROCE_SRQ_SGE_NUM_SGES_SHIFT 0 600 #define ROCE_SRQ_SGE_RESERVED0_MASK 0x3F 601 #define ROCE_SRQ_SGE_RESERVED0_SHIFT 2 602 u8 reserved1; 603 __le16 reserved2; 604 __le32 reserved3; 605 }; 606 607 /* 608 * RoCE doorbell data for SQ and RQ 609 */ 610 struct roce_pwm_val16_data { 611 __le16 icid; 612 __le16 prod_val; 613 }; 614 615 union roce_pwm_val16_data_union { 616 struct roce_pwm_val16_data as_struct; 617 __le32 as_dword; 618 }; 619 620 /* 621 * RoCE doorbell data for CQ 622 */ 623 struct roce_pwm_val32_data { 624 __le16 icid; 625 u8 agg_flags; 626 u8 params; 627 #define ROCE_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 628 #define ROCE_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 629 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 630 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 631 #define ROCE_PWM_VAL32_DATA_RESERVED_MASK 0x1F 632 #define ROCE_PWM_VAL32_DATA_RESERVED_SHIFT 3 633 __le32 cq_cons_val; 634 }; 635 636 union roce_pwm_val32_data_union { 637 struct roce_pwm_val32_data as_struct; 638 struct regpair as_repair; 639 }; 640 641 #endif /* __QLNXR_ROCE_H__ */
Cache object: 82dc20bbe5e68c7528c32fa46129d7d9
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