Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/qlxgb/qla_hw.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2013 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 /* 32 * File: qla_hw.h 33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 34 */ 35 #ifndef _QLA_HW_H_ 36 #define _QLA_HW_H_ 37 38 #define Q8_MAX_NUM_MULTICAST_ADDRS 128 39 #define Q8_MAC_ADDR_LEN 6 40 41 /* 42 * Firmware Interface 43 */ 44 45 /* 46 * Command Response Interface - Commands 47 */ 48 typedef struct qla_cdrp { 49 uint32_t cmd; 50 uint32_t cmd_arg1; 51 uint32_t cmd_arg2; 52 uint32_t cmd_arg3; 53 uint32_t rsp; 54 uint32_t rsp_arg1; 55 uint32_t rsp_arg2; 56 uint32_t rsp_arg3; 57 } qla_cdrp_t; 58 59 #define Q8_CMD_RD_MAX_RDS_PER_CNTXT 0x80000002 60 #define Q8_CMD_RD_MAX_SDS_PER_CNTXT 0x80000003 61 #define Q8_CMD_RD_MAX_RULES_PER_CNTXT 0x80000004 62 #define Q8_CMD_RD_MAX_RX_CNTXT 0x80000005 63 #define Q8_CMD_RD_MAX_TX_CNTXT 0x80000006 64 #define Q8_CMD_CREATE_RX_CNTXT 0x80000007 65 #define Q8_CMD_DESTROY_RX_CNTXT 0x80000008 66 #define Q8_CMD_CREATE_TX_CNTXT 0x80000009 67 #define Q8_CMD_DESTROY_TX_CNTXT 0x8000000A 68 #define Q8_CMD_SETUP_STATS 0x8000000E 69 #define Q8_CMD_GET_STATS 0x8000000F 70 #define Q8_CMD_DELETE_STATS 0x80000010 71 #define Q8_CMD_GEN_INT 0x80000011 72 #define Q8_CMD_SET_MTU 0x80000012 73 #define Q8_CMD_GET_FLOW_CNTRL 0x80000016 74 #define Q8_CMD_SET_FLOW_CNTRL 0x80000017 75 #define Q8_CMD_RD_MAX_MTU 0x80000018 76 #define Q8_CMD_RD_MAX_LRO 0x80000019 77 78 /* 79 * Command Response Interface - Response 80 */ 81 #define Q8_RSP_SUCCESS 0x00000000 82 #define Q8_RSP_NO_HOST_MEM 0x00000001 83 #define Q8_RSP_NO_HOST_RSRC 0x00000002 84 #define Q8_RSP_NO_CARD_CRB 0x00000003 85 #define Q8_RSP_NO_CARD_MEM 0x00000004 86 #define Q8_RSP_NO_CARD_RSRC 0x00000005 87 #define Q8_RSP_INVALID_ARGS 0x00000006 88 #define Q8_RSP_INVALID_ACTION 0x00000007 89 #define Q8_RSP_INVALID_STATE 0x00000008 90 #define Q8_RSP_NOT_SUPPORTED 0x00000009 91 #define Q8_RSP_NOT_PERMITTED 0x0000000A 92 #define Q8_RSP_NOT_READY 0x0000000B 93 #define Q8_RSP_DOES_NOT_EXIST 0x0000000C 94 #define Q8_RSP_ALREADY_EXISTS 0x0000000D 95 #define Q8_RSP_BAD_SIGNATURE 0x0000000E 96 #define Q8_RSP_CMD_NOT_IMPLEMENTED 0x0000000F 97 #define Q8_RSP_CMD_INVALID 0x00000010 98 #define Q8_RSP_TIMEOUT 0x00000011 99 100 /* 101 * Transmit Related Definitions 102 */ 103 104 /* 105 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 106 */ 107 108 typedef struct _q80_tx_cntxt_req { 109 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */ 110 uint64_t cmd_cons_dma_addr; 111 uint64_t rsrvd0; 112 113 uint32_t caps[4]; /* capabilities - bit vector*/ 114 #define CNTXT_CAP0_BASEFW 0x0001 115 #define CNTXT_CAP0_LEGACY_MN 0x0004 116 #define CNTXT_CAP0_LSO 0x0040 117 118 uint32_t intr_mode; /* Interrupt Mode */ 119 #define CNTXT_INTR_MODE_UNIQUE 0x0000 120 #define CNTXT_INTR_MODE_SHARED 0x0001 121 122 uint64_t rsrvd1; 123 uint16_t msi_index; 124 uint16_t rsrvd2; 125 uint64_t phys_addr; /* physical address of transmit ring 126 * in system memory */ 127 uint32_t num_entries; /* number of entries in transmit ring */ 128 uint8_t rsrvd3[128]; 129 } __packed q80_tx_cntxt_req_t; /* 188 bytes total */ 130 131 /* 132 * Transmit Context - Response from Firmware to Q8_CMD_CREATE_TX_CNTXT 133 */ 134 135 typedef struct _q80_tx_cntxt_rsp { 136 uint32_t cntxt_state; /* starting state */ 137 #define CNTXT_STATE_ALLOCATED_NOT_ACTIVE 0x0001 138 #define CNTXT_STATE_ACTIVE 0x0002 139 #define CNTXT_STATE_QUIESCED 0x0004 140 141 uint16_t cntxt_id; /* handle for context */ 142 uint8_t phys_port_id; /* physical id of port */ 143 uint8_t virt_port_id; /* virtual or logical id of port */ 144 uint32_t producer_reg; /* producer register for transmit ring */ 145 uint32_t intr_mask_reg; /* interrupt mask register */ 146 uint8_t rsrvd[128]; 147 } __packed q80_tx_cntxt_rsp_t; /* 144 bytes */ 148 149 /* 150 * Transmit Command Descriptor 151 * These commands are issued on the Transmit Ring associated with a Transmit 152 * context 153 */ 154 typedef struct _q80_tx_cmd { 155 uint8_t tcp_hdr_off; /* TCP Header Offset */ 156 uint8_t ip_hdr_off; /* IP Header Offset */ 157 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 158 159 /* flags field */ 160 #define Q8_TX_CMD_FLAGS_MULTICAST 0x01 161 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 162 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 163 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 164 165 /* opcode field */ 166 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 167 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 168 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 169 #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 170 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 171 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 172 #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 173 174 uint8_t n_bufs; /* # of data segs in data buffer */ 175 uint8_t data_len_lo; /* data length lower 8 bits */ 176 uint16_t data_len_hi; /* data length upper 16 bits */ 177 178 uint64_t buf2_addr; /* buffer 2 address */ 179 180 uint16_t rsrvd0; 181 uint16_t mss; /* MSS for this packet */ 182 uint8_t port_cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 183 184 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 185 186 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 187 uint16_t rsrvd1; 188 189 uint64_t buf3_addr; /* buffer 3 address */ 190 uint64_t buf1_addr; /* buffer 1 address */ 191 192 uint16_t buf1_len; /* length of buffer 1 */ 193 uint16_t buf2_len; /* length of buffer 2 */ 194 uint16_t buf3_len; /* length of buffer 3 */ 195 uint16_t buf4_len; /* length of buffer 4 */ 196 197 uint64_t buf4_addr; /* buffer 4 address */ 198 199 uint32_t rsrvd2; 200 uint16_t rsrvd3; 201 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 202 203 } __packed q80_tx_cmd_t; /* 64 bytes */ 204 205 #define Q8_TX_CMD_MAX_SEGMENTS 4 206 #define Q8_TX_CMD_TSO_ALIGN 2 207 #define Q8_TX_MAX_SEGMENTS 14 208 209 /* 210 * Receive Related Definitions 211 */ 212 /* 213 * Receive Context - Q8_CMD_CREATE_RX_CNTXT Command Configuration Data 214 */ 215 216 typedef struct _q80_rq_sds_ring { 217 uint64_t phys_addr; /* physical addr of status ring in system memory */ 218 uint32_t size; /* number of entries in status ring */ 219 uint16_t msi_index; 220 uint16_t rsrvd; 221 } __packed q80_rq_sds_ring_t; /* 16 bytes */ 222 223 typedef struct _q80_rq_rds_ring { 224 uint64_t phys_addr; /* physical addr of rcv ring in system memory */ 225 uint64_t buf_size; /* packet buffer size */ 226 uint32_t size; /* number of entries in ring */ 227 uint32_t rsrvd; 228 } __packed q80_rq_rds_ring_t; /* 24 bytes */ 229 230 typedef struct _q80_rq_rcv_cntxt { 231 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */ 232 uint32_t caps[4]; /* bit vector */ 233 #define CNTXT_CAP0_JUMBO 0x0080 /* Contiguous Jumbo buffers*/ 234 #define CNTXT_CAP0_LRO 0x0100 235 #define CNTXT_CAP0_HW_LRO 0x0800 /* HW LRO */ 236 237 uint32_t intr_mode; /* same as q80_tx_cntxt_req_t */ 238 uint32_t rds_intr_mode; /* same as q80_tx_cntxt_req_t */ 239 240 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */ 241 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */ 242 243 uint16_t num_rds_rings; 244 uint16_t num_sds_rings; 245 246 uint8_t rsrvd1[132]; 247 } __packed q80_rq_rcv_cntxt_t; /* 176 bytes header + rds + sds ring rqsts */ 248 249 /* 250 * Receive Context - Response from Firmware to Q8_CMD_CREATE_RX_CNTXT 251 */ 252 253 typedef struct _q80_rsp_rds_ring { 254 uint32_t producer_reg; 255 uint32_t rsrvd; 256 } __packed q80_rsp_rds_ring_t; /* 8 bytes */ 257 258 typedef struct _q80_rsp_sds_ring { 259 uint32_t consumer_reg; 260 uint32_t intr_mask_reg; 261 } __packed q80_rsp_sds_ring_t; /* 8 bytes */ 262 263 typedef struct _q80_rsp_rcv_cntxt { 264 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */ 265 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */ 266 267 uint32_t cntxt_state; /* starting state */ 268 uint32_t funcs_per_port; /* number of PCI functions sharing each port */ 269 270 uint16_t num_rds_rings; 271 uint16_t num_sds_rings; 272 273 uint16_t cntxt_id; /* handle for context */ 274 275 uint8_t phys_port; /* physical id of port */ 276 uint8_t virt_port; /* virtual or logical id of port */ 277 278 uint8_t rsrvd[128]; 279 uint8_t data[0]; 280 } __packed q80_rsp_rcv_cntxt_t; /* 152 bytes header + rds + sds ring rspncs */ 281 282 /* 283 * Note: 284 * Transmit Context 285 * 188 (rq) + 144 (rsp) = 332 bytes are required 286 * 287 * Receive Context 288 * 1 RDS and 1 SDS rings: (16+24+176)+(8+8+152) = 384 bytes 289 * 290 * 3 RDS and 4 SDS rings: (((16+24)*3)+176) + (((8+8)*4)+152) = 291 * = 296 + 216 = 512 bytes 292 * Clearly this within the minimum PAGE size of most O.S platforms 293 * (typically 4Kbytes). Hence it is simpler to simply allocate one PAGE 294 * and then carve out space for each context. It is also a good idea to 295 * to throw in the shadown register for the consumer index of the transmit 296 * ring in this PAGE. 297 */ 298 299 /* 300 * Receive Descriptor corresponding to each entry in the receive ring 301 */ 302 typedef struct _q80_rcv_desc { 303 uint16_t handle; 304 uint16_t rsrvd; 305 uint32_t buf_size; /* buffer size in bytes */ 306 uint64_t buf_addr; /* physical address of buffer */ 307 } __packed q80_recv_desc_t; 308 309 /* 310 * Status Descriptor corresponding to each entry in the Status ring 311 */ 312 typedef struct _q80_stat_desc { 313 uint64_t data[2]; 314 } __packed q80_stat_desc_t; 315 316 /* 317 * definitions for data[0] field of Status Descriptor 318 */ 319 #define Q8_STAT_DESC_OWNER(data) ((data >> 56) & 0x3) 320 #define Q8_STAT_DESC_OWNER_HOST 0x1 321 #define Q8_STAT_DESC_OWNER_FW 0x2 322 323 #define Q8_STAT_DESC_OWNER_MASK (((uint64_t)0x3) << 56) 324 #define Q8_STAT_DESC_SET_OWNER(owner) (uint64_t)(((uint64_t)owner) << 56) 325 326 #define Q8_STAT_DESC_OPCODE(data) ((data >> 58) & 0x003F) 327 #define Q8_STAT_DESC_OPCODE_SYN_OFFLOAD 0x03 328 #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x04 329 #define Q8_STAT_DESC_OPCODE_CTRL_MSG 0x05 330 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x12 331 332 /* 333 * definitions for data[0] field of Status Descriptor for standard frames 334 * status descriptor opcode equals 0x04 335 */ 336 #define Q8_STAT_DESC_PORT(data) ((data) & 0x000F) 337 #define Q8_STAT_DESC_STATUS(data) ((data >> 4) & 0x000F) 338 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 339 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 340 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 341 342 #define Q8_STAT_DESC_TYPE(data) ((data >> 8) & 0x000F) 343 #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 12) & 0xFFFF) 344 #define Q8_STAT_DESC_HANDLE(data) ((data >> 28) & 0xFFFF) 345 #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 346 #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 347 #define Q8_STAT_DESC_COUNT(data) ((data >> 53) & 0x0007) 348 349 /* 350 * definitions for data[0-1] fields of Status Descriptor for LRO 351 * status descriptor opcode equals 0x05 352 */ 353 /* definitions for data[0] field */ 354 #define Q8_LRO_STAT_DESC_HANDLE(data) ((data) & 0xFFFF) 355 #define Q8_LRO_STAT_DESC_PAYLOAD_LENGTH(data) ((data >> 16) & 0xFFFF) 356 #define Q8_LRO_STAT_DESC_L2_OFFSET(data) ((data >> 32) & 0xFF) 357 #define Q8_LRO_STAT_DESC_L4_OFFSET(data) ((data >> 40) & 0xFF) 358 #define Q8_LRO_STAT_DESC_TS_PRESENT(data) ((data >> 48) & 0x1) 359 #define Q8_LRO_STAT_DESC_TYPE(data) ((data >> 49) & 0x7) 360 #define Q8_LRO_STAT_DESC_PUSH_BIT(data) ((data >> 52) & 0x1) 361 362 /* definitions for data[1] field */ 363 #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 364 365 /** Driver Related Definitions Begin **/ 366 367 #define MAX_RDS_RINGS 2 /* Max# of Receive Descriptor Rings */ 368 #define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */ 369 #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 370 371 /* The number of descriptors should be a power of 2 */ 372 #define NUM_TX_DESCRIPTORS 2048 373 #define NUM_RX_DESCRIPTORS 8192 374 //#define NUM_RX_JUMBO_DESCRIPTORS 1024 375 #define NUM_RX_JUMBO_DESCRIPTORS 2048 376 //#define NUM_STATUS_DESCRIPTORS 8192 377 #define NUM_STATUS_DESCRIPTORS 2048 378 379 typedef struct _q80_rcv_cntxt_req { 380 q80_rq_rcv_cntxt_t rx_req; 381 q80_rq_rds_ring_t rds_req[MAX_RDS_RINGS]; 382 q80_rq_sds_ring_t sds_req[MAX_SDS_RINGS]; 383 } __packed q80_rcv_cntxt_req_t; 384 385 typedef struct _q80_rcv_cntxt_rsp { 386 q80_rsp_rcv_cntxt_t rx_rsp; 387 q80_rsp_rds_ring_t rds_rsp[MAX_RDS_RINGS]; 388 q80_rsp_sds_ring_t sds_rsp[MAX_SDS_RINGS]; 389 } __packed q80_rcv_cntxt_rsp_t; 390 391 /* 392 * structure describing various dma buffers 393 */ 394 #define RDS_RING_INDEX_NORMAL 0 395 #define RDS_RING_INDEX_JUMBO 1 396 397 typedef struct qla_dmabuf { 398 volatile struct { 399 uint32_t tx_ring :1, 400 rds_ring :1, 401 sds_ring :1, 402 context :1; 403 } flags; 404 405 qla_dma_t tx_ring; 406 qla_dma_t rds_ring[MAX_RDS_RINGS]; 407 qla_dma_t sds_ring[MAX_SDS_RINGS]; 408 qla_dma_t context; 409 } qla_dmabuf_t; 410 411 /** Driver Related Definitions End **/ 412 413 /* 414 * Firmware Control Descriptor 415 */ 416 typedef struct _qla_fw_cds_hdr { 417 uint64_t cmd; 418 #define Q8_FWCD_CNTRL_REQ (0x13 << 23) 419 uint8_t opcode; 420 uint8_t cookie; 421 uint16_t cntxt_id; 422 uint8_t response; 423 #define Q8_FW_CDS_HDR_COMPLETION 0x1 424 uint16_t rsrvd; 425 uint8_t sub_opcode; 426 } __packed qla_fw_cds_hdr_t; 427 428 /* 429 * definitions for opcode in qla_fw_cds_hdr_t 430 */ 431 #define Q8_FWCD_OPCODE_CONFIG_RSS 0x01 432 #define Q8_FWCD_OPCODE_CONFIG_RSS_TABLE 0x02 433 #define Q8_FWCD_OPCODE_CONFIG_INTR_COALESCING 0x03 434 #define Q8_FWCD_OPCODE_CONFIG_LED 0x04 435 #define Q8_FWCD_OPCODE_CONFIG_MAC_ADDR 0x06 436 #define Q8_FWCD_OPCODE_LRO_FLOW 0x07 437 #define Q8_FWCD_OPCODE_GET_SNMP_STATS 0x08 438 #define Q8_FWCD_OPCODE_CONFIG_MAC_RCV_MODE 0x0C 439 #define Q8_FWCD_OPCODE_STATISTICS 0x10 440 #define Q8_FWCD_OPCODE_CONFIG_IPADDR 0x12 441 #define Q8_FWCD_OPCODE_CONFIG_LOOPBACK 0x13 442 #define Q8_FWCD_OPCODE_LINK_EVENT_REQ 0x15 443 #define Q8_FWCD_OPCODE_CONFIG_BRIDGING 0x17 444 #define Q8_FWCD_OPCODE_CONFIG_LRO 0x18 445 446 /* 447 * Configure RSS 448 */ 449 typedef struct _qla_fw_cds_config_rss { 450 qla_fw_cds_hdr_t hdr; 451 uint8_t hash_type; 452 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) 453 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) 454 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 455 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) 456 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) 457 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 458 459 uint8_t flags; 460 #define Q8_FWCD_RSS_FLAGS_ENABLE_RSS 0x1 461 #define Q8_FWCD_RSS_FLAGS_USE_IND_TABLE 0x2 462 uint8_t rsrvd[4]; 463 uint16_t ind_tbl_mask; 464 uint64_t rss_key[5]; 465 } __packed qla_fw_cds_config_rss_t; 466 467 /* 468 * Configure RSS Table 469 */ 470 typedef struct _qla_fw_cds_config_rss_table { 471 qla_fw_cds_hdr_t hdr; 472 uint64_t index; 473 uint8_t table[40]; 474 } __packed qla_fw_cds_config_rss_table_t; 475 476 /* 477 * Configure Interrupt Coalescing 478 */ 479 typedef struct _qla_fw_cds_config_intr_coalesc { 480 qla_fw_cds_hdr_t hdr; 481 uint16_t rsrvd0; 482 uint16_t rsrvd1; 483 uint16_t flags; 484 uint16_t rsrvd2; 485 uint64_t rsrvd3; 486 uint16_t max_rcv_pkts; 487 uint16_t max_rcv_usecs; 488 uint16_t max_snd_pkts; 489 uint16_t max_snd_usecs; 490 uint64_t rsrvd4; 491 uint64_t rsrvd5; 492 uint32_t usecs_to; 493 uint8_t timer_type; 494 #define Q8_FWCMD_INTR_COALESC_TIMER_NONE 0x00 495 #define Q8_FWCMD_INTR_COALESC_TIMER_ONCE 0x01 496 #define Q8_FWCMD_INTR_COALESC_TIMER_PERIODIC 0x02 497 498 uint8_t sds_ring_bitmask; 499 #define Q8_FWCMD_INTR_COALESC_SDS_RING_0 0x01 500 #define Q8_FWCMD_INTR_COALESC_SDS_RING_1 0x02 501 #define Q8_FWCMD_INTR_COALESC_SDS_RING_2 0x04 502 #define Q8_FWCMD_INTR_COALESC_SDS_RING_3 0x08 503 504 uint16_t rsrvd6; 505 } __packed qla_fw_cds_config_intr_coalesc_t; 506 507 /* 508 * Configure LED Parameters 509 */ 510 typedef struct _qla_fw_cds_config_led { 511 qla_fw_cds_hdr_t hdr; 512 uint32_t cntxt_id; 513 uint32_t blink_rate; 514 uint32_t blink_state; 515 uint32_t rsrvd; 516 } __packed qla_fw_cds_config_led_t; 517 518 /* 519 * Configure MAC Address 520 */ 521 typedef struct _qla_fw_cds_config_mac_addr { 522 qla_fw_cds_hdr_t hdr; 523 uint8_t cmd; 524 #define Q8_FWCD_ADD_MAC_ADDR 0x1 525 #define Q8_FWCD_DEL_MAC_ADDR 0x2 526 uint8_t rsrvd; 527 uint8_t mac_addr[6]; 528 } __packed qla_fw_cds_config_mac_addr_t; 529 530 /* 531 * Configure Add/Delete LRO 532 */ 533 typedef struct _qla_fw_cds_config_lro { 534 qla_fw_cds_hdr_t hdr; 535 uint32_t dst_ip_addr; 536 uint32_t src_ip_addr; 537 uint16_t dst_tcp_port; 538 uint16_t src_tcp_port; 539 uint8_t ipv6; 540 uint8_t time_stamp; 541 uint16_t rsrvd; 542 uint32_t rss_hash; 543 uint32_t host_handle; 544 } __packed qla_fw_cds_config_lro_t; 545 546 /* 547 * Get SNMP Statistics 548 */ 549 typedef struct _qla_fw_cds_get_snmp { 550 qla_fw_cds_hdr_t hdr; 551 uint64_t phys_addr; 552 uint16_t size; 553 uint16_t cntxt_id; 554 uint32_t rsrvd; 555 } __packed qla_fw_cds_get_snmp_t; 556 557 typedef struct _qla_snmp_stats { 558 uint64_t jabber_state; 559 uint64_t false_carrier; 560 uint64_t rsrvd; 561 uint64_t mac_cntrl; 562 uint64_t align_errors; 563 uint64_t chksum_errors; 564 uint64_t oversize_frames; 565 uint64_t tx_errors; 566 uint64_t mac_rcv_errors; 567 uint64_t phy_rcv_errors; 568 uint64_t rcv_pause; 569 uint64_t tx_pause; 570 } __packed qla_snmp_stats_t; 571 572 /* 573 * Enable Link Event Requests 574 */ 575 typedef struct _qla_link_event_req { 576 qla_fw_cds_hdr_t hdr; 577 uint8_t enable; 578 uint8_t get_clnk_params; 579 uint8_t pad[6]; 580 } __packed qla_link_event_req_t; 581 582 /* 583 * Set MAC Receive Mode 584 */ 585 typedef struct _qla_set_mac_rcv_mode { 586 qla_fw_cds_hdr_t hdr; 587 588 uint32_t mode; 589 #define Q8_MAC_RCV_RESET_PROMISC_ALLMULTI 0x00 590 #define Q8_MAC_RCV_ENABLE_PROMISCUOUS 0x01 591 #define Q8_MAC_RCV_ENABLE_ALLMULTI 0x02 592 593 uint8_t pad[4]; 594 } __packed qla_set_mac_rcv_mode_t; 595 596 /* 597 * Configure IP Address 598 */ 599 typedef struct _qla_config_ipv4 { 600 qla_fw_cds_hdr_t hdr; 601 602 uint64_t cmd; 603 #define Q8_CONFIG_CMD_IP_ENABLE 0x02 604 #define Q8_CONFIG_CMD_IP_DISABLE 0x03 605 606 uint64_t ipv4_addr; 607 } __packed qla_config_ipv4_t; 608 609 /* 610 * Configure LRO 611 */ 612 typedef struct _qla_config_lro { 613 qla_fw_cds_hdr_t hdr; 614 615 uint64_t cmd; 616 #define Q8_CONFIG_LRO_ENABLE 0x08 617 } __packed qla_config_lro_t; 618 619 /* 620 * Control Messages Received on SDS Ring 621 */ 622 /* Header */ 623 typedef struct _qla_cntrl_msg_hdr { 624 uint16_t rsrvd0; 625 uint16_t err_code; 626 uint8_t rsp_type; 627 uint8_t comp_id; 628 uint16_t tag; 629 #define Q8_CTRL_MSG_TAG_DESC_COUNT_MASK (0x7 << 5) 630 #define Q8_CTRL_MSG_TAG_OWNER_MASK (0x3 << 8) 631 #define Q8_CTRL_MSG_TAG_OPCODE_MASK (0x3F << 10) 632 } __packed qla_cntrl_msg_hdr_t; 633 634 /* 635 * definitions for rsp_type in qla_cntrl_msg_hdr_t 636 */ 637 #define Q8_CTRL_CONFIG_MAC_RSP 0x85 638 #define Q8_CTRL_LRO_FLOW_DELETE_RSP 0x86 639 #define Q8_CTRL_LRO_FLOW_ADD_FAILURE_RSP 0x87 640 #define Q8_CTRL_GET_SNMP_STATS_RSP 0x88 641 #define Q8_CTRL_GET_NETWORK_STATS_RSP 0x8C 642 #define Q8_CTRL_LINK_EVENT_NOTIFICATION 0x8D 643 644 /* 645 * Configure MAC Response 646 */ 647 typedef struct _qla_config_mac_rsp { 648 uint32_t rval; 649 uint32_t rsrvd; 650 } __packed qla_config_mac_rsp_t; 651 652 /* 653 * LRO Flow Response (can be LRO Flow Delete and LRO Flow Add Failure) 654 */ 655 typedef struct _qla_lro_flow_rsp { 656 uint32_t handle; 657 uint32_t rss_hash; 658 uint32_t dst_ip; 659 uint32_t src_ip; 660 uint16_t dst_tcp_port; 661 uint16_t src_tcp_port; 662 uint8_t ipv6; 663 uint8_t rsrvd0; 664 uint16_t rsrvd1; 665 } __packed qla_lro_flow_rsp_t; 666 667 /* 668 * Get SNMP Statistics Response 669 */ 670 typedef struct _qla_get_snmp_stats_rsp { 671 uint64_t rsrvd; 672 } __packed qla_get_snmp_stats_rsp_t; 673 674 /* 675 * Get Network Statistics Response 676 */ 677 typedef struct _qla_get_net_stats_rsp { 678 uint64_t rsrvd; 679 } __packed qla_get_net_stats_rsp_t; 680 681 /* 682 * Link Event Notification 683 */ 684 typedef struct _qla_link_event { 685 uint32_t cable_oui; 686 uint16_t cable_length; 687 688 uint16_t link_speed; 689 #define Q8_LE_SPEED_MASK 0xFFF 690 #define Q8_LE_SPEED_10GBPS 0x710 691 #define Q8_LE_SPEED_1GBPS 0x3E8 692 #define Q8_LE_SPEED_100MBPS 0x064 693 #define Q8_LE_SPEED_10MBPS 0x00A 694 695 uint8_t link_up;/* 0 = down; else up */ 696 697 uint8_t mod_info; 698 #define Q8_LE_MI_MODULE_NOT_PRESENT 0x01 699 #define Q8_LE_MI_UNKNOWN_OPTICAL_MODULE 0x02 700 #define Q8_LE_MI_SR_LR_OPTICAL_MODULE 0x03 701 #define Q8_LE_MI_LRM_OPTICAL_MODULE 0x04 702 #define Q8_LE_MI_SFP_1G_MODULE 0x05 703 #define Q8_LE_MI_UNSUPPORTED_TWINAX 0x06 704 #define Q8_LE_MI_UNSUPPORTED_TWINAX_LENGTH 0x07 705 #define Q8_LE_MI_SUPPORTED_TWINAX 0x08 706 707 uint8_t fduplex; /* 1 = full duplex; 0 = half duplex */ 708 uint8_t autoneg; /* 1 = autoneg enable; 0 = disabled */ 709 uint32_t rsrvd; 710 } __packed qla_link_event_t; 711 712 typedef struct _qla_sds { 713 q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 714 uint32_t sdsr_next; /* next entry in SDS ring to process */ 715 struct lro_ctrl lro; 716 void *rxb_free; 717 uint32_t rx_free; 718 void *rxjb_free; 719 uint32_t rxj_free; 720 volatile uint32_t rcv_active; 721 } qla_sds_t; 722 723 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ 724 sizeof (struct ip) + sizeof (struct tcphdr) + 16) 725 /* 726 * struct for storing hardware specific information for a given interface 727 */ 728 typedef struct _qla_hw { 729 struct { 730 uint32_t 731 lro :1, 732 init_tx_cnxt :1, 733 init_rx_cnxt :1, 734 fduplex :1, 735 autoneg :1, 736 link_up :1; 737 } flags; 738 739 uint16_t link_speed; 740 uint16_t cable_length; 741 uint16_t cable_oui; 742 uint8_t mod_info; 743 uint8_t rsrvd; 744 745 uint32_t max_rds_per_cntxt; 746 uint32_t max_sds_per_cntxt; 747 uint32_t max_rules_per_cntxt; 748 uint32_t max_rcv_cntxts; 749 uint32_t max_xmt_cntxts; 750 uint32_t max_mtu; 751 uint32_t max_lro; 752 753 uint8_t mac_addr[ETHER_ADDR_LEN]; 754 755 uint16_t num_rds_rings; 756 uint16_t num_sds_rings; 757 758 qla_dmabuf_t dma_buf; 759 760 /* Transmit Side */ 761 762 q80_tx_cmd_t *tx_ring_base; 763 764 q80_tx_cntxt_req_t *tx_cntxt_req; /* TX Context Request */ 765 bus_addr_t tx_cntxt_req_paddr; 766 767 q80_tx_cntxt_rsp_t *tx_cntxt_rsp; /* TX Context Response */ 768 bus_addr_t tx_cntxt_rsp_paddr; 769 770 uint32_t *tx_cons; /* tx consumer shadow reg */ 771 bus_addr_t tx_cons_paddr; 772 773 volatile uint32_t txr_free; /* # of free entries in tx ring */ 774 volatile uint32_t txr_next; /* # next available tx ring entry */ 775 volatile uint32_t txr_comp; /* index of last tx entry completed */ 776 777 uint32_t tx_prod_reg; 778 779 /* Receive Side */ 780 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 781 volatile int32_t rxj_next; /* next jumbo rcv ring to arm fw */ 782 783 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 784 volatile int32_t rxj_in; /* next jumbo rcv ring to add mbufs */ 785 786 q80_rcv_cntxt_req_t *rx_cntxt_req; /* Rcv Context Request */ 787 bus_addr_t rx_cntxt_req_paddr; 788 q80_rcv_cntxt_rsp_t *rx_cntxt_rsp; /* Rcv Context Response */ 789 bus_addr_t rx_cntxt_rsp_paddr; 790 791 qla_sds_t sds[MAX_SDS_RINGS]; 792 793 uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 794 } qla_hw_t; 795 796 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, i, val) \ 797 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\ 798 0x1b2000), val) 799 800 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val) \ 801 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val) 802 803 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 804 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\ 805 0x1b2000), val) 806 807 #define QL_CLEAR_INTERRUPTS(ha) \ 808 if (ha->pci_func == 0) {\ 809 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\ 810 } else {\ 811 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\ 812 }\ 813 814 #define QL_ENABLE_INTERRUPTS(ha, sds_index) \ 815 {\ 816 q80_rsp_sds_ring_t *rsp_sds;\ 817 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\ 818 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\ 819 } 820 821 #define QL_DISABLE_INTERRUPTS(ha, sds_index) \ 822 {\ 823 q80_rsp_sds_ring_t *rsp_sds;\ 824 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\ 825 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\ 826 } 827 828 #define QL_BUFFER_ALIGN 16 829 830 #endif /* #ifndef _QLA_HW_H_ */
Cache object: a58e637da76fa1d419dc303645a0a123
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