1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011-2013 Qlogic Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31 /*
32 * File: qla_inline.h
33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
34 */
35 #ifndef _QLA_INLINE_H_
36 #define _QLA_INLINE_H_
37
38 /*
39 * Function: qla_hw_reset
40 */
41 static __inline void qla_hw_reset(qla_host_t *ha)
42 {
43 WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0xFFFFFFFF);
44 }
45
46 #define QL8_SEMLOCK_TIMEOUT 1000/* QLA8020 Semaphore Lock Timeout 10ms */
47
48 /*
49 * Inline functions for hardware semaphores
50 */
51
52 /*
53 * Name: qla_sem_lock
54 * Function: Locks one of the semaphore registers (semaphore 2,3,5 & 7)
55 * If the id_reg is valid, then id_val is written into it.
56 * This is for debugging purpose
57 * Returns: 0 on success; otherwise its failed.
58 */
59 static __inline int
60 qla_sem_lock(qla_host_t *ha, uint32_t sem_reg, uint32_t id_reg, uint32_t id_val)
61 {
62 int count = QL8_SEMLOCK_TIMEOUT;
63
64 while (count) {
65 if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT))
66 break;
67 count--;
68
69 if (!count)
70 return(-1);
71 qla_mdelay(__func__, 10);
72 }
73 if (id_reg)
74 WRITE_OFFSET32(ha, id_reg, id_val);
75
76 return(0);
77 }
78
79 /*
80 * Name: qla_sem_unlock
81 * Function: Unlocks the semaphore registers (semaphore 2,3,5 & 7)
82 * previously locked by qla_sem_lock()
83 */
84 static __inline void
85 qla_sem_unlock(qla_host_t *ha, uint32_t sem_reg)
86 {
87 READ_REG32(ha, sem_reg);
88 }
89
90 static __inline int
91 qla_get_ifq_snd_maxlen(qla_host_t *ha)
92 {
93 return((NUM_TX_DESCRIPTORS - 1));
94 }
95
96 static __inline uint32_t
97 qla_get_optics(qla_host_t *ha)
98 {
99 uint32_t link_speed;
100
101 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
102 if (ha->pci_func == 0)
103 link_speed = link_speed & 0xFF;
104 else
105 link_speed = (link_speed >> 8) & 0xFF;
106
107 switch (link_speed) {
108 case 0x1:
109 link_speed = IFM_100_FX;
110 break;
111
112 case 0x10:
113 link_speed = IFM_1000_SX;
114 break;
115
116 default:
117 link_speed = (IFM_10G_LR | IFM_10G_SR);
118 break;
119 }
120
121 return(link_speed);
122 }
123
124 static __inline uint8_t *
125 qla_get_mac_addr(qla_host_t *ha)
126 {
127 return (ha->hw.mac_addr);
128 }
129
130 static __inline void
131 qla_read_mac_addr(qla_host_t *ha)
132 {
133 uint32_t mac_crb_addr;
134 uint32_t mac_lo;
135 uint32_t mac_hi;
136 uint8_t *macp;
137
138 mac_crb_addr = Q8_CRB_MAC_BLOCK_START +
139 (((ha->pci_func >> 1) * 3) << 2) + ((ha->pci_func & 0x01) << 2);
140
141 mac_lo = READ_REG32(ha, mac_crb_addr);
142 mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4));
143
144 if (ha->pci_func & 0x01) {
145 mac_lo = mac_lo >> 16;
146
147 macp = (uint8_t *)&mac_lo;
148
149 ha->hw.mac_addr[5] = macp[0];
150 ha->hw.mac_addr[4] = macp[1];
151
152 macp = (uint8_t *)&mac_hi;
153
154 ha->hw.mac_addr[3] = macp[0];
155 ha->hw.mac_addr[2] = macp[1];
156 ha->hw.mac_addr[1] = macp[2];
157 ha->hw.mac_addr[0] = macp[3];
158 } else {
159 macp = (uint8_t *)&mac_lo;
160
161 ha->hw.mac_addr[5] = macp[0];
162 ha->hw.mac_addr[4] = macp[1];
163 ha->hw.mac_addr[3] = macp[2];
164 ha->hw.mac_addr[2] = macp[3];
165
166 macp = (uint8_t *)&mac_hi;
167
168 ha->hw.mac_addr[1] = macp[0];
169 ha->hw.mac_addr[0] = macp[1];
170 }
171 return;
172 }
173
174 static __inline void
175 qla_set_hw_rcv_desc(qla_host_t *ha, uint32_t ridx, uint32_t index,
176 uint32_t handle, bus_addr_t paddr, uint32_t buf_size)
177 {
178 q80_recv_desc_t *rcv_desc;
179
180 rcv_desc = (q80_recv_desc_t *)ha->hw.dma_buf.rds_ring[ridx].dma_b;
181
182 rcv_desc += index;
183
184 rcv_desc->handle = (uint16_t)handle;
185 rcv_desc->buf_size = buf_size;
186 rcv_desc->buf_addr = paddr;
187
188 return;
189 }
190
191 static __inline void
192 qla_init_hw_rcv_descriptors(qla_host_t *ha, uint32_t ridx)
193 {
194 if (ridx == RDS_RING_INDEX_NORMAL)
195 bzero((void *)ha->hw.dma_buf.rds_ring[ridx].dma_b,
196 (sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS));
197 else if (ridx == RDS_RING_INDEX_JUMBO)
198 bzero((void *)ha->hw.dma_buf.rds_ring[ridx].dma_b,
199 (sizeof(q80_recv_desc_t) * NUM_RX_JUMBO_DESCRIPTORS));
200 else
201 QL_ASSERT(0, ("%s: invalid rds index [%d]\n", __func__, ridx));
202 }
203
204 static __inline void
205 qla_lock(qla_host_t *ha, const char *str)
206 {
207 while (1) {
208 mtx_lock(&ha->hw_lock);
209 if (!ha->hw_lock_held) {
210 ha->hw_lock_held = 1;
211 ha->qla_lock = str;
212 mtx_unlock(&ha->hw_lock);
213 break;
214 }
215 mtx_unlock(&ha->hw_lock);
216 qla_mdelay(__func__, 1);
217 }
218 return;
219 }
220
221 static __inline void
222 qla_unlock(qla_host_t *ha, const char *str)
223 {
224 mtx_lock(&ha->hw_lock);
225 ha->hw_lock_held = 0;
226 ha->qla_unlock = str;
227 mtx_unlock(&ha->hw_lock);
228 }
229
230 #endif /* #ifndef _QLA_INLINE_H_ */
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