1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2016 Qlogic Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31 /*
32 * File: ql_ioctl.h
33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
34 */
35
36 #ifndef _QL_IOCTL_H_
37 #define _QL_IOCTL_H_
38
39 #include <sys/ioccom.h>
40
41 struct qla_reg_val {
42 uint16_t rd;
43 uint16_t direct;
44 uint32_t reg;
45 uint32_t val;
46 };
47 typedef struct qla_reg_val qla_reg_val_t;
48
49 struct qla_rd_flash {
50 uint32_t off;
51 uint32_t data;
52 };
53 typedef struct qla_rd_flash qla_rd_flash_t;
54
55 struct qla_wr_flash {
56 uint32_t off;
57 uint32_t size;
58 void *buffer;
59 uint32_t pattern;
60 };
61 typedef struct qla_wr_flash qla_wr_flash_t;
62
63 struct qla_erase_flash {
64 uint32_t off;
65 uint32_t size;
66 };
67 typedef struct qla_erase_flash qla_erase_flash_t;
68
69 struct qla_rd_pci_ids {
70 uint16_t ven_id;
71 uint16_t dev_id;
72 uint16_t subsys_ven_id;
73 uint16_t subsys_dev_id;
74 uint8_t rev_id;
75 };
76 typedef struct qla_rd_pci_ids qla_rd_pci_ids_t;
77
78 #define NUM_LOG_ENTRY_PARAMS 5
79 #define NUM_LOG_ENTRIES 512
80
81 struct qla_sp_log_entry {
82 uint32_t fmtstr_idx;
83 uint32_t num_params;
84 uint64_t usec_ts;
85 uint32_t params[NUM_LOG_ENTRY_PARAMS];
86 };
87 typedef struct qla_sp_log_entry qla_sp_log_entry_t;
88
89 /*
90 * structure encapsulating the value to read/write from/to offchip (MS) memory
91 */
92 struct qla_offchip_mem_val {
93 uint16_t rd;
94 uint64_t off;
95 uint32_t data_lo;
96 uint32_t data_hi;
97 uint32_t data_ulo;
98 uint32_t data_uhi;
99 };
100 typedef struct qla_offchip_mem_val qla_offchip_mem_val_t;
101
102 struct qla_rd_fw_dump {
103 uint16_t pci_func;
104 uint16_t saved;
105 uint64_t usec_ts;
106 uint32_t minidump_size;
107 void *minidump;
108 };
109 typedef struct qla_rd_fw_dump qla_rd_fw_dump_t;
110
111 struct qla_drvr_state_tx {
112 uint64_t base_p_addr;
113 uint64_t cons_p_addr;
114 uint32_t tx_prod_reg;
115 uint32_t tx_cntxt_id;
116 uint32_t txr_free;
117 uint32_t txr_next;
118 uint32_t txr_comp;
119 };
120 typedef struct qla_drvr_state_tx qla_drvr_state_tx_t;
121
122 struct qla_drvr_state_sds {
123 uint32_t sdsr_next; /* next entry in SDS ring to process */
124 uint32_t sds_consumer;
125 };
126 typedef struct qla_drvr_state_sds qla_drvr_state_sds_t;
127
128 struct qla_drvr_state_rx {
129 uint32_t prod_std;
130 uint32_t rx_next; /* next standard rcv ring to arm fw */;
131 };
132 typedef struct qla_drvr_state_rx qla_drvr_state_rx_t;
133
134 struct qla_drvr_state_hdr {
135 uint32_t drvr_version_major;
136 uint32_t drvr_version_minor;
137 uint32_t drvr_version_build;
138
139 uint8_t mac_addr[ETHER_ADDR_LEN];
140 uint16_t saved;
141 uint64_t usec_ts;
142 uint16_t link_speed;
143 uint16_t cable_length;
144 uint32_t cable_oui;
145 uint8_t link_up;
146 uint8_t module_type;
147 uint8_t link_faults;
148 uint32_t rcv_intr_coalesce;
149 uint32_t xmt_intr_coalesce;
150
151 uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */
152 uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */
153 uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */
154
155 uint32_t num_tx_rings; /* number of tx rings */
156 uint32_t txr_size; /* size of each tx ring in bytes */
157 uint32_t txr_entries; /* number of descriptors in each tx ring */
158 uint32_t txr_offset; /* start of tx ring [0 - #rings] content */
159
160 uint32_t num_rx_rings; /* number of rx rings */
161 uint32_t rxr_size; /* size of each rx ring in bytes */
162 uint32_t rxr_entries; /* number of descriptors in each rx ring */
163 uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */
164
165 uint32_t num_sds_rings; /* number of sds rings */
166 uint32_t sds_ring_size; /* size of each sds ring in bytes */
167 uint32_t sds_entries; /* number of descriptors in each sds ring */
168 uint32_t sds_offset; /* start of sds ring [0 - #rings] content */
169 };
170
171 typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t;
172
173 struct qla_driver_state {
174 uint32_t size;
175 void *buffer;
176 };
177 typedef struct qla_driver_state qla_driver_state_t;
178
179 struct qla_sp_log {
180 uint32_t next_idx; /* index of next entry in slowpath trace log */
181 uint32_t num_entries; /* number of entries in slowpath trace log */
182 void *buffer;
183 };
184 typedef struct qla_sp_log qla_sp_log_t;
185
186 /*
187 * Read/Write Register
188 */
189 #define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t)
190
191 /*
192 * Read Flash
193 */
194 #define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t)
195
196 /*
197 * Write Flash
198 */
199 #define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t)
200
201 /*
202 * Read Offchip (MS) Memory
203 */
204 #define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t)
205
206 /*
207 * Erase Flash
208 */
209 #define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t)
210
211 /*
212 * Read PCI IDs
213 */
214 #define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t)
215
216 /*
217 * Read Minidump Template Size
218 */
219 #define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t)
220
221 /*
222 * Read Minidump Template
223 */
224 #define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t)
225
226 /*
227 * Read Driver State
228 */
229 #define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t)
230
231 /*
232 * Read Slowpath Log
233 */
234 #define QLA_RD_SLOWPATH_LOG _IOWR('q', 10, qla_sp_log_t)
235
236 /*
237 * Format Strings For Slowpath Trace Logs
238 */
239 #define SP_TLOG_FMT_STR_0 \
240 "qla_mbx_cmd [%ld]: enter no_pause = %d [0x%08x 0x%08x 0x%08x 0x%08x]\n"
241
242 #define SP_TLOG_FMT_STR_1 \
243 "qla_mbx_cmd [%ld]: offline = 0x%08x qla_initiate_recovery = 0x%08x exit1\n"
244
245 #define SP_TLOG_FMT_STR_2 \
246 "qla_mbx_cmd [%ld]: qla_initiate_recovery = 0x%08x exit2\n"
247
248 #define SP_TLOG_FMT_STR_3 \
249 "qla_mbx_cmd [%ld]: timeout exit3 [host_mbx_cntrl = 0x%08x]\n"
250
251 #define SP_TLOG_FMT_STR_4 \
252 "qla_mbx_cmd [%ld]: qla_initiate_recovery = 0x%08x exit4\n"
253
254 #define SP_TLOG_FMT_STR_5 \
255 "qla_mbx_cmd [%ld]: timeout exit5 [fw_mbx_cntrl = 0x%08x]\n"
256
257 #define SP_TLOG_FMT_STR_6 \
258 "qla_mbx_cmd [%ld]: qla_initiate_recovery = 0x%08x exit6\n"
259
260 #define SP_TLOG_FMT_STR_7 \
261 "qla_mbx_cmd [%ld]: exit [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n"
262
263 #define SP_TLOG_FMT_STR_8 \
264 "qla_ioctl [%ld]: SIOCSIFADDR if_drv_flags = 0x%08x [0x%08x] ipv4 = 0x%08x\n"
265
266 #define SP_TLOG_FMT_STR_9 \
267 "qla_ioctl [%ld]: SIOCSIFMTU if_drv_flags = 0x%08x [0x%08x] max_frame_size = 0x%08x if_mtu = 0x%08x\n"
268
269 #define SP_TLOG_FMT_STR_10 \
270 "qla_ioctl [%ld]: SIOCSIFFLAGS if_drv_flags = 0x%08x [0x%08x] ha->if_flags = 0x%08x ifp->if_flags = 0x%08x\n"
271
272 #define SP_TLOG_FMT_STR_11 \
273 "qla_ioctl [%ld]: SIOCSIFCAP if_drv_flags = 0x%08x [0x%08x] mask = 0x%08x ifp->if_capenable = 0x%08x\n"
274
275 #define SP_TLOG_FMT_STR_12 \
276 "qla_set_multi [%ld]: if_drv_flags = 0x%08x [0x%08x] add_multi = 0x%08x mcnt = 0x%08x\n"
277
278 #define SP_TLOG_FMT_STR_13 \
279 "qla_stop [%ld]: \n"
280
281 #define SP_TLOG_FMT_STR_14 \
282 "qla_init_locked [%ld]: \n"
283
284 #endif /* #ifndef _QL_IOCTL_H_ */
Cache object: 4394a865832de585dd865bbe909625e9
|