1 /*
2 * Copyright (c) 2013-2014 Qlogic Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 /*
31 * File: qls_def.h
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 */
34
35 #ifndef _QLS_DEF_H_
36 #define _QLS_DEF_H_
37
38 /*
39 * structure encapsulating a DMA buffer
40 */
41 struct qla_dma {
42 bus_size_t alignment;
43 uint32_t size;
44 void *dma_b;
45 bus_addr_t dma_addr;
46 bus_dmamap_t dma_map;
47 bus_dma_tag_t dma_tag;
48 };
49 typedef struct qla_dma qla_dma_t;
50
51 /*
52 * structure encapsulating interrupt vectors
53 */
54 struct qla_ivec {
55 uint32_t cq_idx;
56 void *ha;
57 struct resource *irq;
58 void *handle;
59 int irq_rid;
60 };
61 typedef struct qla_ivec qla_ivec_t;
62
63 /*
64 * Transmit Related Definitions
65 */
66
67 #define MAX_TX_RINGS 1
68 #define NUM_TX_DESCRIPTORS 1024
69
70 #define QLA_MAX_SEGMENTS 64 /* maximum # of segs in a sg list */
71 #define QLA_OAL_BLK_SIZE (sizeof (q81_txb_desc_t) * QLA_MAX_SEGMENTS)
72
73 #define QLA_TX_OALB_TOTAL_SIZE (NUM_TX_DESCRIPTORS * QLA_OAL_BLK_SIZE)
74
75 #define QLA_TX_PRIVATE_BSIZE ((QLA_TX_OALB_TOTAL_SIZE + \
76 PAGE_SIZE + \
77 (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
78
79 #define QLA_MAX_MTU 9000
80 #define QLA_STD_FRAME_SIZE 1514
81 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
82
83 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
84 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
85
86 struct qla_tx_buf {
87 struct mbuf *m_head;
88 bus_dmamap_t map;
89
90 /* The number of entries in the OAL is determined by QLA_MAX_SEGMENTS */
91 bus_addr_t oal_paddr;
92 void *oal_vaddr;
93 };
94 typedef struct qla_tx_buf qla_tx_buf_t;
95
96 struct qla_tx_ring {
97
98 volatile struct {
99 uint32_t wq_dma:1,
100 privb_dma:1;
101 } flags;
102
103 qla_dma_t privb_dma;
104 qla_dma_t wq_dma;
105
106 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
107 uint64_t count;
108
109 struct resource *wq_db_addr;
110 uint32_t wq_db_offset;
111
112 q81_tx_cmd_t *wq_vaddr;
113 bus_addr_t wq_paddr;
114
115 void *wq_icb_vaddr;
116 bus_addr_t wq_icb_paddr;
117
118 uint32_t *txr_cons_vaddr;
119 bus_addr_t txr_cons_paddr;
120
121 volatile uint32_t txr_free; /* # of free entries in tx ring */
122 volatile uint32_t txr_next; /* # next available tx ring entry */
123 volatile uint32_t txr_done;
124
125 uint64_t tx_frames;
126 uint64_t tx_tso_frames;
127 uint64_t tx_vlan_frames;
128 };
129 typedef struct qla_tx_ring qla_tx_ring_t;
130
131 /*
132 * Receive Related Definitions
133 */
134
135 #define MAX_RX_RINGS MAX_TX_RINGS
136
137 #define NUM_RX_DESCRIPTORS 1024
138 #define NUM_CQ_ENTRIES NUM_RX_DESCRIPTORS
139
140 #define QLA_LGB_SIZE (12 * 1024)
141 #define QLA_NUM_LGB_ENTRIES 32
142
143 #define QLA_LBQ_SIZE (QLA_NUM_LGB_ENTRIES * sizeof(q81_bq_addr_e_t))
144
145 #define QLA_LGBQ_AND_TABLE_SIZE \
146 ((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
147
148
149 /* Please note that Small Buffer size is determined by max mtu size */
150 #define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS
151
152 #define QLA_SBQ_SIZE (QLA_NUM_SMB_ENTRIES * sizeof(q81_bq_addr_e_t))
153
154 #define QLA_SMBQ_AND_TABLE_SIZE \
155 ((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
156
157 struct qla_rx_buf {
158 struct mbuf *m_head;
159 bus_dmamap_t map;
160 bus_addr_t paddr;
161 void *next;
162 };
163 typedef struct qla_rx_buf qla_rx_buf_t;
164
165 struct qla_rx_ring {
166 volatile struct {
167 uint32_t cq_dma:1,
168 lbq_dma:1,
169 sbq_dma:1,
170 lb_dma:1;
171 } flags;
172
173 qla_dma_t cq_dma;
174 qla_dma_t lbq_dma;
175 qla_dma_t sbq_dma;
176 qla_dma_t lb_dma;
177
178 struct lro_ctrl lro;
179
180 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
181 qla_rx_buf_t *rxb_free;
182 uint32_t rx_free;
183 uint32_t rx_next;
184
185 uint32_t cq_db_offset;
186
187 void *cq_icb_vaddr;
188 bus_addr_t cq_icb_paddr;
189
190 uint32_t *cqi_vaddr;
191 bus_addr_t cqi_paddr;
192
193 void *cq_base_vaddr;
194 bus_addr_t cq_base_paddr;
195 uint32_t cq_next; /* next cq entry to process */
196
197 void *lbq_addr_tbl_vaddr;
198 bus_addr_t lbq_addr_tbl_paddr;
199
200 void *lbq_vaddr;
201 bus_addr_t lbq_paddr;
202 uint32_t lbq_next; /* next entry in LBQ to process */
203 uint32_t lbq_free;/* # of entries in LBQ to arm */
204 uint32_t lbq_in; /* next entry in LBQ to arm */
205
206 void *lb_vaddr;
207 bus_addr_t lb_paddr;
208
209 void *sbq_addr_tbl_vaddr;
210 bus_addr_t sbq_addr_tbl_paddr;
211
212 void *sbq_vaddr;
213 bus_addr_t sbq_paddr;
214 uint32_t sbq_next; /* next entry in SBQ to process */
215 uint32_t sbq_free;/* # of entries in SBQ to arm */
216 uint32_t sbq_in; /* next entry in SBQ to arm */
217
218 uint64_t rx_int;
219 uint64_t rss_int;
220 };
221 typedef struct qla_rx_ring qla_rx_ring_t;
222
223
224 #define QLA_WATCHDOG_CALLOUT_TICKS 1
225
226 /*
227 * Multicast Definitions
228 */
229 typedef struct _qla_mcast {
230 uint16_t rsrvd;
231 uint8_t addr[6];
232 } __packed qla_mcast_t;
233
234 /*
235 * Misc. definitions
236 */
237 #define QLA_PAGE_SIZE 4096
238
239 /*
240 * Adapter structure contains the hardware independant information of the
241 * pci function.
242 */
243 struct qla_host {
244 volatile struct {
245 volatile uint32_t
246 mpi_dma :1,
247 rss_dma :1,
248 intr_enable :1,
249 qla_callout_init :1,
250 qla_watchdog_active :1,
251 qla_watchdog_exit :1,
252 qla_watchdog_pause :1,
253 lro_init :1,
254 parent_tag :1,
255 lock_init :1;
256 } flags;
257
258 volatile uint32_t hw_init;
259
260 volatile uint32_t qla_watchdog_exited;
261 volatile uint32_t qla_watchdog_paused;
262 volatile uint32_t qla_initiate_recovery;
263
264 device_t pci_dev;
265
266 uint8_t pci_func;
267 uint16_t watchdog_ticks;
268 uint8_t resvd;
269
270 /* ioctl related */
271 struct cdev *ioctl_dev;
272
273 /* register mapping */
274 struct resource *pci_reg;
275 int reg_rid;
276
277 struct resource *pci_reg1;
278 int reg_rid1;
279
280 int msix_count;
281 qla_ivec_t irq_vec[MAX_RX_RINGS];
282
283 /* parent dma tag */
284 bus_dma_tag_t parent_tag;
285
286 /* interface to o.s */
287 struct ifnet *ifp;
288
289 struct ifmedia media;
290 uint16_t max_frame_size;
291 uint16_t rsrvd0;
292 uint32_t msize;
293 int if_flags;
294
295 /* hardware access lock */
296 struct mtx hw_lock;
297 volatile uint32_t hw_lock_held;
298
299 uint32_t vm_pgsize;
300 /* transmit related */
301 uint32_t num_tx_rings;
302 qla_tx_ring_t tx_ring[MAX_TX_RINGS];
303
304 bus_dma_tag_t tx_tag;
305 struct task tx_task;
306 struct taskqueue *tx_tq;
307 struct callout tx_callout;
308 struct mtx tx_lock;
309
310 /* receive related */
311 uint32_t num_rx_rings;
312 qla_rx_ring_t rx_ring[MAX_RX_RINGS];
313 bus_dma_tag_t rx_tag;
314
315 /* stats */
316 uint32_t err_m_getcl;
317 uint32_t err_m_getjcl;
318 uint32_t err_tx_dmamap_create;
319 uint32_t err_tx_dmamap_load;
320 uint32_t err_tx_defrag;
321
322 /* mac address related */
323 uint8_t mac_rcv_mode;
324 uint8_t mac_addr[ETHER_ADDR_LEN];
325 uint32_t nmcast;
326 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
327
328 /* Link Related */
329 uint8_t link_up;
330 uint32_t link_status;
331 uint32_t link_down_info;
332 uint32_t link_hw_info;
333 uint32_t link_dcbx_counters;
334 uint32_t link_change_counters;
335
336 /* Flash Related */
337 q81_flash_t flash;
338
339 /* debug stuff */
340 volatile const char *qla_lock;
341 volatile const char *qla_unlock;
342
343 /* Error Recovery Related */
344 uint32_t err_inject;
345 struct task err_task;
346 struct taskqueue *err_tq;
347
348 /* Chip related */
349 uint32_t rev_id;
350
351 /* mailbox completions */
352 uint32_t aen[Q81_NUM_AEN_REGISTERS];
353 uint32_t mbox[Q81_NUM_MBX_REGISTERS];
354 volatile uint32_t mbx_done;
355
356 /* mpi dump related */
357 qla_dma_t mpi_dma;
358 qla_dma_t rss_dma;
359
360 };
361 typedef struct qla_host qla_host_t;
362
363 /* note that align has to be a power of 2 */
364 #define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
365 #define QL_MIN(x, y) ((x < y) ? x : y)
366
367 #define QL_RUNNING(ifp) \
368 ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
369 IFF_DRV_RUNNING)
370
371 /* Return 0, if identical, else 1 */
372
373 #define QL_MAC_CMP(mac1, mac2) \
374 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
375 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
376
377 #endif /* #ifndef _QLS_DEF_H_ */
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