1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2014 Qlogic Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/12.0/sys/dev/qlxge/qls_def.h 326255 2017-11-27 14:52:40Z pfg $
30 */
31
32 /*
33 * File: qls_def.h
34 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
35 */
36
37 #ifndef _QLS_DEF_H_
38 #define _QLS_DEF_H_
39
40 /*
41 * structure encapsulating a DMA buffer
42 */
43 struct qla_dma {
44 bus_size_t alignment;
45 uint32_t size;
46 void *dma_b;
47 bus_addr_t dma_addr;
48 bus_dmamap_t dma_map;
49 bus_dma_tag_t dma_tag;
50 };
51 typedef struct qla_dma qla_dma_t;
52
53 /*
54 * structure encapsulating interrupt vectors
55 */
56 struct qla_ivec {
57 uint32_t cq_idx;
58 void *ha;
59 struct resource *irq;
60 void *handle;
61 int irq_rid;
62 };
63 typedef struct qla_ivec qla_ivec_t;
64
65 /*
66 * Transmit Related Definitions
67 */
68
69 #define MAX_TX_RINGS 1
70 #define NUM_TX_DESCRIPTORS 1024
71
72 #define QLA_MAX_SEGMENTS 64 /* maximum # of segs in a sg list */
73 #define QLA_OAL_BLK_SIZE (sizeof (q81_txb_desc_t) * QLA_MAX_SEGMENTS)
74
75 #define QLA_TX_OALB_TOTAL_SIZE (NUM_TX_DESCRIPTORS * QLA_OAL_BLK_SIZE)
76
77 #define QLA_TX_PRIVATE_BSIZE ((QLA_TX_OALB_TOTAL_SIZE + \
78 PAGE_SIZE + \
79 (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
80
81 #define QLA_MAX_MTU 9000
82 #define QLA_STD_FRAME_SIZE 1514
83 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
84
85 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
86 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
87
88 struct qla_tx_buf {
89 struct mbuf *m_head;
90 bus_dmamap_t map;
91
92 /* The number of entries in the OAL is determined by QLA_MAX_SEGMENTS */
93 bus_addr_t oal_paddr;
94 void *oal_vaddr;
95 };
96 typedef struct qla_tx_buf qla_tx_buf_t;
97
98 struct qla_tx_ring {
99
100 volatile struct {
101 uint32_t wq_dma:1,
102 privb_dma:1;
103 } flags;
104
105 qla_dma_t privb_dma;
106 qla_dma_t wq_dma;
107
108 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
109 uint64_t count;
110
111 struct resource *wq_db_addr;
112 uint32_t wq_db_offset;
113
114 q81_tx_cmd_t *wq_vaddr;
115 bus_addr_t wq_paddr;
116
117 void *wq_icb_vaddr;
118 bus_addr_t wq_icb_paddr;
119
120 uint32_t *txr_cons_vaddr;
121 bus_addr_t txr_cons_paddr;
122
123 volatile uint32_t txr_free; /* # of free entries in tx ring */
124 volatile uint32_t txr_next; /* # next available tx ring entry */
125 volatile uint32_t txr_done;
126
127 uint64_t tx_frames;
128 uint64_t tx_tso_frames;
129 uint64_t tx_vlan_frames;
130 };
131 typedef struct qla_tx_ring qla_tx_ring_t;
132
133 /*
134 * Receive Related Definitions
135 */
136
137 #define MAX_RX_RINGS MAX_TX_RINGS
138
139 #define NUM_RX_DESCRIPTORS 1024
140 #define NUM_CQ_ENTRIES NUM_RX_DESCRIPTORS
141
142 #define QLA_LGB_SIZE (12 * 1024)
143 #define QLA_NUM_LGB_ENTRIES 32
144
145 #define QLA_LBQ_SIZE (QLA_NUM_LGB_ENTRIES * sizeof(q81_bq_addr_e_t))
146
147 #define QLA_LGBQ_AND_TABLE_SIZE \
148 ((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
149
150
151 /* Please note that Small Buffer size is determined by max mtu size */
152 #define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS
153
154 #define QLA_SBQ_SIZE (QLA_NUM_SMB_ENTRIES * sizeof(q81_bq_addr_e_t))
155
156 #define QLA_SMBQ_AND_TABLE_SIZE \
157 ((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
158
159 struct qla_rx_buf {
160 struct mbuf *m_head;
161 bus_dmamap_t map;
162 bus_addr_t paddr;
163 void *next;
164 };
165 typedef struct qla_rx_buf qla_rx_buf_t;
166
167 struct qla_rx_ring {
168 volatile struct {
169 uint32_t cq_dma:1,
170 lbq_dma:1,
171 sbq_dma:1,
172 lb_dma:1;
173 } flags;
174
175 qla_dma_t cq_dma;
176 qla_dma_t lbq_dma;
177 qla_dma_t sbq_dma;
178 qla_dma_t lb_dma;
179
180 struct lro_ctrl lro;
181
182 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
183 qla_rx_buf_t *rxb_free;
184 uint32_t rx_free;
185 uint32_t rx_next;
186
187 uint32_t cq_db_offset;
188
189 void *cq_icb_vaddr;
190 bus_addr_t cq_icb_paddr;
191
192 uint32_t *cqi_vaddr;
193 bus_addr_t cqi_paddr;
194
195 void *cq_base_vaddr;
196 bus_addr_t cq_base_paddr;
197 uint32_t cq_next; /* next cq entry to process */
198
199 void *lbq_addr_tbl_vaddr;
200 bus_addr_t lbq_addr_tbl_paddr;
201
202 void *lbq_vaddr;
203 bus_addr_t lbq_paddr;
204 uint32_t lbq_next; /* next entry in LBQ to process */
205 uint32_t lbq_free;/* # of entries in LBQ to arm */
206 uint32_t lbq_in; /* next entry in LBQ to arm */
207
208 void *lb_vaddr;
209 bus_addr_t lb_paddr;
210
211 void *sbq_addr_tbl_vaddr;
212 bus_addr_t sbq_addr_tbl_paddr;
213
214 void *sbq_vaddr;
215 bus_addr_t sbq_paddr;
216 uint32_t sbq_next; /* next entry in SBQ to process */
217 uint32_t sbq_free;/* # of entries in SBQ to arm */
218 uint32_t sbq_in; /* next entry in SBQ to arm */
219
220 uint64_t rx_int;
221 uint64_t rss_int;
222 };
223 typedef struct qla_rx_ring qla_rx_ring_t;
224
225
226 #define QLA_WATCHDOG_CALLOUT_TICKS 1
227
228 /*
229 * Multicast Definitions
230 */
231 typedef struct _qla_mcast {
232 uint16_t rsrvd;
233 uint8_t addr[6];
234 } __packed qla_mcast_t;
235
236 /*
237 * Misc. definitions
238 */
239 #define QLA_PAGE_SIZE 4096
240
241 /*
242 * Adapter structure contains the hardware independent information of the
243 * pci function.
244 */
245 struct qla_host {
246 volatile struct {
247 volatile uint32_t
248 mpi_dma :1,
249 rss_dma :1,
250 intr_enable :1,
251 qla_callout_init :1,
252 qla_watchdog_active :1,
253 qla_watchdog_exit :1,
254 qla_watchdog_pause :1,
255 lro_init :1,
256 parent_tag :1,
257 lock_init :1;
258 } flags;
259
260 volatile uint32_t hw_init;
261
262 volatile uint32_t qla_watchdog_exited;
263 volatile uint32_t qla_watchdog_paused;
264 volatile uint32_t qla_initiate_recovery;
265
266 device_t pci_dev;
267
268 uint8_t pci_func;
269 uint16_t watchdog_ticks;
270 uint8_t resvd;
271
272 /* ioctl related */
273 struct cdev *ioctl_dev;
274
275 /* register mapping */
276 struct resource *pci_reg;
277 int reg_rid;
278
279 struct resource *pci_reg1;
280 int reg_rid1;
281
282 int msix_count;
283 qla_ivec_t irq_vec[MAX_RX_RINGS];
284
285 /* parent dma tag */
286 bus_dma_tag_t parent_tag;
287
288 /* interface to o.s */
289 struct ifnet *ifp;
290
291 struct ifmedia media;
292 uint16_t max_frame_size;
293 uint16_t rsrvd0;
294 uint32_t msize;
295 int if_flags;
296
297 /* hardware access lock */
298 struct mtx hw_lock;
299 volatile uint32_t hw_lock_held;
300
301 uint32_t vm_pgsize;
302 /* transmit related */
303 uint32_t num_tx_rings;
304 qla_tx_ring_t tx_ring[MAX_TX_RINGS];
305
306 bus_dma_tag_t tx_tag;
307 struct task tx_task;
308 struct taskqueue *tx_tq;
309 struct callout tx_callout;
310 struct mtx tx_lock;
311
312 /* receive related */
313 uint32_t num_rx_rings;
314 qla_rx_ring_t rx_ring[MAX_RX_RINGS];
315 bus_dma_tag_t rx_tag;
316
317 /* stats */
318 uint32_t err_m_getcl;
319 uint32_t err_m_getjcl;
320 uint32_t err_tx_dmamap_create;
321 uint32_t err_tx_dmamap_load;
322 uint32_t err_tx_defrag;
323
324 /* mac address related */
325 uint8_t mac_rcv_mode;
326 uint8_t mac_addr[ETHER_ADDR_LEN];
327 uint32_t nmcast;
328 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
329
330 /* Link Related */
331 uint8_t link_up;
332 uint32_t link_status;
333 uint32_t link_down_info;
334 uint32_t link_hw_info;
335 uint32_t link_dcbx_counters;
336 uint32_t link_change_counters;
337
338 /* Flash Related */
339 q81_flash_t flash;
340
341 /* debug stuff */
342 volatile const char *qla_lock;
343 volatile const char *qla_unlock;
344
345 /* Error Recovery Related */
346 uint32_t err_inject;
347 struct task err_task;
348 struct taskqueue *err_tq;
349
350 /* Chip related */
351 uint32_t rev_id;
352
353 /* mailbox completions */
354 uint32_t aen[Q81_NUM_AEN_REGISTERS];
355 uint32_t mbox[Q81_NUM_MBX_REGISTERS];
356 volatile uint32_t mbx_done;
357
358 /* mpi dump related */
359 qla_dma_t mpi_dma;
360 qla_dma_t rss_dma;
361
362 };
363 typedef struct qla_host qla_host_t;
364
365 /* note that align has to be a power of 2 */
366 #define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1)))
367 #define QL_MIN(x, y) ((x < y) ? x : y)
368
369 #define QL_RUNNING(ifp) \
370 ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
371 IFF_DRV_RUNNING)
372
373 /* Return 0, if identical, else 1 */
374
375 #define QL_MAC_CMP(mac1, mac2) \
376 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
377 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
378
379 #endif /* #ifndef _QLS_DEF_H_ */
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