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sys/dev/qlxge/qls_dump.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: qls_dump.c 32 */ 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "qls_os.h" 37 #include "qls_hw.h" 38 #include "qls_def.h" 39 #include "qls_glbl.h" 40 #include "qls_dump.h" 41 42 qls_mpi_coredump_t ql_mpi_coredump; 43 44 #define Q81_CORE_SEG_NUM 1 45 #define Q81_TEST_LOGIC_SEG_NUM 2 46 #define Q81_RMII_SEG_NUM 3 47 #define Q81_FCMAC1_SEG_NUM 4 48 #define Q81_FCMAC2_SEG_NUM 5 49 #define Q81_FC1_MBOX_SEG_NUM 6 50 #define Q81_IDE_SEG_NUM 7 51 #define Q81_NIC1_MBOX_SEG_NUM 8 52 #define Q81_SMBUS_SEG_NUM 9 53 #define Q81_FC2_MBOX_SEG_NUM 10 54 #define Q81_NIC2_MBOX_SEG_NUM 11 55 #define Q81_I2C_SEG_NUM 12 56 #define Q81_MEMC_SEG_NUM 13 57 #define Q81_PBUS_SEG_NUM 14 58 #define Q81_MDE_SEG_NUM 15 59 #define Q81_NIC1_CONTROL_SEG_NUM 16 60 #define Q81_NIC2_CONTROL_SEG_NUM 17 61 #define Q81_NIC1_XGMAC_SEG_NUM 18 62 #define Q81_NIC2_XGMAC_SEG_NUM 19 63 #define Q81_WCS_RAM_SEG_NUM 20 64 #define Q81_MEMC_RAM_SEG_NUM 21 65 #define Q81_XAUI1_AN_SEG_NUM 22 66 #define Q81_XAUI1_HSS_PCS_SEG_NUM 23 67 #define Q81_XFI1_AN_SEG_NUM 24 68 #define Q81_XFI1_TRAIN_SEG_NUM 25 69 #define Q81_XFI1_HSS_PCS_SEG_NUM 26 70 #define Q81_XFI1_HSS_TX_SEG_NUM 27 71 #define Q81_XFI1_HSS_RX_SEG_NUM 28 72 #define Q81_XFI1_HSS_PLL_SEG_NUM 29 73 #define Q81_INTR_STATES_SEG_NUM 31 74 #define Q81_ETS_SEG_NUM 34 75 #define Q81_PROBE_DUMP_SEG_NUM 35 76 #define Q81_ROUTING_INDEX_SEG_NUM 36 77 #define Q81_MAC_PROTOCOL_SEG_NUM 37 78 #define Q81_XAUI2_AN_SEG_NUM 38 79 #define Q81_XAUI2_HSS_PCS_SEG_NUM 39 80 #define Q81_XFI2_AN_SEG_NUM 40 81 #define Q81_XFI2_TRAIN_SEG_NUM 41 82 #define Q81_XFI2_HSS_PCS_SEG_NUM 42 83 #define Q81_XFI2_HSS_TX_SEG_NUM 43 84 #define Q81_XFI2_HSS_RX_SEG_NUM 44 85 #define Q81_XFI2_HSS_PLL_SEG_NUM 45 86 #define Q81_WQC1_SEG_NUM 46 87 #define Q81_CQC1_SEG_NUM 47 88 #define Q81_WQC2_SEG_NUM 48 89 #define Q81_CQC2_SEG_NUM 49 90 #define Q81_SEM_REGS_SEG_NUM 50 91 92 enum 93 { 94 Q81_PAUSE_SRC_LO = 0x00000100, 95 Q81_PAUSE_SRC_HI = 0x00000104, 96 Q81_GLOBAL_CFG = 0x00000108, 97 Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/ 98 Q81_GLOBAL_CFG_JUMBO = (1 << 6), /*Control*/ 99 Q81_GLOBAL_CFG_TX_STAT_EN = (1 << 10), /*Control*/ 100 Q81_GLOBAL_CFG_RX_STAT_EN = (1 << 11), /*Control*/ 101 Q81_TX_CFG = 0x0000010c, 102 Q81_TX_CFG_RESET = (1 << 0), /*Control*/ 103 Q81_TX_CFG_EN = (1 << 1), /*Control*/ 104 Q81_TX_CFG_PREAM = (1 << 2), /*Control*/ 105 Q81_RX_CFG = 0x00000110, 106 Q81_RX_CFG_RESET = (1 << 0), /*Control*/ 107 Q81_RX_CFG_EN = (1 << 1), /*Control*/ 108 Q81_RX_CFG_PREAM = (1 << 2), /*Control*/ 109 Q81_FLOW_CTL = 0x0000011c, 110 Q81_PAUSE_OPCODE = 0x00000120, 111 Q81_PAUSE_TIMER = 0x00000124, 112 Q81_PAUSE_FRM_DEST_LO = 0x00000128, 113 Q81_PAUSE_FRM_DEST_HI = 0x0000012c, 114 Q81_MAC_TX_PARAMS = 0x00000134, 115 Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/ 116 Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/ 117 Q81_MAC_RX_PARAMS = 0x00000138, 118 Q81_MAC_SYS_INT = 0x00000144, 119 Q81_MAC_SYS_INT_MASK = 0x00000148, 120 Q81_MAC_MGMT_INT = 0x0000014c, 121 Q81_MAC_MGMT_IN_MASK = 0x00000150, 122 Q81_EXT_ARB_MODE = 0x000001fc, 123 Q81_TX_PKTS = 0x00000200, 124 Q81_TX_PKTS_LO = 0x00000204, 125 Q81_TX_BYTES = 0x00000208, 126 Q81_TX_BYTES_LO = 0x0000020C, 127 Q81_TX_MCAST_PKTS = 0x00000210, 128 Q81_TX_MCAST_PKTS_LO = 0x00000214, 129 Q81_TX_BCAST_PKTS = 0x00000218, 130 Q81_TX_BCAST_PKTS_LO = 0x0000021C, 131 Q81_TX_UCAST_PKTS = 0x00000220, 132 Q81_TX_UCAST_PKTS_LO = 0x00000224, 133 Q81_TX_CTL_PKTS = 0x00000228, 134 Q81_TX_CTL_PKTS_LO = 0x0000022c, 135 Q81_TX_PAUSE_PKTS = 0x00000230, 136 Q81_TX_PAUSE_PKTS_LO = 0x00000234, 137 Q81_TX_64_PKT = 0x00000238, 138 Q81_TX_64_PKT_LO = 0x0000023c, 139 Q81_TX_65_TO_127_PKT = 0x00000240, 140 Q81_TX_65_TO_127_PKT_LO = 0x00000244, 141 Q81_TX_128_TO_255_PKT = 0x00000248, 142 Q81_TX_128_TO_255_PKT_LO = 0x0000024c, 143 Q81_TX_256_511_PKT = 0x00000250, 144 Q81_TX_256_511_PKT_LO = 0x00000254, 145 Q81_TX_512_TO_1023_PKT = 0x00000258, 146 Q81_TX_512_TO_1023_PKT_LO = 0x0000025c, 147 Q81_TX_1024_TO_1518_PKT = 0x00000260, 148 Q81_TX_1024_TO_1518_PKT_LO = 0x00000264, 149 Q81_TX_1519_TO_MAX_PKT = 0x00000268, 150 Q81_TX_1519_TO_MAX_PKT_LO = 0x0000026c, 151 Q81_TX_UNDERSIZE_PKT = 0x00000270, 152 Q81_TX_UNDERSIZE_PKT_LO = 0x00000274, 153 Q81_TX_OVERSIZE_PKT = 0x00000278, 154 Q81_TX_OVERSIZE_PKT_LO = 0x0000027c, 155 Q81_RX_HALF_FULL_DET = 0x000002a0, 156 Q81_TX_HALF_FULL_DET_LO = 0x000002a4, 157 Q81_RX_OVERFLOW_DET = 0x000002a8, 158 Q81_TX_OVERFLOW_DET_LO = 0x000002ac, 159 Q81_RX_HALF_FULL_MASK = 0x000002b0, 160 Q81_TX_HALF_FULL_MASK_LO = 0x000002b4, 161 Q81_RX_OVERFLOW_MASK = 0x000002b8, 162 Q81_TX_OVERFLOW_MASK_LO = 0x000002bc, 163 Q81_STAT_CNT_CTL = 0x000002c0, 164 Q81_STAT_CNT_CTL_CLEAR_TX = (1 << 0), /*Control*/ 165 Q81_STAT_CNT_CTL_CLEAR_RX = (1 << 1), /*Control*/ 166 Q81_AUX_RX_HALF_FULL_DET = 0x000002d0, 167 Q81_AUX_TX_HALF_FULL_DET = 0x000002d4, 168 Q81_AUX_RX_OVERFLOW_DET = 0x000002d8, 169 Q81_AUX_TX_OVERFLOW_DET = 0x000002dc, 170 Q81_AUX_RX_HALF_FULL_MASK = 0x000002f0, 171 Q81_AUX_TX_HALF_FULL_MASK = 0x000002f4, 172 Q81_AUX_RX_OVERFLOW_MASK = 0x000002f8, 173 Q81_AUX_TX_OVERFLOW_MASK = 0x000002fc, 174 Q81_RX_BYTES = 0x00000300, 175 Q81_RX_BYTES_LO = 0x00000304, 176 Q81_RX_BYTES_OK = 0x00000308, 177 Q81_RX_BYTES_OK_LO = 0x0000030c, 178 Q81_RX_PKTS = 0x00000310, 179 Q81_RX_PKTS_LO = 0x00000314, 180 Q81_RX_PKTS_OK = 0x00000318, 181 Q81_RX_PKTS_OK_LO = 0x0000031c, 182 Q81_RX_BCAST_PKTS = 0x00000320, 183 Q81_RX_BCAST_PKTS_LO = 0x00000324, 184 Q81_RX_MCAST_PKTS = 0x00000328, 185 Q81_RX_MCAST_PKTS_LO = 0x0000032c, 186 Q81_RX_UCAST_PKTS = 0x00000330, 187 Q81_RX_UCAST_PKTS_LO = 0x00000334, 188 Q81_RX_UNDERSIZE_PKTS = 0x00000338, 189 Q81_RX_UNDERSIZE_PKTS_LO = 0x0000033c, 190 Q81_RX_OVERSIZE_PKTS = 0x00000340, 191 Q81_RX_OVERSIZE_PKTS_LO = 0x00000344, 192 Q81_RX_JABBER_PKTS = 0x00000348, 193 Q81_RX_JABBER_PKTS_LO = 0x0000034c, 194 Q81_RX_UNDERSIZE_FCERR_PKTS = 0x00000350, 195 Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354, 196 Q81_RX_DROP_EVENTS = 0x00000358, 197 Q81_RX_DROP_EVENTS_LO = 0x0000035c, 198 Q81_RX_FCERR_PKTS = 0x00000360, 199 Q81_RX_FCERR_PKTS_LO = 0x00000364, 200 Q81_RX_ALIGN_ERR = 0x00000368, 201 Q81_RX_ALIGN_ERR_LO = 0x0000036c, 202 Q81_RX_SYMBOL_ERR = 0x00000370, 203 Q81_RX_SYMBOL_ERR_LO = 0x00000374, 204 Q81_RX_MAC_ERR = 0x00000378, 205 Q81_RX_MAC_ERR_LO = 0x0000037c, 206 Q81_RX_CTL_PKTS = 0x00000380, 207 Q81_RX_CTL_PKTS_LO = 0x00000384, 208 Q81_RX_PAUSE_PKTS = 0x00000388, 209 Q81_RX_PAUSE_PKTS_LO = 0x0000038c, 210 Q81_RX_64_PKTS = 0x00000390, 211 Q81_RX_64_PKTS_LO = 0x00000394, 212 Q81_RX_65_TO_127_PKTS = 0x00000398, 213 Q81_RX_65_TO_127_PKTS_LO = 0x0000039c, 214 Q81_RX_128_255_PKTS = 0x000003a0, 215 Q81_RX_128_255_PKTS_LO = 0x000003a4, 216 Q81_RX_256_511_PKTS = 0x000003a8, 217 Q81_RX_256_511_PKTS_LO = 0x000003ac, 218 Q81_RX_512_TO_1023_PKTS = 0x000003b0, 219 Q81_RX_512_TO_1023_PKTS_LO = 0x000003b4, 220 Q81_RX_1024_TO_1518_PKTS = 0x000003b8, 221 Q81_RX_1024_TO_1518_PKTS_LO = 0x000003bc, 222 Q81_RX_1519_TO_MAX_PKTS = 0x000003c0, 223 Q81_RX_1519_TO_MAX_PKTS_LO = 0x000003c4, 224 Q81_RX_LEN_ERR_PKTS = 0x000003c8, 225 Q81_RX_LEN_ERR_PKTS_LO = 0x000003cc, 226 Q81_MDIO_TX_DATA = 0x00000400, 227 Q81_MDIO_RX_DATA = 0x00000410, 228 Q81_MDIO_CMD = 0x00000420, 229 Q81_MDIO_PHY_ADDR = 0x00000430, 230 Q81_MDIO_PORT = 0x00000440, 231 Q81_MDIO_STATUS = 0x00000450, 232 Q81_TX_CBFC_PAUSE_FRAMES0 = 0x00000500, 233 Q81_TX_CBFC_PAUSE_FRAMES0_LO = 0x00000504, 234 Q81_TX_CBFC_PAUSE_FRAMES1 = 0x00000508, 235 Q81_TX_CBFC_PAUSE_FRAMES1_LO = 0x0000050C, 236 Q81_TX_CBFC_PAUSE_FRAMES2 = 0x00000510, 237 Q81_TX_CBFC_PAUSE_FRAMES2_LO = 0x00000514, 238 Q81_TX_CBFC_PAUSE_FRAMES3 = 0x00000518, 239 Q81_TX_CBFC_PAUSE_FRAMES3_LO = 0x0000051C, 240 Q81_TX_CBFC_PAUSE_FRAMES4 = 0x00000520, 241 Q81_TX_CBFC_PAUSE_FRAMES4_LO = 0x00000524, 242 Q81_TX_CBFC_PAUSE_FRAMES5 = 0x00000528, 243 Q81_TX_CBFC_PAUSE_FRAMES5_LO = 0x0000052C, 244 Q81_TX_CBFC_PAUSE_FRAMES6 = 0x00000530, 245 Q81_TX_CBFC_PAUSE_FRAMES6_LO = 0x00000534, 246 Q81_TX_CBFC_PAUSE_FRAMES7 = 0x00000538, 247 Q81_TX_CBFC_PAUSE_FRAMES7_LO = 0x0000053C, 248 Q81_TX_FCOE_PKTS = 0x00000540, 249 Q81_TX_FCOE_PKTS_LO = 0x00000544, 250 Q81_TX_MGMT_PKTS = 0x00000548, 251 Q81_TX_MGMT_PKTS_LO = 0x0000054C, 252 Q81_RX_CBFC_PAUSE_FRAMES0 = 0x00000568, 253 Q81_RX_CBFC_PAUSE_FRAMES0_LO = 0x0000056C, 254 Q81_RX_CBFC_PAUSE_FRAMES1 = 0x00000570, 255 Q81_RX_CBFC_PAUSE_FRAMES1_LO = 0x00000574, 256 Q81_RX_CBFC_PAUSE_FRAMES2 = 0x00000578, 257 Q81_RX_CBFC_PAUSE_FRAMES2_LO = 0x0000057C, 258 Q81_RX_CBFC_PAUSE_FRAMES3 = 0x00000580, 259 Q81_RX_CBFC_PAUSE_FRAMES3_LO = 0x00000584, 260 Q81_RX_CBFC_PAUSE_FRAMES4 = 0x00000588, 261 Q81_RX_CBFC_PAUSE_FRAMES4_LO = 0x0000058C, 262 Q81_RX_CBFC_PAUSE_FRAMES5 = 0x00000590, 263 Q81_RX_CBFC_PAUSE_FRAMES5_LO = 0x00000594, 264 Q81_RX_CBFC_PAUSE_FRAMES6 = 0x00000598, 265 Q81_RX_CBFC_PAUSE_FRAMES6_LO = 0x0000059C, 266 Q81_RX_CBFC_PAUSE_FRAMES7 = 0x000005A0, 267 Q81_RX_CBFC_PAUSE_FRAMES7_LO = 0x000005A4, 268 Q81_RX_FCOE_PKTS = 0x000005A8, 269 Q81_RX_FCOE_PKTS_LO = 0x000005AC, 270 Q81_RX_MGMT_PKTS = 0x000005B0, 271 Q81_RX_MGMT_PKTS_LO = 0x000005B4, 272 Q81_RX_NIC_FIFO_DROP = 0x000005B8, 273 Q81_RX_NIC_FIFO_DROP_LO = 0x000005BC, 274 Q81_RX_FCOE_FIFO_DROP = 0x000005C0, 275 Q81_RX_FCOE_FIFO_DROP_LO = 0x000005C4, 276 Q81_RX_MGMT_FIFO_DROP = 0x000005C8, 277 Q81_RX_MGMT_FIFO_DROP_LO = 0x000005CC, 278 Q81_RX_PKTS_PRIORITY0 = 0x00000600, 279 Q81_RX_PKTS_PRIORITY0_LO = 0x00000604, 280 Q81_RX_PKTS_PRIORITY1 = 0x00000608, 281 Q81_RX_PKTS_PRIORITY1_LO = 0x0000060C, 282 Q81_RX_PKTS_PRIORITY2 = 0x00000610, 283 Q81_RX_PKTS_PRIORITY2_LO = 0x00000614, 284 Q81_RX_PKTS_PRIORITY3 = 0x00000618, 285 Q81_RX_PKTS_PRIORITY3_LO = 0x0000061C, 286 Q81_RX_PKTS_PRIORITY4 = 0x00000620, 287 Q81_RX_PKTS_PRIORITY4_LO = 0x00000624, 288 Q81_RX_PKTS_PRIORITY5 = 0x00000628, 289 Q81_RX_PKTS_PRIORITY5_LO = 0x0000062C, 290 Q81_RX_PKTS_PRIORITY6 = 0x00000630, 291 Q81_RX_PKTS_PRIORITY6_LO = 0x00000634, 292 Q81_RX_PKTS_PRIORITY7 = 0x00000638, 293 Q81_RX_PKTS_PRIORITY7_LO = 0x0000063C, 294 Q81_RX_OCTETS_PRIORITY0 = 0x00000640, 295 Q81_RX_OCTETS_PRIORITY0_LO = 0x00000644, 296 Q81_RX_OCTETS_PRIORITY1 = 0x00000648, 297 Q81_RX_OCTETS_PRIORITY1_LO = 0x0000064C, 298 Q81_RX_OCTETS_PRIORITY2 = 0x00000650, 299 Q81_RX_OCTETS_PRIORITY2_LO = 0x00000654, 300 Q81_RX_OCTETS_PRIORITY3 = 0x00000658, 301 Q81_RX_OCTETS_PRIORITY3_LO = 0x0000065C, 302 Q81_RX_OCTETS_PRIORITY4 = 0x00000660, 303 Q81_RX_OCTETS_PRIORITY4_LO = 0x00000664, 304 Q81_RX_OCTETS_PRIORITY5 = 0x00000668, 305 Q81_RX_OCTETS_PRIORITY5_LO = 0x0000066C, 306 Q81_RX_OCTETS_PRIORITY6 = 0x00000670, 307 Q81_RX_OCTETS_PRIORITY6_LO = 0x00000674, 308 Q81_RX_OCTETS_PRIORITY7 = 0x00000678, 309 Q81_RX_OCTETS_PRIORITY7_LO = 0x0000067C, 310 Q81_TX_PKTS_PRIORITY0 = 0x00000680, 311 Q81_TX_PKTS_PRIORITY0_LO = 0x00000684, 312 Q81_TX_PKTS_PRIORITY1 = 0x00000688, 313 Q81_TX_PKTS_PRIORITY1_LO = 0x0000068C, 314 Q81_TX_PKTS_PRIORITY2 = 0x00000690, 315 Q81_TX_PKTS_PRIORITY2_LO = 0x00000694, 316 Q81_TX_PKTS_PRIORITY3 = 0x00000698, 317 Q81_TX_PKTS_PRIORITY3_LO = 0x0000069C, 318 Q81_TX_PKTS_PRIORITY4 = 0x000006A0, 319 Q81_TX_PKTS_PRIORITY4_LO = 0x000006A4, 320 Q81_TX_PKTS_PRIORITY5 = 0x000006A8, 321 Q81_TX_PKTS_PRIORITY5_LO = 0x000006AC, 322 Q81_TX_PKTS_PRIORITY6 = 0x000006B0, 323 Q81_TX_PKTS_PRIORITY6_LO = 0x000006B4, 324 Q81_TX_PKTS_PRIORITY7 = 0x000006B8, 325 Q81_TX_PKTS_PRIORITY7_LO = 0x000006BC, 326 Q81_TX_OCTETS_PRIORITY0 = 0x000006C0, 327 Q81_TX_OCTETS_PRIORITY0_LO = 0x000006C4, 328 Q81_TX_OCTETS_PRIORITY1 = 0x000006C8, 329 Q81_TX_OCTETS_PRIORITY1_LO = 0x000006CC, 330 Q81_TX_OCTETS_PRIORITY2 = 0x000006D0, 331 Q81_TX_OCTETS_PRIORITY2_LO = 0x000006D4, 332 Q81_TX_OCTETS_PRIORITY3 = 0x000006D8, 333 Q81_TX_OCTETS_PRIORITY3_LO = 0x000006DC, 334 Q81_TX_OCTETS_PRIORITY4 = 0x000006E0, 335 Q81_TX_OCTETS_PRIORITY4_LO = 0x000006E4, 336 Q81_TX_OCTETS_PRIORITY5 = 0x000006E8, 337 Q81_TX_OCTETS_PRIORITY5_LO = 0x000006EC, 338 Q81_TX_OCTETS_PRIORITY6 = 0x000006F0, 339 Q81_TX_OCTETS_PRIORITY6_LO = 0x000006F4, 340 Q81_TX_OCTETS_PRIORITY7 = 0x000006F8, 341 Q81_TX_OCTETS_PRIORITY7_LO = 0x000006FC, 342 Q81_RX_DISCARD_PRIORITY0 = 0x00000700, 343 Q81_RX_DISCARD_PRIORITY0_LO = 0x00000704, 344 Q81_RX_DISCARD_PRIORITY1 = 0x00000708, 345 Q81_RX_DISCARD_PRIORITY1_LO = 0x0000070C, 346 Q81_RX_DISCARD_PRIORITY2 = 0x00000710, 347 Q81_RX_DISCARD_PRIORITY2_LO = 0x00000714, 348 Q81_RX_DISCARD_PRIORITY3 = 0x00000718, 349 Q81_RX_DISCARD_PRIORITY3_LO = 0x0000071C, 350 Q81_RX_DISCARD_PRIORITY4 = 0x00000720, 351 Q81_RX_DISCARD_PRIORITY4_LO = 0x00000724, 352 Q81_RX_DISCARD_PRIORITY5 = 0x00000728, 353 Q81_RX_DISCARD_PRIORITY5_LO = 0x0000072C, 354 Q81_RX_DISCARD_PRIORITY6 = 0x00000730, 355 Q81_RX_DISCARD_PRIORITY6_LO = 0x00000734, 356 Q81_RX_DISCARD_PRIORITY7 = 0x00000738, 357 Q81_RX_DISCARD_PRIORITY7_LO = 0x0000073C 358 }; 359 360 static void 361 qls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num, 362 uint32_t seg_size, unsigned char *desc) 363 { 364 memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t)); 365 366 seg_hdr->cookie = Q81_MPID_COOKIE; 367 seg_hdr->seg_num = seg_num; 368 seg_hdr->seg_size = seg_size; 369 370 memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1); 371 372 return; 373 } 374 375 static int 376 qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit) 377 { 378 uint32_t data; 379 int count = 10; 380 381 while (count) { 382 data = READ_REG32(ha, reg); 383 384 if (data & err_bit) 385 return (-1); 386 else if (data & bit) 387 return (0); 388 389 qls_mdelay(__func__, 10); 390 count--; 391 } 392 return (-1); 393 } 394 395 static int 396 qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 397 { 398 int ret; 399 400 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 401 Q81_CTL_PROC_ADDR_ERR); 402 403 if (ret) 404 goto exit_qls_rd_mpi_reg; 405 406 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); 407 408 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 409 Q81_CTL_PROC_ADDR_ERR); 410 411 if (ret) 412 goto exit_qls_rd_mpi_reg; 413 414 *data = READ_REG32(ha, Q81_CTL_PROC_DATA); 415 416 exit_qls_rd_mpi_reg: 417 return (ret); 418 } 419 420 static int 421 qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data) 422 { 423 int ret = 0; 424 425 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 426 Q81_CTL_PROC_ADDR_ERR); 427 if (ret) 428 goto exit_qls_wr_mpi_reg; 429 430 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); 431 432 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); 433 434 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 435 Q81_CTL_PROC_ADDR_ERR); 436 exit_qls_wr_mpi_reg: 437 return (ret); 438 } 439 440 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002 441 #define Q81_INVALID_NUM 0xFFFFFFFF 442 443 #define Q81_NIC1_FUNC_ENABLE 0x00000001 444 #define Q81_NIC1_FUNC_MASK 0x0000000e 445 #define Q81_NIC1_FUNC_SHIFT 1 446 #define Q81_NIC2_FUNC_ENABLE 0x00000010 447 #define Q81_NIC2_FUNC_MASK 0x000000e0 448 #define Q81_NIC2_FUNC_SHIFT 5 449 #define Q81_FUNCTION_SHIFT 6 450 451 static uint32_t 452 qls_get_other_fnum(qla_host_t *ha) 453 { 454 int ret; 455 uint32_t o_func; 456 uint32_t test_logic; 457 uint32_t nic1_fnum = Q81_INVALID_NUM; 458 uint32_t nic2_fnum = Q81_INVALID_NUM; 459 460 ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic); 461 if (ret) 462 return(Q81_INVALID_NUM); 463 464 if (test_logic & Q81_NIC1_FUNC_ENABLE) 465 nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >> 466 Q81_NIC1_FUNC_SHIFT; 467 468 if (test_logic & Q81_NIC2_FUNC_ENABLE) 469 nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >> 470 Q81_NIC2_FUNC_SHIFT; 471 472 if (ha->pci_func == 0) 473 o_func = nic2_fnum; 474 else 475 o_func = nic1_fnum; 476 477 return(o_func); 478 } 479 480 static uint32_t 481 qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg) 482 { 483 uint32_t ofunc; 484 uint32_t data; 485 int ret = 0; 486 487 ofunc = qls_get_other_fnum(ha); 488 489 if (ofunc == Q81_INVALID_NUM) 490 return(Q81_INVALID_NUM); 491 492 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 493 494 ret = qls_rd_mpi_reg(ha, reg, &data); 495 496 if (ret != 0) 497 return(Q81_INVALID_NUM); 498 499 return(data); 500 } 501 502 static void 503 qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value) 504 { 505 uint32_t ofunc; 506 507 ofunc = qls_get_other_fnum(ha); 508 509 if (ofunc == Q81_INVALID_NUM) 510 return; 511 512 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 513 514 qls_wr_mpi_reg(ha, reg, value); 515 516 return; 517 } 518 519 static int 520 qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, 521 uint32_t err_bit) 522 { 523 uint32_t data; 524 int count = 10; 525 526 while (count) { 527 data = qls_rd_ofunc_reg(ha, reg); 528 529 if (data & err_bit) 530 return (-1); 531 else if (data & bit) 532 return (0); 533 534 qls_mdelay(__func__, 10); 535 count--; 536 } 537 return (-1); 538 } 539 540 #define Q81_XG_SERDES_ADDR_RDY BIT_31 541 #define Q81_XG_SERDES_ADDR_READ BIT_30 542 543 static int 544 qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 545 { 546 int ret; 547 548 /* wait for reg to come ready */ 549 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 550 Q81_XG_SERDES_ADDR_RDY, 0); 551 if (ret) 552 goto exit_qls_rd_ofunc_serdes_reg; 553 554 /* set up for reg read */ 555 qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 556 (reg | Q81_XG_SERDES_ADDR_READ)); 557 558 /* wait for reg to come ready */ 559 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 560 Q81_XG_SERDES_ADDR_RDY, 0); 561 if (ret) 562 goto exit_qls_rd_ofunc_serdes_reg; 563 564 /* get the data */ 565 *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2)); 566 567 exit_qls_rd_ofunc_serdes_reg: 568 return ret; 569 } 570 571 #define Q81_XGMAC_ADDR_RDY BIT_31 572 #define Q81_XGMAC_ADDR_R BIT_30 573 #define Q81_XGMAC_ADDR_XME BIT_29 574 575 static int 576 qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 577 { 578 int ret = 0; 579 580 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 581 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 582 583 if (ret) 584 goto exit_qls_rd_ofunc_xgmac_reg; 585 586 qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2), 587 (reg | Q81_XGMAC_ADDR_R)); 588 589 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 590 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 591 if (ret) 592 goto exit_qls_rd_ofunc_xgmac_reg; 593 594 *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA); 595 596 exit_qls_rd_ofunc_xgmac_reg: 597 return ret; 598 } 599 600 static int 601 qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 602 { 603 int ret; 604 605 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 606 Q81_XG_SERDES_ADDR_RDY, 0); 607 608 if (ret) 609 goto exit_qls_rd_serdes_reg; 610 611 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ 612 (reg | Q81_XG_SERDES_ADDR_READ)); 613 614 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 615 Q81_XG_SERDES_ADDR_RDY, 0); 616 617 if (ret) 618 goto exit_qls_rd_serdes_reg; 619 620 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA); 621 622 exit_qls_rd_serdes_reg: 623 624 return ret; 625 } 626 627 static void 628 qls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr, 629 uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid) 630 { 631 int ret = -1; 632 633 if (dvalid) 634 ret = qls_rd_serdes_reg(ha, addr, dptr); 635 636 if (ret) 637 *dptr = Q81_BAD_DATA; 638 639 ret = -1; 640 641 if(ind_valid) 642 ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr); 643 644 if (ret) 645 *ind_ptr = Q81_BAD_DATA; 646 } 647 648 #define Q81_XFI1_POWERED_UP 0x00000005 649 #define Q81_XFI2_POWERED_UP 0x0000000A 650 #define Q81_XAUI_POWERED_UP 0x00000001 651 652 static int 653 qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump) 654 { 655 int ret; 656 uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid; 657 uint32_t temp, xaui_reg, i; 658 uint32_t *dptr, *indptr; 659 660 xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0; 661 662 xaui_reg = 0x800; 663 664 ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp); 665 if (ret) 666 temp = 0; 667 668 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 669 xaui_ind_valid = 1; 670 671 ret = qls_rd_serdes_reg(ha, xaui_reg, &temp); 672 if (ret) 673 temp = 0; 674 675 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 676 xaui_d_valid = 1; 677 678 ret = qls_rd_serdes_reg(ha, 0x1E06, &temp); 679 if (ret) 680 temp = 0; 681 682 if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) { 683 if (ha->pci_func & 1) 684 xfi_ind_valid = 1; /* NIC 2, so the indirect 685 (NIC1) xfi is up*/ 686 else 687 xfi_d_valid = 1; 688 } 689 690 if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) { 691 if(ha->pci_func & 1) 692 xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1) 693 xfi is up */ 694 else 695 xfi_ind_valid = 1; 696 } 697 698 if (ha->pci_func & 1) { 699 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 700 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 701 } else { 702 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 703 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 704 } 705 706 for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) { 707 qls_get_both_serdes(ha, i, dptr, indptr, 708 xaui_d_valid, xaui_ind_valid); 709 } 710 711 if (ha->pci_func & 1) { 712 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 713 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 714 } else { 715 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 716 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 717 } 718 719 for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) { 720 qls_get_both_serdes(ha, i, dptr, indptr, 721 xaui_d_valid, xaui_ind_valid); 722 } 723 724 if (ha->pci_func & 1) { 725 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 726 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 727 } else { 728 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 729 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 730 } 731 732 for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) { 733 qls_get_both_serdes(ha, i, dptr, indptr, 734 xfi_d_valid, xfi_ind_valid); 735 } 736 737 if (ha->pci_func & 1) { 738 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 739 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 740 } else { 741 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 742 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 743 } 744 745 for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) { 746 qls_get_both_serdes(ha, i, dptr, indptr, 747 xfi_d_valid, xfi_ind_valid); 748 } 749 750 if (ha->pci_func & 1) { 751 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 752 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 753 } else { 754 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 755 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 756 } 757 758 for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) { 759 qls_get_both_serdes(ha, i, dptr, indptr, 760 xfi_d_valid, xfi_ind_valid); 761 } 762 763 if (ha->pci_func & 1) { 764 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 765 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 766 } else { 767 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 768 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 769 } 770 771 for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) { 772 qls_get_both_serdes(ha, i, dptr, indptr, 773 xfi_d_valid, xfi_ind_valid); 774 } 775 776 if (ha->pci_func & 1) { 777 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 778 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 779 } else { 780 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 781 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 782 } 783 784 for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) { 785 qls_get_both_serdes(ha, i, dptr, indptr, 786 xfi_d_valid, xfi_ind_valid); 787 } 788 789 if (ha->pci_func & 1) { 790 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 791 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 792 } else { 793 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 794 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 795 } 796 797 for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) { 798 qls_get_both_serdes(ha, i, dptr, indptr, 799 xfi_d_valid, xfi_ind_valid); 800 } 801 802 return(0); 803 } 804 805 static int 806 qls_unpause_mpi_risc(qla_host_t *ha) 807 { 808 uint32_t data; 809 810 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 811 812 if (!(data & Q81_CTL_HCS_RISC_PAUSED)) 813 return -1; 814 815 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 816 Q81_CTL_HCS_CMD_CLR_RISC_PAUSE); 817 818 return 0; 819 } 820 821 static int 822 qls_pause_mpi_risc(qla_host_t *ha) 823 { 824 uint32_t data; 825 int count = 10; 826 827 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 828 Q81_CTL_HCS_CMD_SET_RISC_PAUSE); 829 830 do { 831 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 832 833 if (data & Q81_CTL_HCS_RISC_PAUSED) 834 break; 835 836 qls_mdelay(__func__, 10); 837 838 count--; 839 840 } while (count); 841 842 return ((count == 0) ? -1 : 0); 843 } 844 845 static void 846 qls_get_intr_states(qla_host_t *ha, uint32_t *buf) 847 { 848 int i; 849 850 for (i = 0; i < MAX_RX_RINGS; i++, buf++) { 851 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); 852 853 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); 854 } 855 } 856 857 static int 858 qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data) 859 { 860 int ret = 0; 861 862 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 863 Q81_XGMAC_ADDR_XME); 864 if (ret) 865 goto exit_qls_rd_xgmac_reg; 866 867 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); 868 869 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 870 Q81_XGMAC_ADDR_XME); 871 if (ret) 872 goto exit_qls_rd_xgmac_reg; 873 874 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA); 875 876 exit_qls_rd_xgmac_reg: 877 return ret; 878 } 879 880 static int 881 qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func) 882 { 883 int ret = 0; 884 int i; 885 886 for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { 887 switch (i) { 888 case Q81_PAUSE_SRC_LO : 889 case Q81_PAUSE_SRC_HI : 890 case Q81_GLOBAL_CFG : 891 case Q81_TX_CFG : 892 case Q81_RX_CFG : 893 case Q81_FLOW_CTL : 894 case Q81_PAUSE_OPCODE : 895 case Q81_PAUSE_TIMER : 896 case Q81_PAUSE_FRM_DEST_LO : 897 case Q81_PAUSE_FRM_DEST_HI : 898 case Q81_MAC_TX_PARAMS : 899 case Q81_MAC_RX_PARAMS : 900 case Q81_MAC_SYS_INT : 901 case Q81_MAC_SYS_INT_MASK : 902 case Q81_MAC_MGMT_INT : 903 case Q81_MAC_MGMT_IN_MASK : 904 case Q81_EXT_ARB_MODE : 905 case Q81_TX_PKTS : 906 case Q81_TX_PKTS_LO : 907 case Q81_TX_BYTES : 908 case Q81_TX_BYTES_LO : 909 case Q81_TX_MCAST_PKTS : 910 case Q81_TX_MCAST_PKTS_LO : 911 case Q81_TX_BCAST_PKTS : 912 case Q81_TX_BCAST_PKTS_LO : 913 case Q81_TX_UCAST_PKTS : 914 case Q81_TX_UCAST_PKTS_LO : 915 case Q81_TX_CTL_PKTS : 916 case Q81_TX_CTL_PKTS_LO : 917 case Q81_TX_PAUSE_PKTS : 918 case Q81_TX_PAUSE_PKTS_LO : 919 case Q81_TX_64_PKT : 920 case Q81_TX_64_PKT_LO : 921 case Q81_TX_65_TO_127_PKT : 922 case Q81_TX_65_TO_127_PKT_LO : 923 case Q81_TX_128_TO_255_PKT : 924 case Q81_TX_128_TO_255_PKT_LO : 925 case Q81_TX_256_511_PKT : 926 case Q81_TX_256_511_PKT_LO : 927 case Q81_TX_512_TO_1023_PKT : 928 case Q81_TX_512_TO_1023_PKT_LO : 929 case Q81_TX_1024_TO_1518_PKT : 930 case Q81_TX_1024_TO_1518_PKT_LO : 931 case Q81_TX_1519_TO_MAX_PKT : 932 case Q81_TX_1519_TO_MAX_PKT_LO : 933 case Q81_TX_UNDERSIZE_PKT : 934 case Q81_TX_UNDERSIZE_PKT_LO : 935 case Q81_TX_OVERSIZE_PKT : 936 case Q81_TX_OVERSIZE_PKT_LO : 937 case Q81_RX_HALF_FULL_DET : 938 case Q81_TX_HALF_FULL_DET_LO : 939 case Q81_RX_OVERFLOW_DET : 940 case Q81_TX_OVERFLOW_DET_LO : 941 case Q81_RX_HALF_FULL_MASK : 942 case Q81_TX_HALF_FULL_MASK_LO : 943 case Q81_RX_OVERFLOW_MASK : 944 case Q81_TX_OVERFLOW_MASK_LO : 945 case Q81_STAT_CNT_CTL : 946 case Q81_AUX_RX_HALF_FULL_DET : 947 case Q81_AUX_TX_HALF_FULL_DET : 948 case Q81_AUX_RX_OVERFLOW_DET : 949 case Q81_AUX_TX_OVERFLOW_DET : 950 case Q81_AUX_RX_HALF_FULL_MASK : 951 case Q81_AUX_TX_HALF_FULL_MASK : 952 case Q81_AUX_RX_OVERFLOW_MASK : 953 case Q81_AUX_TX_OVERFLOW_MASK : 954 case Q81_RX_BYTES : 955 case Q81_RX_BYTES_LO : 956 case Q81_RX_BYTES_OK : 957 case Q81_RX_BYTES_OK_LO : 958 case Q81_RX_PKTS : 959 case Q81_RX_PKTS_LO : 960 case Q81_RX_PKTS_OK : 961 case Q81_RX_PKTS_OK_LO : 962 case Q81_RX_BCAST_PKTS : 963 case Q81_RX_BCAST_PKTS_LO : 964 case Q81_RX_MCAST_PKTS : 965 case Q81_RX_MCAST_PKTS_LO : 966 case Q81_RX_UCAST_PKTS : 967 case Q81_RX_UCAST_PKTS_LO : 968 case Q81_RX_UNDERSIZE_PKTS : 969 case Q81_RX_UNDERSIZE_PKTS_LO : 970 case Q81_RX_OVERSIZE_PKTS : 971 case Q81_RX_OVERSIZE_PKTS_LO : 972 case Q81_RX_JABBER_PKTS : 973 case Q81_RX_JABBER_PKTS_LO : 974 case Q81_RX_UNDERSIZE_FCERR_PKTS : 975 case Q81_RX_UNDERSIZE_FCERR_PKTS_LO : 976 case Q81_RX_DROP_EVENTS : 977 case Q81_RX_DROP_EVENTS_LO : 978 case Q81_RX_FCERR_PKTS : 979 case Q81_RX_FCERR_PKTS_LO : 980 case Q81_RX_ALIGN_ERR : 981 case Q81_RX_ALIGN_ERR_LO : 982 case Q81_RX_SYMBOL_ERR : 983 case Q81_RX_SYMBOL_ERR_LO : 984 case Q81_RX_MAC_ERR : 985 case Q81_RX_MAC_ERR_LO : 986 case Q81_RX_CTL_PKTS : 987 case Q81_RX_CTL_PKTS_LO : 988 case Q81_RX_PAUSE_PKTS : 989 case Q81_RX_PAUSE_PKTS_LO : 990 case Q81_RX_64_PKTS : 991 case Q81_RX_64_PKTS_LO : 992 case Q81_RX_65_TO_127_PKTS : 993 case Q81_RX_65_TO_127_PKTS_LO : 994 case Q81_RX_128_255_PKTS : 995 case Q81_RX_128_255_PKTS_LO : 996 case Q81_RX_256_511_PKTS : 997 case Q81_RX_256_511_PKTS_LO : 998 case Q81_RX_512_TO_1023_PKTS : 999 case Q81_RX_512_TO_1023_PKTS_LO : 1000 case Q81_RX_1024_TO_1518_PKTS : 1001 case Q81_RX_1024_TO_1518_PKTS_LO : 1002 case Q81_RX_1519_TO_MAX_PKTS : 1003 case Q81_RX_1519_TO_MAX_PKTS_LO : 1004 case Q81_RX_LEN_ERR_PKTS : 1005 case Q81_RX_LEN_ERR_PKTS_LO : 1006 case Q81_MDIO_TX_DATA : 1007 case Q81_MDIO_RX_DATA : 1008 case Q81_MDIO_CMD : 1009 case Q81_MDIO_PHY_ADDR : 1010 case Q81_MDIO_PORT : 1011 case Q81_MDIO_STATUS : 1012 case Q81_TX_CBFC_PAUSE_FRAMES0 : 1013 case Q81_TX_CBFC_PAUSE_FRAMES0_LO : 1014 case Q81_TX_CBFC_PAUSE_FRAMES1 : 1015 case Q81_TX_CBFC_PAUSE_FRAMES1_LO : 1016 case Q81_TX_CBFC_PAUSE_FRAMES2 : 1017 case Q81_TX_CBFC_PAUSE_FRAMES2_LO : 1018 case Q81_TX_CBFC_PAUSE_FRAMES3 : 1019 case Q81_TX_CBFC_PAUSE_FRAMES3_LO : 1020 case Q81_TX_CBFC_PAUSE_FRAMES4 : 1021 case Q81_TX_CBFC_PAUSE_FRAMES4_LO : 1022 case Q81_TX_CBFC_PAUSE_FRAMES5 : 1023 case Q81_TX_CBFC_PAUSE_FRAMES5_LO : 1024 case Q81_TX_CBFC_PAUSE_FRAMES6 : 1025 case Q81_TX_CBFC_PAUSE_FRAMES6_LO : 1026 case Q81_TX_CBFC_PAUSE_FRAMES7 : 1027 case Q81_TX_CBFC_PAUSE_FRAMES7_LO : 1028 case Q81_TX_FCOE_PKTS : 1029 case Q81_TX_FCOE_PKTS_LO : 1030 case Q81_TX_MGMT_PKTS : 1031 case Q81_TX_MGMT_PKTS_LO : 1032 case Q81_RX_CBFC_PAUSE_FRAMES0 : 1033 case Q81_RX_CBFC_PAUSE_FRAMES0_LO : 1034 case Q81_RX_CBFC_PAUSE_FRAMES1 : 1035 case Q81_RX_CBFC_PAUSE_FRAMES1_LO : 1036 case Q81_RX_CBFC_PAUSE_FRAMES2 : 1037 case Q81_RX_CBFC_PAUSE_FRAMES2_LO : 1038 case Q81_RX_CBFC_PAUSE_FRAMES3 : 1039 case Q81_RX_CBFC_PAUSE_FRAMES3_LO : 1040 case Q81_RX_CBFC_PAUSE_FRAMES4 : 1041 case Q81_RX_CBFC_PAUSE_FRAMES4_LO : 1042 case Q81_RX_CBFC_PAUSE_FRAMES5 : 1043 case Q81_RX_CBFC_PAUSE_FRAMES5_LO : 1044 case Q81_RX_CBFC_PAUSE_FRAMES6 : 1045 case Q81_RX_CBFC_PAUSE_FRAMES6_LO : 1046 case Q81_RX_CBFC_PAUSE_FRAMES7 : 1047 case Q81_RX_CBFC_PAUSE_FRAMES7_LO : 1048 case Q81_RX_FCOE_PKTS : 1049 case Q81_RX_FCOE_PKTS_LO : 1050 case Q81_RX_MGMT_PKTS : 1051 case Q81_RX_MGMT_PKTS_LO : 1052 case Q81_RX_NIC_FIFO_DROP : 1053 case Q81_RX_NIC_FIFO_DROP_LO : 1054 case Q81_RX_FCOE_FIFO_DROP : 1055 case Q81_RX_FCOE_FIFO_DROP_LO : 1056 case Q81_RX_MGMT_FIFO_DROP : 1057 case Q81_RX_MGMT_FIFO_DROP_LO : 1058 case Q81_RX_PKTS_PRIORITY0 : 1059 case Q81_RX_PKTS_PRIORITY0_LO : 1060 case Q81_RX_PKTS_PRIORITY1 : 1061 case Q81_RX_PKTS_PRIORITY1_LO : 1062 case Q81_RX_PKTS_PRIORITY2 : 1063 case Q81_RX_PKTS_PRIORITY2_LO : 1064 case Q81_RX_PKTS_PRIORITY3 : 1065 case Q81_RX_PKTS_PRIORITY3_LO : 1066 case Q81_RX_PKTS_PRIORITY4 : 1067 case Q81_RX_PKTS_PRIORITY4_LO : 1068 case Q81_RX_PKTS_PRIORITY5 : 1069 case Q81_RX_PKTS_PRIORITY5_LO : 1070 case Q81_RX_PKTS_PRIORITY6 : 1071 case Q81_RX_PKTS_PRIORITY6_LO : 1072 case Q81_RX_PKTS_PRIORITY7 : 1073 case Q81_RX_PKTS_PRIORITY7_LO : 1074 case Q81_RX_OCTETS_PRIORITY0 : 1075 case Q81_RX_OCTETS_PRIORITY0_LO : 1076 case Q81_RX_OCTETS_PRIORITY1 : 1077 case Q81_RX_OCTETS_PRIORITY1_LO : 1078 case Q81_RX_OCTETS_PRIORITY2 : 1079 case Q81_RX_OCTETS_PRIORITY2_LO : 1080 case Q81_RX_OCTETS_PRIORITY3 : 1081 case Q81_RX_OCTETS_PRIORITY3_LO : 1082 case Q81_RX_OCTETS_PRIORITY4 : 1083 case Q81_RX_OCTETS_PRIORITY4_LO : 1084 case Q81_RX_OCTETS_PRIORITY5 : 1085 case Q81_RX_OCTETS_PRIORITY5_LO : 1086 case Q81_RX_OCTETS_PRIORITY6 : 1087 case Q81_RX_OCTETS_PRIORITY6_LO : 1088 case Q81_RX_OCTETS_PRIORITY7 : 1089 case Q81_RX_OCTETS_PRIORITY7_LO : 1090 case Q81_TX_PKTS_PRIORITY0 : 1091 case Q81_TX_PKTS_PRIORITY0_LO : 1092 case Q81_TX_PKTS_PRIORITY1 : 1093 case Q81_TX_PKTS_PRIORITY1_LO : 1094 case Q81_TX_PKTS_PRIORITY2 : 1095 case Q81_TX_PKTS_PRIORITY2_LO : 1096 case Q81_TX_PKTS_PRIORITY3 : 1097 case Q81_TX_PKTS_PRIORITY3_LO : 1098 case Q81_TX_PKTS_PRIORITY4 : 1099 case Q81_TX_PKTS_PRIORITY4_LO : 1100 case Q81_TX_PKTS_PRIORITY5 : 1101 case Q81_TX_PKTS_PRIORITY5_LO : 1102 case Q81_TX_PKTS_PRIORITY6 : 1103 case Q81_TX_PKTS_PRIORITY6_LO : 1104 case Q81_TX_PKTS_PRIORITY7 : 1105 case Q81_TX_PKTS_PRIORITY7_LO : 1106 case Q81_TX_OCTETS_PRIORITY0 : 1107 case Q81_TX_OCTETS_PRIORITY0_LO : 1108 case Q81_TX_OCTETS_PRIORITY1 : 1109 case Q81_TX_OCTETS_PRIORITY1_LO : 1110 case Q81_TX_OCTETS_PRIORITY2 : 1111 case Q81_TX_OCTETS_PRIORITY2_LO : 1112 case Q81_TX_OCTETS_PRIORITY3 : 1113 case Q81_TX_OCTETS_PRIORITY3_LO : 1114 case Q81_TX_OCTETS_PRIORITY4 : 1115 case Q81_TX_OCTETS_PRIORITY4_LO : 1116 case Q81_TX_OCTETS_PRIORITY5 : 1117 case Q81_TX_OCTETS_PRIORITY5_LO : 1118 case Q81_TX_OCTETS_PRIORITY6 : 1119 case Q81_TX_OCTETS_PRIORITY6_LO : 1120 case Q81_TX_OCTETS_PRIORITY7 : 1121 case Q81_TX_OCTETS_PRIORITY7_LO : 1122 case Q81_RX_DISCARD_PRIORITY0 : 1123 case Q81_RX_DISCARD_PRIORITY0_LO : 1124 case Q81_RX_DISCARD_PRIORITY1 : 1125 case Q81_RX_DISCARD_PRIORITY1_LO : 1126 case Q81_RX_DISCARD_PRIORITY2 : 1127 case Q81_RX_DISCARD_PRIORITY2_LO : 1128 case Q81_RX_DISCARD_PRIORITY3 : 1129 case Q81_RX_DISCARD_PRIORITY3_LO : 1130 case Q81_RX_DISCARD_PRIORITY4 : 1131 case Q81_RX_DISCARD_PRIORITY4_LO : 1132 case Q81_RX_DISCARD_PRIORITY5 : 1133 case Q81_RX_DISCARD_PRIORITY5_LO : 1134 case Q81_RX_DISCARD_PRIORITY6 : 1135 case Q81_RX_DISCARD_PRIORITY6_LO : 1136 case Q81_RX_DISCARD_PRIORITY7 : 1137 case Q81_RX_DISCARD_PRIORITY7_LO : 1138 1139 if (o_func) 1140 ret = qls_rd_ofunc_xgmac_reg(ha, 1141 i, buf); 1142 else 1143 ret = qls_rd_xgmac_reg(ha, i, buf); 1144 1145 if (ret) 1146 *buf = Q81_BAD_DATA; 1147 1148 break; 1149 1150 default: 1151 break; 1152 } 1153 } 1154 return 0; 1155 } 1156 1157 static int 1158 qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count) 1159 { 1160 int i, ret = 0; 1161 1162 for (i = 0; i < count; i++, buf++) { 1163 ret = qls_rd_mpi_reg(ha, (offset + i), buf); 1164 1165 if (ret) 1166 return ret; 1167 } 1168 1169 return (ret); 1170 } 1171 1172 static int 1173 qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf) 1174 { 1175 uint32_t i; 1176 int ret; 1177 1178 #define Q81_RISC_124 0x0000007c 1179 #define Q81_RISC_127 0x0000007f 1180 #define Q81_SHADOW_OFFSET 0xb0000000 1181 1182 for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { 1183 ret = qls_wr_mpi_reg(ha, 1184 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124), 1185 (Q81_SHADOW_OFFSET | i << 20)); 1186 if (ret) 1187 goto exit_qls_get_mpi_shadow_regs; 1188 1189 ret = qls_mpi_risc_rd_reg(ha, 1190 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127), 1191 buf); 1192 if (ret) 1193 goto exit_qls_get_mpi_shadow_regs; 1194 } 1195 1196 exit_qls_get_mpi_shadow_regs: 1197 return ret; 1198 } 1199 1200 #define SYS_CLOCK (0x00) 1201 #define PCI_CLOCK (0x80) 1202 #define FC_CLOCK (0x140) 1203 #define XGM_CLOCK (0x180) 1204 1205 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000 1206 #define Q81_UP 0x00008000 1207 #define Q81_MAX_MUX 0x40 1208 #define Q81_MAX_MODULES 0x1F 1209 1210 static uint32_t * 1211 qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf) 1212 { 1213 uint32_t module, mux_sel, probe, lo_val, hi_val; 1214 1215 for (module = 0; module < Q81_MAX_MODULES; module ++) { 1216 if (valid[module]) { 1217 for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { 1218 probe = clock | Q81_ADDRESS_REGISTER_ENABLE | 1219 mux_sel | (module << 9); 1220 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1221 probe); 1222 1223 lo_val = READ_REG32(ha,\ 1224 Q81_CTL_XG_PROBE_MUX_DATA); 1225 1226 if (mux_sel == 0) { 1227 *buf = probe; 1228 buf ++; 1229 } 1230 1231 probe |= Q81_UP; 1232 1233 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1234 probe); 1235 hi_val = READ_REG32(ha,\ 1236 Q81_CTL_XG_PROBE_MUX_DATA); 1237 1238 *buf = lo_val; 1239 buf++; 1240 *buf = hi_val; 1241 buf++; 1242 } 1243 } 1244 } 1245 1246 return(buf); 1247 } 1248 1249 static int 1250 qls_get_probe_dump(qla_host_t *ha, uint32_t *buf) 1251 { 1252 1253 uint8_t sys_clock_valid_modules[0x20] = { 1254 1, // 0x00 1255 1, // 0x01 1256 1, // 0x02 1257 0, // 0x03 1258 1, // 0x04 1259 1, // 0x05 1260 1, // 0x06 1261 1, // 0x07 1262 1, // 0x08 1263 1, // 0x09 1264 1, // 0x0A 1265 1, // 0x0B 1266 1, // 0x0C 1267 1, // 0x0D 1268 1, // 0x0E 1269 0, // 0x0F 1270 1, // 0x10 1271 1, // 0x11 1272 1, // 0x12 1273 1, // 0x13 1274 0, // 0x14 1275 0, // 0x15 1276 0, // 0x16 1277 0, // 0x17 1278 0, // 0x18 1279 0, // 0x19 1280 0, // 0x1A 1281 0, // 0x1B 1282 0, // 0x1C 1283 0, // 0x1D 1284 0, // 0x1E 1285 0 // 0x1F 1286 }; 1287 1288 uint8_t pci_clock_valid_modules[0x20] = { 1289 1, // 0x00 1290 0, // 0x01 1291 0, // 0x02 1292 0, // 0x03 1293 0, // 0x04 1294 0, // 0x05 1295 1, // 0x06 1296 1, // 0x07 1297 0, // 0x08 1298 0, // 0x09 1299 0, // 0x0A 1300 0, // 0x0B 1301 0, // 0x0C 1302 0, // 0x0D 1303 1, // 0x0E 1304 0, // 0x0F 1305 0, // 0x10 1306 0, // 0x11 1307 0, // 0x12 1308 0, // 0x13 1309 0, // 0x14 1310 0, // 0x15 1311 0, // 0x16 1312 0, // 0x17 1313 0, // 0x18 1314 0, // 0x19 1315 0, // 0x1A 1316 0, // 0x1B 1317 0, // 0x1C 1318 0, // 0x1D 1319 0, // 0x1E 1320 0 // 0x1F 1321 }; 1322 1323 uint8_t xgm_clock_valid_modules[0x20] = { 1324 1, // 0x00 1325 0, // 0x01 1326 0, // 0x02 1327 1, // 0x03 1328 0, // 0x04 1329 0, // 0x05 1330 0, // 0x06 1331 0, // 0x07 1332 1, // 0x08 1333 1, // 0x09 1334 0, // 0x0A 1335 0, // 0x0B 1336 1, // 0x0C 1337 1, // 0x0D 1338 1, // 0x0E 1339 0, // 0x0F 1340 1, // 0x10 1341 1, // 0x11 1342 0, // 0x12 1343 0, // 0x13 1344 0, // 0x14 1345 0, // 0x15 1346 0, // 0x16 1347 0, // 0x17 1348 0, // 0x18 1349 0, // 0x19 1350 0, // 0x1A 1351 0, // 0x1B 1352 0, // 0x1C 1353 0, // 0x1D 1354 0, // 0x1E 1355 0 // 0x1F 1356 }; 1357 1358 uint8_t fc_clock_valid_modules[0x20] = { 1359 1, // 0x00 1360 0, // 0x01 1361 0, // 0x02 1362 0, // 0x03 1363 0, // 0x04 1364 0, // 0x05 1365 0, // 0x06 1366 0, // 0x07 1367 0, // 0x08 1368 0, // 0x09 1369 0, // 0x0A 1370 0, // 0x0B 1371 1, // 0x0C 1372 1, // 0x0D 1373 0, // 0x0E 1374 0, // 0x0F 1375 0, // 0x10 1376 0, // 0x11 1377 0, // 0x12 1378 0, // 0x13 1379 0, // 0x14 1380 0, // 0x15 1381 0, // 0x16 1382 0, // 0x17 1383 0, // 0x18 1384 0, // 0x19 1385 0, // 0x1A 1386 0, // 0x1B 1387 0, // 0x1C 1388 0, // 0x1D 1389 0, // 0x1E 1390 0 // 0x1F 1391 }; 1392 1393 qls_wr_mpi_reg(ha, 0x100e, 0x18a20000); 1394 1395 buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf); 1396 1397 buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf); 1398 1399 buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf); 1400 1401 buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf); 1402 1403 return(0); 1404 } 1405 1406 static void 1407 qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf) 1408 { 1409 uint32_t type, idx, idx_max; 1410 uint32_t r_idx; 1411 uint32_t r_data; 1412 uint32_t val; 1413 1414 for (type = 0; type < 4; type ++) { 1415 if (type < 2) 1416 idx_max = 8; 1417 else 1418 idx_max = 16; 1419 1420 for (idx = 0; idx < idx_max; idx ++) { 1421 val = 0x04000000 | (type << 16) | (idx << 8); 1422 WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val); 1423 1424 r_idx = 0; 1425 while ((r_idx & 0x40000000) == 0) 1426 r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX); 1427 1428 r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA); 1429 1430 *buf = type; 1431 buf ++; 1432 *buf = idx; 1433 buf ++; 1434 *buf = r_idx; 1435 buf ++; 1436 *buf = r_data; 1437 buf ++; 1438 } 1439 } 1440 } 1441 1442 static void 1443 qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf) 1444 { 1445 1446 #define Q81_RS_AND_ADR 0x06000000 1447 #define Q81_RS_ONLY 0x04000000 1448 #define Q81_NUM_TYPES 10 1449 1450 uint32_t result_index, result_data; 1451 uint32_t type; 1452 uint32_t index; 1453 uint32_t offset; 1454 uint32_t val; 1455 uint32_t initial_val; 1456 uint32_t max_index; 1457 uint32_t max_offset; 1458 1459 for (type = 0; type < Q81_NUM_TYPES; type ++) { 1460 switch (type) { 1461 case 0: // CAM 1462 initial_val = Q81_RS_AND_ADR; 1463 max_index = 512; 1464 max_offset = 3; 1465 break; 1466 1467 case 1: // Multicast MAC Address 1468 initial_val = Q81_RS_ONLY; 1469 max_index = 32; 1470 max_offset = 2; 1471 break; 1472 1473 case 2: // VLAN filter mask 1474 case 3: // MC filter mask 1475 initial_val = Q81_RS_ONLY; 1476 max_index = 4096; 1477 max_offset = 1; 1478 break; 1479 1480 case 4: // FC MAC addresses 1481 initial_val = Q81_RS_ONLY; 1482 max_index = 4; 1483 max_offset = 2; 1484 break; 1485 1486 case 5: // Mgmt MAC addresses 1487 initial_val = Q81_RS_ONLY; 1488 max_index = 8; 1489 max_offset = 2; 1490 break; 1491 1492 case 6: // Mgmt VLAN addresses 1493 initial_val = Q81_RS_ONLY; 1494 max_index = 16; 1495 max_offset = 1; 1496 break; 1497 1498 case 7: // Mgmt IPv4 address 1499 initial_val = Q81_RS_ONLY; 1500 max_index = 4; 1501 max_offset = 1; 1502 break; 1503 1504 case 8: // Mgmt IPv6 address 1505 initial_val = Q81_RS_ONLY; 1506 max_index = 4; 1507 max_offset = 4; 1508 break; 1509 1510 case 9: // Mgmt TCP/UDP Dest port 1511 initial_val = Q81_RS_ONLY; 1512 max_index = 4; 1513 max_offset = 1; 1514 break; 1515 1516 default: 1517 printf("Bad type!!! 0x%08x\n", type); 1518 max_index = 0; 1519 max_offset = 0; 1520 break; 1521 } 1522 1523 for (index = 0; index < max_index; index ++) { 1524 for (offset = 0; offset < max_offset; offset ++) { 1525 val = initial_val | (type << 16) | 1526 (index << 4) | (offset); 1527 1528 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\ 1529 val); 1530 1531 result_index = 0; 1532 1533 while ((result_index & 0x40000000) == 0) 1534 result_index = 1535 READ_REG32(ha, \ 1536 Q81_CTL_MAC_PROTO_ADDR_INDEX); 1537 1538 result_data = READ_REG32(ha,\ 1539 Q81_CTL_MAC_PROTO_ADDR_DATA); 1540 1541 *buf = result_index; 1542 buf ++; 1543 1544 *buf = result_data; 1545 buf ++; 1546 } 1547 } 1548 } 1549 } 1550 1551 static int 1552 qls_get_ets_regs(qla_host_t *ha, uint32_t *buf) 1553 { 1554 int ret = 0; 1555 int i; 1556 1557 for(i = 0; i < 8; i ++, buf ++) { 1558 WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \ 1559 ((i << 29) | 0x08000000)); 1560 *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD); 1561 } 1562 1563 for(i = 0; i < 2; i ++, buf ++) { 1564 WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \ 1565 ((i << 29) | 0x08000000)); 1566 *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD); 1567 } 1568 1569 return ret; 1570 } 1571 1572 int 1573 qls_mpi_core_dump(qla_host_t *ha) 1574 { 1575 int ret; 1576 int i; 1577 uint32_t reg, reg_val; 1578 1579 qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump; 1580 1581 ret = qls_pause_mpi_risc(ha); 1582 if (ret) { 1583 printf("Failed RISC pause. Status = 0x%.08x\n",ret); 1584 return(-1); 1585 } 1586 1587 memset(&(mpi_dump->mpi_global_header), 0, 1588 sizeof(qls_mpid_glbl_hdr_t)); 1589 1590 mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE; 1591 mpi_dump->mpi_global_header.hdr_size = 1592 sizeof(qls_mpid_glbl_hdr_t); 1593 mpi_dump->mpi_global_header.img_size = 1594 sizeof(qls_mpi_coredump_t); 1595 1596 memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump", 1597 sizeof(mpi_dump->mpi_global_header.id)); 1598 1599 qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr, 1600 Q81_NIC1_CONTROL_SEG_NUM, 1601 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)), 1602 "NIC1 Registers"); 1603 1604 qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr, 1605 Q81_NIC2_CONTROL_SEG_NUM, 1606 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)), 1607 "NIC2 Registers"); 1608 1609 qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr, 1610 Q81_NIC1_XGMAC_SEG_NUM, 1611 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)), 1612 "NIC1 XGMac Registers"); 1613 1614 qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr, 1615 Q81_NIC2_XGMAC_SEG_NUM, 1616 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)), 1617 "NIC2 XGMac Registers"); 1618 1619 if (ha->pci_func & 1) { 1620 for (i = 0; i < 64; i++) 1621 mpi_dump->nic2_regs[i] = 1622 READ_REG32(ha, i * sizeof(uint32_t)); 1623 1624 for (i = 0; i < 64; i++) 1625 mpi_dump->nic1_regs[i] = 1626 qls_rd_ofunc_reg(ha, 1627 (i * sizeof(uint32_t)) / 4); 1628 1629 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0); 1630 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1); 1631 } else { 1632 for (i = 0; i < 64; i++) 1633 mpi_dump->nic1_regs[i] = 1634 READ_REG32(ha, i * sizeof(uint32_t)); 1635 1636 for (i = 0; i < 64; i++) 1637 mpi_dump->nic2_regs[i] = 1638 qls_rd_ofunc_reg(ha, 1639 (i * sizeof(uint32_t)) / 4); 1640 1641 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0); 1642 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); 1643 } 1644 1645 qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr, 1646 Q81_XAUI1_AN_SEG_NUM, 1647 (sizeof(qls_mpid_seg_hdr_t) + 1648 sizeof(mpi_dump->serdes1_xaui_an)), 1649 "XAUI1 AN Registers"); 1650 1651 qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr, 1652 Q81_XAUI1_HSS_PCS_SEG_NUM, 1653 (sizeof(qls_mpid_seg_hdr_t) + 1654 sizeof(mpi_dump->serdes1_xaui_hss_pcs)), 1655 "XAUI1 HSS PCS Registers"); 1656 1657 qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr, 1658 Q81_XFI1_AN_SEG_NUM, 1659 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)), 1660 "XFI1 AN Registers"); 1661 1662 qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr, 1663 Q81_XFI1_TRAIN_SEG_NUM, 1664 (sizeof(qls_mpid_seg_hdr_t) + 1665 sizeof(mpi_dump->serdes1_xfi_train)), 1666 "XFI1 TRAIN Registers"); 1667 1668 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr, 1669 Q81_XFI1_HSS_PCS_SEG_NUM, 1670 (sizeof(qls_mpid_seg_hdr_t) + 1671 sizeof(mpi_dump->serdes1_xfi_hss_pcs)), 1672 "XFI1 HSS PCS Registers"); 1673 1674 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr, 1675 Q81_XFI1_HSS_TX_SEG_NUM, 1676 (sizeof(qls_mpid_seg_hdr_t) + 1677 sizeof(mpi_dump->serdes1_xfi_hss_tx)), 1678 "XFI1 HSS TX Registers"); 1679 1680 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr, 1681 Q81_XFI1_HSS_RX_SEG_NUM, 1682 (sizeof(qls_mpid_seg_hdr_t) + 1683 sizeof(mpi_dump->serdes1_xfi_hss_rx)), 1684 "XFI1 HSS RX Registers"); 1685 1686 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr, 1687 Q81_XFI1_HSS_PLL_SEG_NUM, 1688 (sizeof(qls_mpid_seg_hdr_t) + 1689 sizeof(mpi_dump->serdes1_xfi_hss_pll)), 1690 "XFI1 HSS PLL Registers"); 1691 1692 qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr, 1693 Q81_XAUI2_AN_SEG_NUM, 1694 (sizeof(qls_mpid_seg_hdr_t) + 1695 sizeof(mpi_dump->serdes2_xaui_an)), 1696 "XAUI2 AN Registers"); 1697 1698 qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr, 1699 Q81_XAUI2_HSS_PCS_SEG_NUM, 1700 (sizeof(qls_mpid_seg_hdr_t) + 1701 sizeof(mpi_dump->serdes2_xaui_hss_pcs)), 1702 "XAUI2 HSS PCS Registers"); 1703 1704 qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr, 1705 Q81_XFI2_AN_SEG_NUM, 1706 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)), 1707 "XFI2 AN Registers"); 1708 1709 qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr, 1710 Q81_XFI2_TRAIN_SEG_NUM, 1711 (sizeof(qls_mpid_seg_hdr_t) + 1712 sizeof(mpi_dump->serdes2_xfi_train)), 1713 "XFI2 TRAIN Registers"); 1714 1715 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr, 1716 Q81_XFI2_HSS_PCS_SEG_NUM, 1717 (sizeof(qls_mpid_seg_hdr_t) + 1718 sizeof(mpi_dump->serdes2_xfi_hss_pcs)), 1719 "XFI2 HSS PCS Registers"); 1720 1721 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr, 1722 Q81_XFI2_HSS_TX_SEG_NUM, 1723 (sizeof(qls_mpid_seg_hdr_t) + 1724 sizeof(mpi_dump->serdes2_xfi_hss_tx)), 1725 "XFI2 HSS TX Registers"); 1726 1727 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr, 1728 Q81_XFI2_HSS_RX_SEG_NUM, 1729 (sizeof(qls_mpid_seg_hdr_t) + 1730 sizeof(mpi_dump->serdes2_xfi_hss_rx)), 1731 "XFI2 HSS RX Registers"); 1732 1733 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr, 1734 Q81_XFI2_HSS_PLL_SEG_NUM, 1735 (sizeof(qls_mpid_seg_hdr_t) + 1736 sizeof(mpi_dump->serdes2_xfi_hss_pll)), 1737 "XFI2 HSS PLL Registers"); 1738 1739 qls_rd_serdes_regs(ha, mpi_dump); 1740 1741 qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr, 1742 Q81_CORE_SEG_NUM, 1743 (sizeof(mpi_dump->core_regs_seg_hdr) + 1744 sizeof(mpi_dump->mpi_core_regs) + 1745 sizeof(mpi_dump->mpi_core_sh_regs)), 1746 "Core Registers"); 1747 1748 ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0], 1749 Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT); 1750 1751 ret = qls_get_mpi_shadow_regs(ha, 1752 &mpi_dump->mpi_core_sh_regs[0]); 1753 1754 qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr, 1755 Q81_TEST_LOGIC_SEG_NUM, 1756 (sizeof(qls_mpid_seg_hdr_t) + 1757 sizeof(mpi_dump->test_logic_regs)), 1758 "Test Logic Regs"); 1759 1760 ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0], 1761 Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT); 1762 1763 qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr, 1764 Q81_RMII_SEG_NUM, 1765 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)), 1766 "RMII Registers"); 1767 1768 ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0], 1769 Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT); 1770 1771 qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr, 1772 Q81_FCMAC1_SEG_NUM, 1773 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)), 1774 "FCMAC1 Registers"); 1775 1776 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0], 1777 Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1778 1779 qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr, 1780 Q81_FCMAC2_SEG_NUM, 1781 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)), 1782 "FCMAC2 Registers"); 1783 1784 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0], 1785 Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1786 1787 qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr, 1788 Q81_FC1_MBOX_SEG_NUM, 1789 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)), 1790 "FC1 MBox Regs"); 1791 1792 ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0], 1793 Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1794 1795 qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr, 1796 Q81_IDE_SEG_NUM, 1797 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)), 1798 "IDE Registers"); 1799 1800 ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0], 1801 Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT); 1802 1803 qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr, 1804 Q81_NIC1_MBOX_SEG_NUM, 1805 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)), 1806 "NIC1 MBox Regs"); 1807 1808 ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0], 1809 Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1810 1811 qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr, 1812 Q81_SMBUS_SEG_NUM, 1813 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)), 1814 "SMBus Registers"); 1815 1816 ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0], 1817 Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT); 1818 1819 qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr, 1820 Q81_FC2_MBOX_SEG_NUM, 1821 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)), 1822 "FC2 MBox Regs"); 1823 1824 ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0], 1825 Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1826 1827 qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr, 1828 Q81_NIC2_MBOX_SEG_NUM, 1829 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)), 1830 "NIC2 MBox Regs"); 1831 1832 ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0], 1833 Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1834 1835 qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr, 1836 Q81_I2C_SEG_NUM, 1837 (sizeof(qls_mpid_seg_hdr_t) + 1838 sizeof(mpi_dump->i2c_regs)), 1839 "I2C Registers"); 1840 1841 ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0], 1842 Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT); 1843 1844 qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr, 1845 Q81_MEMC_SEG_NUM, 1846 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)), 1847 "MEMC Registers"); 1848 1849 ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0], 1850 Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT); 1851 1852 qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr, 1853 Q81_PBUS_SEG_NUM, 1854 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)), 1855 "PBUS Registers"); 1856 1857 ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0], 1858 Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT); 1859 1860 qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr, 1861 Q81_MDE_SEG_NUM, 1862 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)), 1863 "MDE Registers"); 1864 1865 ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0], 1866 Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT); 1867 1868 qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr, 1869 Q81_INTR_STATES_SEG_NUM, 1870 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)), 1871 "INTR States"); 1872 1873 qls_get_intr_states(ha, &mpi_dump->intr_states[0]); 1874 1875 qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr, 1876 Q81_PROBE_DUMP_SEG_NUM, 1877 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)), 1878 "Probe Dump"); 1879 1880 qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]); 1881 1882 qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr, 1883 Q81_ROUTING_INDEX_SEG_NUM, 1884 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)), 1885 "Routing Regs"); 1886 1887 qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]); 1888 1889 qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr, 1890 Q81_MAC_PROTOCOL_SEG_NUM, 1891 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)), 1892 "MAC Prot Regs"); 1893 1894 qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]); 1895 1896 qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr, 1897 Q81_ETS_SEG_NUM, 1898 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)), 1899 "ETS Registers"); 1900 1901 ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]); 1902 1903 qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr, 1904 Q81_SEM_REGS_SEG_NUM, 1905 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)), 1906 "Sem Registers"); 1907 1908 for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { 1909 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) | 1910 (Q81_CTL_SEMAPHORE >> 2); 1911 1912 ret = qls_mpi_risc_rd_reg(ha, reg, ®_val); 1913 mpi_dump->sem_regs[i] = reg_val; 1914 1915 if (ret != 0) 1916 mpi_dump->sem_regs[i] = Q81_BAD_DATA; 1917 } 1918 1919 ret = qls_unpause_mpi_risc(ha); 1920 if (ret) 1921 printf("Failed RISC unpause. Status = 0x%.08x\n",ret); 1922 1923 ret = qls_mpi_reset(ha); 1924 if (ret) 1925 printf("Failed RISC reset. Status = 0x%.08x\n",ret); 1926 1927 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000); 1928 1929 qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr, 1930 Q81_MEMC_RAM_SEG_NUM, 1931 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)), 1932 "MEMC RAM"); 1933 1934 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1935 Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT); 1936 if (ret) 1937 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret); 1938 1939 qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr, 1940 Q81_WCS_RAM_SEG_NUM, 1941 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)), 1942 "WCS RAM"); 1943 1944 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1945 Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT); 1946 if (ret) 1947 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret); 1948 1949 qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr, 1950 Q81_WQC1_SEG_NUM, 1951 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)), 1952 "WQC 1"); 1953 1954 qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr, 1955 Q81_WQC2_SEG_NUM, 1956 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)), 1957 "WQC 2"); 1958 1959 qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr, 1960 Q81_CQC1_SEG_NUM, 1961 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)), 1962 "CQC 1"); 1963 1964 qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr, 1965 Q81_CQC2_SEG_NUM, 1966 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)), 1967 "CQC 2"); 1968 1969 return 0; 1970 }
Cache object: 874b81d5ae2a24545bc9f4cf24a9caac
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