Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/qlxge/qls_dump.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: qls_dump.c 32 */ 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "qls_os.h" 37 #include "qls_hw.h" 38 #include "qls_def.h" 39 #include "qls_glbl.h" 40 #include "qls_dump.h" 41 42 qls_mpi_coredump_t ql_mpi_coredump; 43 44 #define Q81_CORE_SEG_NUM 1 45 #define Q81_TEST_LOGIC_SEG_NUM 2 46 #define Q81_RMII_SEG_NUM 3 47 #define Q81_FCMAC1_SEG_NUM 4 48 #define Q81_FCMAC2_SEG_NUM 5 49 #define Q81_FC1_MBOX_SEG_NUM 6 50 #define Q81_IDE_SEG_NUM 7 51 #define Q81_NIC1_MBOX_SEG_NUM 8 52 #define Q81_SMBUS_SEG_NUM 9 53 #define Q81_FC2_MBOX_SEG_NUM 10 54 #define Q81_NIC2_MBOX_SEG_NUM 11 55 #define Q81_I2C_SEG_NUM 12 56 #define Q81_MEMC_SEG_NUM 13 57 #define Q81_PBUS_SEG_NUM 14 58 #define Q81_MDE_SEG_NUM 15 59 #define Q81_NIC1_CONTROL_SEG_NUM 16 60 #define Q81_NIC2_CONTROL_SEG_NUM 17 61 #define Q81_NIC1_XGMAC_SEG_NUM 18 62 #define Q81_NIC2_XGMAC_SEG_NUM 19 63 #define Q81_WCS_RAM_SEG_NUM 20 64 #define Q81_MEMC_RAM_SEG_NUM 21 65 #define Q81_XAUI1_AN_SEG_NUM 22 66 #define Q81_XAUI1_HSS_PCS_SEG_NUM 23 67 #define Q81_XFI1_AN_SEG_NUM 24 68 #define Q81_XFI1_TRAIN_SEG_NUM 25 69 #define Q81_XFI1_HSS_PCS_SEG_NUM 26 70 #define Q81_XFI1_HSS_TX_SEG_NUM 27 71 #define Q81_XFI1_HSS_RX_SEG_NUM 28 72 #define Q81_XFI1_HSS_PLL_SEG_NUM 29 73 #define Q81_INTR_STATES_SEG_NUM 31 74 #define Q81_ETS_SEG_NUM 34 75 #define Q81_PROBE_DUMP_SEG_NUM 35 76 #define Q81_ROUTING_INDEX_SEG_NUM 36 77 #define Q81_MAC_PROTOCOL_SEG_NUM 37 78 #define Q81_XAUI2_AN_SEG_NUM 38 79 #define Q81_XAUI2_HSS_PCS_SEG_NUM 39 80 #define Q81_XFI2_AN_SEG_NUM 40 81 #define Q81_XFI2_TRAIN_SEG_NUM 41 82 #define Q81_XFI2_HSS_PCS_SEG_NUM 42 83 #define Q81_XFI2_HSS_TX_SEG_NUM 43 84 #define Q81_XFI2_HSS_RX_SEG_NUM 44 85 #define Q81_XFI2_HSS_PLL_SEG_NUM 45 86 #define Q81_WQC1_SEG_NUM 46 87 #define Q81_CQC1_SEG_NUM 47 88 #define Q81_WQC2_SEG_NUM 48 89 #define Q81_CQC2_SEG_NUM 49 90 #define Q81_SEM_REGS_SEG_NUM 50 91 92 enum 93 { 94 Q81_PAUSE_SRC_LO = 0x00000100, 95 Q81_PAUSE_SRC_HI = 0x00000104, 96 Q81_GLOBAL_CFG = 0x00000108, 97 Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/ 98 Q81_GLOBAL_CFG_JUMBO = (1 << 6), /*Control*/ 99 Q81_GLOBAL_CFG_TX_STAT_EN = (1 << 10), /*Control*/ 100 Q81_GLOBAL_CFG_RX_STAT_EN = (1 << 11), /*Control*/ 101 Q81_TX_CFG = 0x0000010c, 102 Q81_TX_CFG_RESET = (1 << 0), /*Control*/ 103 Q81_TX_CFG_EN = (1 << 1), /*Control*/ 104 Q81_TX_CFG_PREAM = (1 << 2), /*Control*/ 105 Q81_RX_CFG = 0x00000110, 106 Q81_RX_CFG_RESET = (1 << 0), /*Control*/ 107 Q81_RX_CFG_EN = (1 << 1), /*Control*/ 108 Q81_RX_CFG_PREAM = (1 << 2), /*Control*/ 109 Q81_FLOW_CTL = 0x0000011c, 110 Q81_PAUSE_OPCODE = 0x00000120, 111 Q81_PAUSE_TIMER = 0x00000124, 112 Q81_PAUSE_FRM_DEST_LO = 0x00000128, 113 Q81_PAUSE_FRM_DEST_HI = 0x0000012c, 114 Q81_MAC_TX_PARAMS = 0x00000134, 115 Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/ 116 Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/ 117 Q81_MAC_RX_PARAMS = 0x00000138, 118 Q81_MAC_SYS_INT = 0x00000144, 119 Q81_MAC_SYS_INT_MASK = 0x00000148, 120 Q81_MAC_MGMT_INT = 0x0000014c, 121 Q81_MAC_MGMT_IN_MASK = 0x00000150, 122 Q81_EXT_ARB_MODE = 0x000001fc, 123 Q81_TX_PKTS = 0x00000200, 124 Q81_TX_PKTS_LO = 0x00000204, 125 Q81_TX_BYTES = 0x00000208, 126 Q81_TX_BYTES_LO = 0x0000020C, 127 Q81_TX_MCAST_PKTS = 0x00000210, 128 Q81_TX_MCAST_PKTS_LO = 0x00000214, 129 Q81_TX_BCAST_PKTS = 0x00000218, 130 Q81_TX_BCAST_PKTS_LO = 0x0000021C, 131 Q81_TX_UCAST_PKTS = 0x00000220, 132 Q81_TX_UCAST_PKTS_LO = 0x00000224, 133 Q81_TX_CTL_PKTS = 0x00000228, 134 Q81_TX_CTL_PKTS_LO = 0x0000022c, 135 Q81_TX_PAUSE_PKTS = 0x00000230, 136 Q81_TX_PAUSE_PKTS_LO = 0x00000234, 137 Q81_TX_64_PKT = 0x00000238, 138 Q81_TX_64_PKT_LO = 0x0000023c, 139 Q81_TX_65_TO_127_PKT = 0x00000240, 140 Q81_TX_65_TO_127_PKT_LO = 0x00000244, 141 Q81_TX_128_TO_255_PKT = 0x00000248, 142 Q81_TX_128_TO_255_PKT_LO = 0x0000024c, 143 Q81_TX_256_511_PKT = 0x00000250, 144 Q81_TX_256_511_PKT_LO = 0x00000254, 145 Q81_TX_512_TO_1023_PKT = 0x00000258, 146 Q81_TX_512_TO_1023_PKT_LO = 0x0000025c, 147 Q81_TX_1024_TO_1518_PKT = 0x00000260, 148 Q81_TX_1024_TO_1518_PKT_LO = 0x00000264, 149 Q81_TX_1519_TO_MAX_PKT = 0x00000268, 150 Q81_TX_1519_TO_MAX_PKT_LO = 0x0000026c, 151 Q81_TX_UNDERSIZE_PKT = 0x00000270, 152 Q81_TX_UNDERSIZE_PKT_LO = 0x00000274, 153 Q81_TX_OVERSIZE_PKT = 0x00000278, 154 Q81_TX_OVERSIZE_PKT_LO = 0x0000027c, 155 Q81_RX_HALF_FULL_DET = 0x000002a0, 156 Q81_TX_HALF_FULL_DET_LO = 0x000002a4, 157 Q81_RX_OVERFLOW_DET = 0x000002a8, 158 Q81_TX_OVERFLOW_DET_LO = 0x000002ac, 159 Q81_RX_HALF_FULL_MASK = 0x000002b0, 160 Q81_TX_HALF_FULL_MASK_LO = 0x000002b4, 161 Q81_RX_OVERFLOW_MASK = 0x000002b8, 162 Q81_TX_OVERFLOW_MASK_LO = 0x000002bc, 163 Q81_STAT_CNT_CTL = 0x000002c0, 164 Q81_STAT_CNT_CTL_CLEAR_TX = (1 << 0), /*Control*/ 165 Q81_STAT_CNT_CTL_CLEAR_RX = (1 << 1), /*Control*/ 166 Q81_AUX_RX_HALF_FULL_DET = 0x000002d0, 167 Q81_AUX_TX_HALF_FULL_DET = 0x000002d4, 168 Q81_AUX_RX_OVERFLOW_DET = 0x000002d8, 169 Q81_AUX_TX_OVERFLOW_DET = 0x000002dc, 170 Q81_AUX_RX_HALF_FULL_MASK = 0x000002f0, 171 Q81_AUX_TX_HALF_FULL_MASK = 0x000002f4, 172 Q81_AUX_RX_OVERFLOW_MASK = 0x000002f8, 173 Q81_AUX_TX_OVERFLOW_MASK = 0x000002fc, 174 Q81_RX_BYTES = 0x00000300, 175 Q81_RX_BYTES_LO = 0x00000304, 176 Q81_RX_BYTES_OK = 0x00000308, 177 Q81_RX_BYTES_OK_LO = 0x0000030c, 178 Q81_RX_PKTS = 0x00000310, 179 Q81_RX_PKTS_LO = 0x00000314, 180 Q81_RX_PKTS_OK = 0x00000318, 181 Q81_RX_PKTS_OK_LO = 0x0000031c, 182 Q81_RX_BCAST_PKTS = 0x00000320, 183 Q81_RX_BCAST_PKTS_LO = 0x00000324, 184 Q81_RX_MCAST_PKTS = 0x00000328, 185 Q81_RX_MCAST_PKTS_LO = 0x0000032c, 186 Q81_RX_UCAST_PKTS = 0x00000330, 187 Q81_RX_UCAST_PKTS_LO = 0x00000334, 188 Q81_RX_UNDERSIZE_PKTS = 0x00000338, 189 Q81_RX_UNDERSIZE_PKTS_LO = 0x0000033c, 190 Q81_RX_OVERSIZE_PKTS = 0x00000340, 191 Q81_RX_OVERSIZE_PKTS_LO = 0x00000344, 192 Q81_RX_JABBER_PKTS = 0x00000348, 193 Q81_RX_JABBER_PKTS_LO = 0x0000034c, 194 Q81_RX_UNDERSIZE_FCERR_PKTS = 0x00000350, 195 Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354, 196 Q81_RX_DROP_EVENTS = 0x00000358, 197 Q81_RX_DROP_EVENTS_LO = 0x0000035c, 198 Q81_RX_FCERR_PKTS = 0x00000360, 199 Q81_RX_FCERR_PKTS_LO = 0x00000364, 200 Q81_RX_ALIGN_ERR = 0x00000368, 201 Q81_RX_ALIGN_ERR_LO = 0x0000036c, 202 Q81_RX_SYMBOL_ERR = 0x00000370, 203 Q81_RX_SYMBOL_ERR_LO = 0x00000374, 204 Q81_RX_MAC_ERR = 0x00000378, 205 Q81_RX_MAC_ERR_LO = 0x0000037c, 206 Q81_RX_CTL_PKTS = 0x00000380, 207 Q81_RX_CTL_PKTS_LO = 0x00000384, 208 Q81_RX_PAUSE_PKTS = 0x00000388, 209 Q81_RX_PAUSE_PKTS_LO = 0x0000038c, 210 Q81_RX_64_PKTS = 0x00000390, 211 Q81_RX_64_PKTS_LO = 0x00000394, 212 Q81_RX_65_TO_127_PKTS = 0x00000398, 213 Q81_RX_65_TO_127_PKTS_LO = 0x0000039c, 214 Q81_RX_128_255_PKTS = 0x000003a0, 215 Q81_RX_128_255_PKTS_LO = 0x000003a4, 216 Q81_RX_256_511_PKTS = 0x000003a8, 217 Q81_RX_256_511_PKTS_LO = 0x000003ac, 218 Q81_RX_512_TO_1023_PKTS = 0x000003b0, 219 Q81_RX_512_TO_1023_PKTS_LO = 0x000003b4, 220 Q81_RX_1024_TO_1518_PKTS = 0x000003b8, 221 Q81_RX_1024_TO_1518_PKTS_LO = 0x000003bc, 222 Q81_RX_1519_TO_MAX_PKTS = 0x000003c0, 223 Q81_RX_1519_TO_MAX_PKTS_LO = 0x000003c4, 224 Q81_RX_LEN_ERR_PKTS = 0x000003c8, 225 Q81_RX_LEN_ERR_PKTS_LO = 0x000003cc, 226 Q81_MDIO_TX_DATA = 0x00000400, 227 Q81_MDIO_RX_DATA = 0x00000410, 228 Q81_MDIO_CMD = 0x00000420, 229 Q81_MDIO_PHY_ADDR = 0x00000430, 230 Q81_MDIO_PORT = 0x00000440, 231 Q81_MDIO_STATUS = 0x00000450, 232 Q81_TX_CBFC_PAUSE_FRAMES0 = 0x00000500, 233 Q81_TX_CBFC_PAUSE_FRAMES0_LO = 0x00000504, 234 Q81_TX_CBFC_PAUSE_FRAMES1 = 0x00000508, 235 Q81_TX_CBFC_PAUSE_FRAMES1_LO = 0x0000050C, 236 Q81_TX_CBFC_PAUSE_FRAMES2 = 0x00000510, 237 Q81_TX_CBFC_PAUSE_FRAMES2_LO = 0x00000514, 238 Q81_TX_CBFC_PAUSE_FRAMES3 = 0x00000518, 239 Q81_TX_CBFC_PAUSE_FRAMES3_LO = 0x0000051C, 240 Q81_TX_CBFC_PAUSE_FRAMES4 = 0x00000520, 241 Q81_TX_CBFC_PAUSE_FRAMES4_LO = 0x00000524, 242 Q81_TX_CBFC_PAUSE_FRAMES5 = 0x00000528, 243 Q81_TX_CBFC_PAUSE_FRAMES5_LO = 0x0000052C, 244 Q81_TX_CBFC_PAUSE_FRAMES6 = 0x00000530, 245 Q81_TX_CBFC_PAUSE_FRAMES6_LO = 0x00000534, 246 Q81_TX_CBFC_PAUSE_FRAMES7 = 0x00000538, 247 Q81_TX_CBFC_PAUSE_FRAMES7_LO = 0x0000053C, 248 Q81_TX_FCOE_PKTS = 0x00000540, 249 Q81_TX_FCOE_PKTS_LO = 0x00000544, 250 Q81_TX_MGMT_PKTS = 0x00000548, 251 Q81_TX_MGMT_PKTS_LO = 0x0000054C, 252 Q81_RX_CBFC_PAUSE_FRAMES0 = 0x00000568, 253 Q81_RX_CBFC_PAUSE_FRAMES0_LO = 0x0000056C, 254 Q81_RX_CBFC_PAUSE_FRAMES1 = 0x00000570, 255 Q81_RX_CBFC_PAUSE_FRAMES1_LO = 0x00000574, 256 Q81_RX_CBFC_PAUSE_FRAMES2 = 0x00000578, 257 Q81_RX_CBFC_PAUSE_FRAMES2_LO = 0x0000057C, 258 Q81_RX_CBFC_PAUSE_FRAMES3 = 0x00000580, 259 Q81_RX_CBFC_PAUSE_FRAMES3_LO = 0x00000584, 260 Q81_RX_CBFC_PAUSE_FRAMES4 = 0x00000588, 261 Q81_RX_CBFC_PAUSE_FRAMES4_LO = 0x0000058C, 262 Q81_RX_CBFC_PAUSE_FRAMES5 = 0x00000590, 263 Q81_RX_CBFC_PAUSE_FRAMES5_LO = 0x00000594, 264 Q81_RX_CBFC_PAUSE_FRAMES6 = 0x00000598, 265 Q81_RX_CBFC_PAUSE_FRAMES6_LO = 0x0000059C, 266 Q81_RX_CBFC_PAUSE_FRAMES7 = 0x000005A0, 267 Q81_RX_CBFC_PAUSE_FRAMES7_LO = 0x000005A4, 268 Q81_RX_FCOE_PKTS = 0x000005A8, 269 Q81_RX_FCOE_PKTS_LO = 0x000005AC, 270 Q81_RX_MGMT_PKTS = 0x000005B0, 271 Q81_RX_MGMT_PKTS_LO = 0x000005B4, 272 Q81_RX_NIC_FIFO_DROP = 0x000005B8, 273 Q81_RX_NIC_FIFO_DROP_LO = 0x000005BC, 274 Q81_RX_FCOE_FIFO_DROP = 0x000005C0, 275 Q81_RX_FCOE_FIFO_DROP_LO = 0x000005C4, 276 Q81_RX_MGMT_FIFO_DROP = 0x000005C8, 277 Q81_RX_MGMT_FIFO_DROP_LO = 0x000005CC, 278 Q81_RX_PKTS_PRIORITY0 = 0x00000600, 279 Q81_RX_PKTS_PRIORITY0_LO = 0x00000604, 280 Q81_RX_PKTS_PRIORITY1 = 0x00000608, 281 Q81_RX_PKTS_PRIORITY1_LO = 0x0000060C, 282 Q81_RX_PKTS_PRIORITY2 = 0x00000610, 283 Q81_RX_PKTS_PRIORITY2_LO = 0x00000614, 284 Q81_RX_PKTS_PRIORITY3 = 0x00000618, 285 Q81_RX_PKTS_PRIORITY3_LO = 0x0000061C, 286 Q81_RX_PKTS_PRIORITY4 = 0x00000620, 287 Q81_RX_PKTS_PRIORITY4_LO = 0x00000624, 288 Q81_RX_PKTS_PRIORITY5 = 0x00000628, 289 Q81_RX_PKTS_PRIORITY5_LO = 0x0000062C, 290 Q81_RX_PKTS_PRIORITY6 = 0x00000630, 291 Q81_RX_PKTS_PRIORITY6_LO = 0x00000634, 292 Q81_RX_PKTS_PRIORITY7 = 0x00000638, 293 Q81_RX_PKTS_PRIORITY7_LO = 0x0000063C, 294 Q81_RX_OCTETS_PRIORITY0 = 0x00000640, 295 Q81_RX_OCTETS_PRIORITY0_LO = 0x00000644, 296 Q81_RX_OCTETS_PRIORITY1 = 0x00000648, 297 Q81_RX_OCTETS_PRIORITY1_LO = 0x0000064C, 298 Q81_RX_OCTETS_PRIORITY2 = 0x00000650, 299 Q81_RX_OCTETS_PRIORITY2_LO = 0x00000654, 300 Q81_RX_OCTETS_PRIORITY3 = 0x00000658, 301 Q81_RX_OCTETS_PRIORITY3_LO = 0x0000065C, 302 Q81_RX_OCTETS_PRIORITY4 = 0x00000660, 303 Q81_RX_OCTETS_PRIORITY4_LO = 0x00000664, 304 Q81_RX_OCTETS_PRIORITY5 = 0x00000668, 305 Q81_RX_OCTETS_PRIORITY5_LO = 0x0000066C, 306 Q81_RX_OCTETS_PRIORITY6 = 0x00000670, 307 Q81_RX_OCTETS_PRIORITY6_LO = 0x00000674, 308 Q81_RX_OCTETS_PRIORITY7 = 0x00000678, 309 Q81_RX_OCTETS_PRIORITY7_LO = 0x0000067C, 310 Q81_TX_PKTS_PRIORITY0 = 0x00000680, 311 Q81_TX_PKTS_PRIORITY0_LO = 0x00000684, 312 Q81_TX_PKTS_PRIORITY1 = 0x00000688, 313 Q81_TX_PKTS_PRIORITY1_LO = 0x0000068C, 314 Q81_TX_PKTS_PRIORITY2 = 0x00000690, 315 Q81_TX_PKTS_PRIORITY2_LO = 0x00000694, 316 Q81_TX_PKTS_PRIORITY3 = 0x00000698, 317 Q81_TX_PKTS_PRIORITY3_LO = 0x0000069C, 318 Q81_TX_PKTS_PRIORITY4 = 0x000006A0, 319 Q81_TX_PKTS_PRIORITY4_LO = 0x000006A4, 320 Q81_TX_PKTS_PRIORITY5 = 0x000006A8, 321 Q81_TX_PKTS_PRIORITY5_LO = 0x000006AC, 322 Q81_TX_PKTS_PRIORITY6 = 0x000006B0, 323 Q81_TX_PKTS_PRIORITY6_LO = 0x000006B4, 324 Q81_TX_PKTS_PRIORITY7 = 0x000006B8, 325 Q81_TX_PKTS_PRIORITY7_LO = 0x000006BC, 326 Q81_TX_OCTETS_PRIORITY0 = 0x000006C0, 327 Q81_TX_OCTETS_PRIORITY0_LO = 0x000006C4, 328 Q81_TX_OCTETS_PRIORITY1 = 0x000006C8, 329 Q81_TX_OCTETS_PRIORITY1_LO = 0x000006CC, 330 Q81_TX_OCTETS_PRIORITY2 = 0x000006D0, 331 Q81_TX_OCTETS_PRIORITY2_LO = 0x000006D4, 332 Q81_TX_OCTETS_PRIORITY3 = 0x000006D8, 333 Q81_TX_OCTETS_PRIORITY3_LO = 0x000006DC, 334 Q81_TX_OCTETS_PRIORITY4 = 0x000006E0, 335 Q81_TX_OCTETS_PRIORITY4_LO = 0x000006E4, 336 Q81_TX_OCTETS_PRIORITY5 = 0x000006E8, 337 Q81_TX_OCTETS_PRIORITY5_LO = 0x000006EC, 338 Q81_TX_OCTETS_PRIORITY6 = 0x000006F0, 339 Q81_TX_OCTETS_PRIORITY6_LO = 0x000006F4, 340 Q81_TX_OCTETS_PRIORITY7 = 0x000006F8, 341 Q81_TX_OCTETS_PRIORITY7_LO = 0x000006FC, 342 Q81_RX_DISCARD_PRIORITY0 = 0x00000700, 343 Q81_RX_DISCARD_PRIORITY0_LO = 0x00000704, 344 Q81_RX_DISCARD_PRIORITY1 = 0x00000708, 345 Q81_RX_DISCARD_PRIORITY1_LO = 0x0000070C, 346 Q81_RX_DISCARD_PRIORITY2 = 0x00000710, 347 Q81_RX_DISCARD_PRIORITY2_LO = 0x00000714, 348 Q81_RX_DISCARD_PRIORITY3 = 0x00000718, 349 Q81_RX_DISCARD_PRIORITY3_LO = 0x0000071C, 350 Q81_RX_DISCARD_PRIORITY4 = 0x00000720, 351 Q81_RX_DISCARD_PRIORITY4_LO = 0x00000724, 352 Q81_RX_DISCARD_PRIORITY5 = 0x00000728, 353 Q81_RX_DISCARD_PRIORITY5_LO = 0x0000072C, 354 Q81_RX_DISCARD_PRIORITY6 = 0x00000730, 355 Q81_RX_DISCARD_PRIORITY6_LO = 0x00000734, 356 Q81_RX_DISCARD_PRIORITY7 = 0x00000738, 357 Q81_RX_DISCARD_PRIORITY7_LO = 0x0000073C 358 }; 359 360 static void 361 qls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num, 362 uint32_t seg_size, unsigned char *desc) 363 { 364 memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t)); 365 366 seg_hdr->cookie = Q81_MPID_COOKIE; 367 seg_hdr->seg_num = seg_num; 368 seg_hdr->seg_size = seg_size; 369 370 memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1); 371 372 return; 373 } 374 375 static int 376 qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit) 377 { 378 uint32_t data; 379 int count = 10; 380 381 while (count) { 382 data = READ_REG32(ha, reg); 383 384 if (data & err_bit) 385 return (-1); 386 else if (data & bit) 387 return (0); 388 389 qls_mdelay(__func__, 10); 390 count--; 391 } 392 return (-1); 393 } 394 395 static int 396 qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 397 { 398 int ret; 399 400 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 401 Q81_CTL_PROC_ADDR_ERR); 402 403 if (ret) 404 goto exit_qls_rd_mpi_reg; 405 406 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); 407 408 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 409 Q81_CTL_PROC_ADDR_ERR); 410 411 if (ret) 412 goto exit_qls_rd_mpi_reg; 413 414 *data = READ_REG32(ha, Q81_CTL_PROC_DATA); 415 416 exit_qls_rd_mpi_reg: 417 return (ret); 418 } 419 420 static int 421 qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data) 422 { 423 int ret = 0; 424 425 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 426 Q81_CTL_PROC_ADDR_ERR); 427 if (ret) 428 goto exit_qls_wr_mpi_reg; 429 430 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); 431 432 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); 433 434 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 435 Q81_CTL_PROC_ADDR_ERR); 436 exit_qls_wr_mpi_reg: 437 return (ret); 438 } 439 440 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002 441 #define Q81_INVALID_NUM 0xFFFFFFFF 442 443 #define Q81_NIC1_FUNC_ENABLE 0x00000001 444 #define Q81_NIC1_FUNC_MASK 0x0000000e 445 #define Q81_NIC1_FUNC_SHIFT 1 446 #define Q81_NIC2_FUNC_ENABLE 0x00000010 447 #define Q81_NIC2_FUNC_MASK 0x000000e0 448 #define Q81_NIC2_FUNC_SHIFT 5 449 #define Q81_FUNCTION_SHIFT 6 450 451 static uint32_t 452 qls_get_other_fnum(qla_host_t *ha) 453 { 454 int ret; 455 uint32_t o_func; 456 uint32_t test_logic; 457 uint32_t nic1_fnum = Q81_INVALID_NUM; 458 uint32_t nic2_fnum = Q81_INVALID_NUM; 459 460 ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic); 461 if (ret) 462 return(Q81_INVALID_NUM); 463 464 if (test_logic & Q81_NIC1_FUNC_ENABLE) 465 nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >> 466 Q81_NIC1_FUNC_SHIFT; 467 468 if (test_logic & Q81_NIC2_FUNC_ENABLE) 469 nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >> 470 Q81_NIC2_FUNC_SHIFT; 471 472 if (ha->pci_func == 0) 473 o_func = nic2_fnum; 474 else 475 o_func = nic1_fnum; 476 477 return(o_func); 478 } 479 480 static uint32_t 481 qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg) 482 { 483 uint32_t ofunc; 484 uint32_t data; 485 int ret = 0; 486 487 ofunc = qls_get_other_fnum(ha); 488 489 if (ofunc == Q81_INVALID_NUM) 490 return(Q81_INVALID_NUM); 491 492 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 493 494 ret = qls_rd_mpi_reg(ha, reg, &data); 495 496 if (ret != 0) 497 return(Q81_INVALID_NUM); 498 499 return(data); 500 } 501 502 static void 503 qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value) 504 { 505 uint32_t ofunc; 506 int ret = 0; 507 508 ofunc = qls_get_other_fnum(ha); 509 510 if (ofunc == Q81_INVALID_NUM) 511 return; 512 513 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 514 515 ret = qls_wr_mpi_reg(ha, reg, value); 516 517 return; 518 } 519 520 static int 521 qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, 522 uint32_t err_bit) 523 { 524 uint32_t data; 525 int count = 10; 526 527 while (count) { 528 data = qls_rd_ofunc_reg(ha, reg); 529 530 if (data & err_bit) 531 return (-1); 532 else if (data & bit) 533 return (0); 534 535 qls_mdelay(__func__, 10); 536 count--; 537 } 538 return (-1); 539 } 540 541 #define Q81_XG_SERDES_ADDR_RDY BIT_31 542 #define Q81_XG_SERDES_ADDR_READ BIT_30 543 544 static int 545 qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 546 { 547 int ret; 548 549 /* wait for reg to come ready */ 550 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 551 Q81_XG_SERDES_ADDR_RDY, 0); 552 if (ret) 553 goto exit_qls_rd_ofunc_serdes_reg; 554 555 /* set up for reg read */ 556 qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 557 (reg | Q81_XG_SERDES_ADDR_READ)); 558 559 /* wait for reg to come ready */ 560 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 561 Q81_XG_SERDES_ADDR_RDY, 0); 562 if (ret) 563 goto exit_qls_rd_ofunc_serdes_reg; 564 565 /* get the data */ 566 *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2)); 567 568 exit_qls_rd_ofunc_serdes_reg: 569 return ret; 570 } 571 572 #define Q81_XGMAC_ADDR_RDY BIT_31 573 #define Q81_XGMAC_ADDR_R BIT_30 574 #define Q81_XGMAC_ADDR_XME BIT_29 575 576 static int 577 qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 578 { 579 int ret = 0; 580 581 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 582 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 583 584 if (ret) 585 goto exit_qls_rd_ofunc_xgmac_reg; 586 587 qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2), 588 (reg | Q81_XGMAC_ADDR_R)); 589 590 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 591 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 592 if (ret) 593 goto exit_qls_rd_ofunc_xgmac_reg; 594 595 *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA); 596 597 exit_qls_rd_ofunc_xgmac_reg: 598 return ret; 599 } 600 601 static int 602 qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 603 { 604 int ret; 605 606 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 607 Q81_XG_SERDES_ADDR_RDY, 0); 608 609 if (ret) 610 goto exit_qls_rd_serdes_reg; 611 612 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ 613 (reg | Q81_XG_SERDES_ADDR_READ)); 614 615 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 616 Q81_XG_SERDES_ADDR_RDY, 0); 617 618 if (ret) 619 goto exit_qls_rd_serdes_reg; 620 621 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA); 622 623 exit_qls_rd_serdes_reg: 624 625 return ret; 626 } 627 628 static void 629 qls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr, 630 uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid) 631 { 632 int ret = -1; 633 634 if (dvalid) 635 ret = qls_rd_serdes_reg(ha, addr, dptr); 636 637 if (ret) 638 *dptr = Q81_BAD_DATA; 639 640 ret = -1; 641 642 if(ind_valid) 643 ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr); 644 645 if (ret) 646 *ind_ptr = Q81_BAD_DATA; 647 } 648 649 #define Q81_XFI1_POWERED_UP 0x00000005 650 #define Q81_XFI2_POWERED_UP 0x0000000A 651 #define Q81_XAUI_POWERED_UP 0x00000001 652 653 static int 654 qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump) 655 { 656 int ret; 657 uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid; 658 uint32_t temp, xaui_reg, i; 659 uint32_t *dptr, *indptr; 660 661 xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0; 662 663 xaui_reg = 0x800; 664 665 ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp); 666 if (ret) 667 temp = 0; 668 669 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 670 xaui_ind_valid = 1; 671 672 ret = qls_rd_serdes_reg(ha, xaui_reg, &temp); 673 if (ret) 674 temp = 0; 675 676 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 677 xaui_d_valid = 1; 678 679 ret = qls_rd_serdes_reg(ha, 0x1E06, &temp); 680 if (ret) 681 temp = 0; 682 683 if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) { 684 if (ha->pci_func & 1) 685 xfi_ind_valid = 1; /* NIC 2, so the indirect 686 (NIC1) xfi is up*/ 687 else 688 xfi_d_valid = 1; 689 } 690 691 if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) { 692 if(ha->pci_func & 1) 693 xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1) 694 xfi is up */ 695 else 696 xfi_ind_valid = 1; 697 } 698 699 if (ha->pci_func & 1) { 700 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 701 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 702 } else { 703 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 704 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 705 } 706 707 for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) { 708 qls_get_both_serdes(ha, i, dptr, indptr, 709 xaui_d_valid, xaui_ind_valid); 710 } 711 712 if (ha->pci_func & 1) { 713 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 714 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 715 } else { 716 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 717 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 718 } 719 720 for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) { 721 qls_get_both_serdes(ha, i, dptr, indptr, 722 xaui_d_valid, xaui_ind_valid); 723 } 724 725 if (ha->pci_func & 1) { 726 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 727 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 728 } else { 729 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 730 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 731 } 732 733 for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) { 734 qls_get_both_serdes(ha, i, dptr, indptr, 735 xfi_d_valid, xfi_ind_valid); 736 } 737 738 if (ha->pci_func & 1) { 739 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 740 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 741 } else { 742 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 743 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 744 } 745 746 for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) { 747 qls_get_both_serdes(ha, i, dptr, indptr, 748 xfi_d_valid, xfi_ind_valid); 749 } 750 751 if (ha->pci_func & 1) { 752 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 753 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 754 } else { 755 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 756 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 757 } 758 759 for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) { 760 qls_get_both_serdes(ha, i, dptr, indptr, 761 xfi_d_valid, xfi_ind_valid); 762 } 763 764 if (ha->pci_func & 1) { 765 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 766 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 767 } else { 768 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 769 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 770 } 771 772 for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) { 773 qls_get_both_serdes(ha, i, dptr, indptr, 774 xfi_d_valid, xfi_ind_valid); 775 } 776 777 if (ha->pci_func & 1) { 778 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 779 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 780 } else { 781 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 782 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 783 } 784 785 for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) { 786 qls_get_both_serdes(ha, i, dptr, indptr, 787 xfi_d_valid, xfi_ind_valid); 788 } 789 790 if (ha->pci_func & 1) { 791 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 792 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 793 } else { 794 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 795 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 796 } 797 798 for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) { 799 qls_get_both_serdes(ha, i, dptr, indptr, 800 xfi_d_valid, xfi_ind_valid); 801 } 802 803 return(0); 804 } 805 806 static int 807 qls_unpause_mpi_risc(qla_host_t *ha) 808 { 809 uint32_t data; 810 811 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 812 813 if (!(data & Q81_CTL_HCS_RISC_PAUSED)) 814 return -1; 815 816 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 817 Q81_CTL_HCS_CMD_CLR_RISC_PAUSE); 818 819 return 0; 820 } 821 822 static int 823 qls_pause_mpi_risc(qla_host_t *ha) 824 { 825 uint32_t data; 826 int count = 10; 827 828 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 829 Q81_CTL_HCS_CMD_SET_RISC_PAUSE); 830 831 do { 832 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 833 834 if (data & Q81_CTL_HCS_RISC_PAUSED) 835 break; 836 837 qls_mdelay(__func__, 10); 838 839 count--; 840 841 } while (count); 842 843 return ((count == 0) ? -1 : 0); 844 } 845 846 static void 847 qls_get_intr_states(qla_host_t *ha, uint32_t *buf) 848 { 849 int i; 850 851 for (i = 0; i < MAX_RX_RINGS; i++, buf++) { 852 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); 853 854 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); 855 } 856 } 857 858 static int 859 qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data) 860 { 861 int ret = 0; 862 863 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 864 Q81_XGMAC_ADDR_XME); 865 if (ret) 866 goto exit_qls_rd_xgmac_reg; 867 868 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); 869 870 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 871 Q81_XGMAC_ADDR_XME); 872 if (ret) 873 goto exit_qls_rd_xgmac_reg; 874 875 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA); 876 877 exit_qls_rd_xgmac_reg: 878 return ret; 879 } 880 881 static int 882 qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func) 883 { 884 int ret = 0; 885 int i; 886 887 for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { 888 switch (i) { 889 case Q81_PAUSE_SRC_LO : 890 case Q81_PAUSE_SRC_HI : 891 case Q81_GLOBAL_CFG : 892 case Q81_TX_CFG : 893 case Q81_RX_CFG : 894 case Q81_FLOW_CTL : 895 case Q81_PAUSE_OPCODE : 896 case Q81_PAUSE_TIMER : 897 case Q81_PAUSE_FRM_DEST_LO : 898 case Q81_PAUSE_FRM_DEST_HI : 899 case Q81_MAC_TX_PARAMS : 900 case Q81_MAC_RX_PARAMS : 901 case Q81_MAC_SYS_INT : 902 case Q81_MAC_SYS_INT_MASK : 903 case Q81_MAC_MGMT_INT : 904 case Q81_MAC_MGMT_IN_MASK : 905 case Q81_EXT_ARB_MODE : 906 case Q81_TX_PKTS : 907 case Q81_TX_PKTS_LO : 908 case Q81_TX_BYTES : 909 case Q81_TX_BYTES_LO : 910 case Q81_TX_MCAST_PKTS : 911 case Q81_TX_MCAST_PKTS_LO : 912 case Q81_TX_BCAST_PKTS : 913 case Q81_TX_BCAST_PKTS_LO : 914 case Q81_TX_UCAST_PKTS : 915 case Q81_TX_UCAST_PKTS_LO : 916 case Q81_TX_CTL_PKTS : 917 case Q81_TX_CTL_PKTS_LO : 918 case Q81_TX_PAUSE_PKTS : 919 case Q81_TX_PAUSE_PKTS_LO : 920 case Q81_TX_64_PKT : 921 case Q81_TX_64_PKT_LO : 922 case Q81_TX_65_TO_127_PKT : 923 case Q81_TX_65_TO_127_PKT_LO : 924 case Q81_TX_128_TO_255_PKT : 925 case Q81_TX_128_TO_255_PKT_LO : 926 case Q81_TX_256_511_PKT : 927 case Q81_TX_256_511_PKT_LO : 928 case Q81_TX_512_TO_1023_PKT : 929 case Q81_TX_512_TO_1023_PKT_LO : 930 case Q81_TX_1024_TO_1518_PKT : 931 case Q81_TX_1024_TO_1518_PKT_LO : 932 case Q81_TX_1519_TO_MAX_PKT : 933 case Q81_TX_1519_TO_MAX_PKT_LO : 934 case Q81_TX_UNDERSIZE_PKT : 935 case Q81_TX_UNDERSIZE_PKT_LO : 936 case Q81_TX_OVERSIZE_PKT : 937 case Q81_TX_OVERSIZE_PKT_LO : 938 case Q81_RX_HALF_FULL_DET : 939 case Q81_TX_HALF_FULL_DET_LO : 940 case Q81_RX_OVERFLOW_DET : 941 case Q81_TX_OVERFLOW_DET_LO : 942 case Q81_RX_HALF_FULL_MASK : 943 case Q81_TX_HALF_FULL_MASK_LO : 944 case Q81_RX_OVERFLOW_MASK : 945 case Q81_TX_OVERFLOW_MASK_LO : 946 case Q81_STAT_CNT_CTL : 947 case Q81_AUX_RX_HALF_FULL_DET : 948 case Q81_AUX_TX_HALF_FULL_DET : 949 case Q81_AUX_RX_OVERFLOW_DET : 950 case Q81_AUX_TX_OVERFLOW_DET : 951 case Q81_AUX_RX_HALF_FULL_MASK : 952 case Q81_AUX_TX_HALF_FULL_MASK : 953 case Q81_AUX_RX_OVERFLOW_MASK : 954 case Q81_AUX_TX_OVERFLOW_MASK : 955 case Q81_RX_BYTES : 956 case Q81_RX_BYTES_LO : 957 case Q81_RX_BYTES_OK : 958 case Q81_RX_BYTES_OK_LO : 959 case Q81_RX_PKTS : 960 case Q81_RX_PKTS_LO : 961 case Q81_RX_PKTS_OK : 962 case Q81_RX_PKTS_OK_LO : 963 case Q81_RX_BCAST_PKTS : 964 case Q81_RX_BCAST_PKTS_LO : 965 case Q81_RX_MCAST_PKTS : 966 case Q81_RX_MCAST_PKTS_LO : 967 case Q81_RX_UCAST_PKTS : 968 case Q81_RX_UCAST_PKTS_LO : 969 case Q81_RX_UNDERSIZE_PKTS : 970 case Q81_RX_UNDERSIZE_PKTS_LO : 971 case Q81_RX_OVERSIZE_PKTS : 972 case Q81_RX_OVERSIZE_PKTS_LO : 973 case Q81_RX_JABBER_PKTS : 974 case Q81_RX_JABBER_PKTS_LO : 975 case Q81_RX_UNDERSIZE_FCERR_PKTS : 976 case Q81_RX_UNDERSIZE_FCERR_PKTS_LO : 977 case Q81_RX_DROP_EVENTS : 978 case Q81_RX_DROP_EVENTS_LO : 979 case Q81_RX_FCERR_PKTS : 980 case Q81_RX_FCERR_PKTS_LO : 981 case Q81_RX_ALIGN_ERR : 982 case Q81_RX_ALIGN_ERR_LO : 983 case Q81_RX_SYMBOL_ERR : 984 case Q81_RX_SYMBOL_ERR_LO : 985 case Q81_RX_MAC_ERR : 986 case Q81_RX_MAC_ERR_LO : 987 case Q81_RX_CTL_PKTS : 988 case Q81_RX_CTL_PKTS_LO : 989 case Q81_RX_PAUSE_PKTS : 990 case Q81_RX_PAUSE_PKTS_LO : 991 case Q81_RX_64_PKTS : 992 case Q81_RX_64_PKTS_LO : 993 case Q81_RX_65_TO_127_PKTS : 994 case Q81_RX_65_TO_127_PKTS_LO : 995 case Q81_RX_128_255_PKTS : 996 case Q81_RX_128_255_PKTS_LO : 997 case Q81_RX_256_511_PKTS : 998 case Q81_RX_256_511_PKTS_LO : 999 case Q81_RX_512_TO_1023_PKTS : 1000 case Q81_RX_512_TO_1023_PKTS_LO : 1001 case Q81_RX_1024_TO_1518_PKTS : 1002 case Q81_RX_1024_TO_1518_PKTS_LO : 1003 case Q81_RX_1519_TO_MAX_PKTS : 1004 case Q81_RX_1519_TO_MAX_PKTS_LO : 1005 case Q81_RX_LEN_ERR_PKTS : 1006 case Q81_RX_LEN_ERR_PKTS_LO : 1007 case Q81_MDIO_TX_DATA : 1008 case Q81_MDIO_RX_DATA : 1009 case Q81_MDIO_CMD : 1010 case Q81_MDIO_PHY_ADDR : 1011 case Q81_MDIO_PORT : 1012 case Q81_MDIO_STATUS : 1013 case Q81_TX_CBFC_PAUSE_FRAMES0 : 1014 case Q81_TX_CBFC_PAUSE_FRAMES0_LO : 1015 case Q81_TX_CBFC_PAUSE_FRAMES1 : 1016 case Q81_TX_CBFC_PAUSE_FRAMES1_LO : 1017 case Q81_TX_CBFC_PAUSE_FRAMES2 : 1018 case Q81_TX_CBFC_PAUSE_FRAMES2_LO : 1019 case Q81_TX_CBFC_PAUSE_FRAMES3 : 1020 case Q81_TX_CBFC_PAUSE_FRAMES3_LO : 1021 case Q81_TX_CBFC_PAUSE_FRAMES4 : 1022 case Q81_TX_CBFC_PAUSE_FRAMES4_LO : 1023 case Q81_TX_CBFC_PAUSE_FRAMES5 : 1024 case Q81_TX_CBFC_PAUSE_FRAMES5_LO : 1025 case Q81_TX_CBFC_PAUSE_FRAMES6 : 1026 case Q81_TX_CBFC_PAUSE_FRAMES6_LO : 1027 case Q81_TX_CBFC_PAUSE_FRAMES7 : 1028 case Q81_TX_CBFC_PAUSE_FRAMES7_LO : 1029 case Q81_TX_FCOE_PKTS : 1030 case Q81_TX_FCOE_PKTS_LO : 1031 case Q81_TX_MGMT_PKTS : 1032 case Q81_TX_MGMT_PKTS_LO : 1033 case Q81_RX_CBFC_PAUSE_FRAMES0 : 1034 case Q81_RX_CBFC_PAUSE_FRAMES0_LO : 1035 case Q81_RX_CBFC_PAUSE_FRAMES1 : 1036 case Q81_RX_CBFC_PAUSE_FRAMES1_LO : 1037 case Q81_RX_CBFC_PAUSE_FRAMES2 : 1038 case Q81_RX_CBFC_PAUSE_FRAMES2_LO : 1039 case Q81_RX_CBFC_PAUSE_FRAMES3 : 1040 case Q81_RX_CBFC_PAUSE_FRAMES3_LO : 1041 case Q81_RX_CBFC_PAUSE_FRAMES4 : 1042 case Q81_RX_CBFC_PAUSE_FRAMES4_LO : 1043 case Q81_RX_CBFC_PAUSE_FRAMES5 : 1044 case Q81_RX_CBFC_PAUSE_FRAMES5_LO : 1045 case Q81_RX_CBFC_PAUSE_FRAMES6 : 1046 case Q81_RX_CBFC_PAUSE_FRAMES6_LO : 1047 case Q81_RX_CBFC_PAUSE_FRAMES7 : 1048 case Q81_RX_CBFC_PAUSE_FRAMES7_LO : 1049 case Q81_RX_FCOE_PKTS : 1050 case Q81_RX_FCOE_PKTS_LO : 1051 case Q81_RX_MGMT_PKTS : 1052 case Q81_RX_MGMT_PKTS_LO : 1053 case Q81_RX_NIC_FIFO_DROP : 1054 case Q81_RX_NIC_FIFO_DROP_LO : 1055 case Q81_RX_FCOE_FIFO_DROP : 1056 case Q81_RX_FCOE_FIFO_DROP_LO : 1057 case Q81_RX_MGMT_FIFO_DROP : 1058 case Q81_RX_MGMT_FIFO_DROP_LO : 1059 case Q81_RX_PKTS_PRIORITY0 : 1060 case Q81_RX_PKTS_PRIORITY0_LO : 1061 case Q81_RX_PKTS_PRIORITY1 : 1062 case Q81_RX_PKTS_PRIORITY1_LO : 1063 case Q81_RX_PKTS_PRIORITY2 : 1064 case Q81_RX_PKTS_PRIORITY2_LO : 1065 case Q81_RX_PKTS_PRIORITY3 : 1066 case Q81_RX_PKTS_PRIORITY3_LO : 1067 case Q81_RX_PKTS_PRIORITY4 : 1068 case Q81_RX_PKTS_PRIORITY4_LO : 1069 case Q81_RX_PKTS_PRIORITY5 : 1070 case Q81_RX_PKTS_PRIORITY5_LO : 1071 case Q81_RX_PKTS_PRIORITY6 : 1072 case Q81_RX_PKTS_PRIORITY6_LO : 1073 case Q81_RX_PKTS_PRIORITY7 : 1074 case Q81_RX_PKTS_PRIORITY7_LO : 1075 case Q81_RX_OCTETS_PRIORITY0 : 1076 case Q81_RX_OCTETS_PRIORITY0_LO : 1077 case Q81_RX_OCTETS_PRIORITY1 : 1078 case Q81_RX_OCTETS_PRIORITY1_LO : 1079 case Q81_RX_OCTETS_PRIORITY2 : 1080 case Q81_RX_OCTETS_PRIORITY2_LO : 1081 case Q81_RX_OCTETS_PRIORITY3 : 1082 case Q81_RX_OCTETS_PRIORITY3_LO : 1083 case Q81_RX_OCTETS_PRIORITY4 : 1084 case Q81_RX_OCTETS_PRIORITY4_LO : 1085 case Q81_RX_OCTETS_PRIORITY5 : 1086 case Q81_RX_OCTETS_PRIORITY5_LO : 1087 case Q81_RX_OCTETS_PRIORITY6 : 1088 case Q81_RX_OCTETS_PRIORITY6_LO : 1089 case Q81_RX_OCTETS_PRIORITY7 : 1090 case Q81_RX_OCTETS_PRIORITY7_LO : 1091 case Q81_TX_PKTS_PRIORITY0 : 1092 case Q81_TX_PKTS_PRIORITY0_LO : 1093 case Q81_TX_PKTS_PRIORITY1 : 1094 case Q81_TX_PKTS_PRIORITY1_LO : 1095 case Q81_TX_PKTS_PRIORITY2 : 1096 case Q81_TX_PKTS_PRIORITY2_LO : 1097 case Q81_TX_PKTS_PRIORITY3 : 1098 case Q81_TX_PKTS_PRIORITY3_LO : 1099 case Q81_TX_PKTS_PRIORITY4 : 1100 case Q81_TX_PKTS_PRIORITY4_LO : 1101 case Q81_TX_PKTS_PRIORITY5 : 1102 case Q81_TX_PKTS_PRIORITY5_LO : 1103 case Q81_TX_PKTS_PRIORITY6 : 1104 case Q81_TX_PKTS_PRIORITY6_LO : 1105 case Q81_TX_PKTS_PRIORITY7 : 1106 case Q81_TX_PKTS_PRIORITY7_LO : 1107 case Q81_TX_OCTETS_PRIORITY0 : 1108 case Q81_TX_OCTETS_PRIORITY0_LO : 1109 case Q81_TX_OCTETS_PRIORITY1 : 1110 case Q81_TX_OCTETS_PRIORITY1_LO : 1111 case Q81_TX_OCTETS_PRIORITY2 : 1112 case Q81_TX_OCTETS_PRIORITY2_LO : 1113 case Q81_TX_OCTETS_PRIORITY3 : 1114 case Q81_TX_OCTETS_PRIORITY3_LO : 1115 case Q81_TX_OCTETS_PRIORITY4 : 1116 case Q81_TX_OCTETS_PRIORITY4_LO : 1117 case Q81_TX_OCTETS_PRIORITY5 : 1118 case Q81_TX_OCTETS_PRIORITY5_LO : 1119 case Q81_TX_OCTETS_PRIORITY6 : 1120 case Q81_TX_OCTETS_PRIORITY6_LO : 1121 case Q81_TX_OCTETS_PRIORITY7 : 1122 case Q81_TX_OCTETS_PRIORITY7_LO : 1123 case Q81_RX_DISCARD_PRIORITY0 : 1124 case Q81_RX_DISCARD_PRIORITY0_LO : 1125 case Q81_RX_DISCARD_PRIORITY1 : 1126 case Q81_RX_DISCARD_PRIORITY1_LO : 1127 case Q81_RX_DISCARD_PRIORITY2 : 1128 case Q81_RX_DISCARD_PRIORITY2_LO : 1129 case Q81_RX_DISCARD_PRIORITY3 : 1130 case Q81_RX_DISCARD_PRIORITY3_LO : 1131 case Q81_RX_DISCARD_PRIORITY4 : 1132 case Q81_RX_DISCARD_PRIORITY4_LO : 1133 case Q81_RX_DISCARD_PRIORITY5 : 1134 case Q81_RX_DISCARD_PRIORITY5_LO : 1135 case Q81_RX_DISCARD_PRIORITY6 : 1136 case Q81_RX_DISCARD_PRIORITY6_LO : 1137 case Q81_RX_DISCARD_PRIORITY7 : 1138 case Q81_RX_DISCARD_PRIORITY7_LO : 1139 1140 if (o_func) 1141 ret = qls_rd_ofunc_xgmac_reg(ha, 1142 i, buf); 1143 else 1144 ret = qls_rd_xgmac_reg(ha, i, buf); 1145 1146 if (ret) 1147 *buf = Q81_BAD_DATA; 1148 1149 break; 1150 1151 default: 1152 break; 1153 } 1154 } 1155 return 0; 1156 } 1157 1158 static int 1159 qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count) 1160 { 1161 int i, ret = 0; 1162 1163 for (i = 0; i < count; i++, buf++) { 1164 ret = qls_rd_mpi_reg(ha, (offset + i), buf); 1165 1166 if (ret) 1167 return ret; 1168 } 1169 1170 return (ret); 1171 } 1172 1173 static int 1174 qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf) 1175 { 1176 uint32_t i; 1177 int ret; 1178 1179 #define Q81_RISC_124 0x0000007c 1180 #define Q81_RISC_127 0x0000007f 1181 #define Q81_SHADOW_OFFSET 0xb0000000 1182 1183 for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { 1184 ret = qls_wr_mpi_reg(ha, 1185 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124), 1186 (Q81_SHADOW_OFFSET | i << 20)); 1187 if (ret) 1188 goto exit_qls_get_mpi_shadow_regs; 1189 1190 ret = qls_mpi_risc_rd_reg(ha, 1191 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127), 1192 buf); 1193 if (ret) 1194 goto exit_qls_get_mpi_shadow_regs; 1195 } 1196 1197 exit_qls_get_mpi_shadow_regs: 1198 return ret; 1199 } 1200 1201 #define SYS_CLOCK (0x00) 1202 #define PCI_CLOCK (0x80) 1203 #define FC_CLOCK (0x140) 1204 #define XGM_CLOCK (0x180) 1205 1206 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000 1207 #define Q81_UP 0x00008000 1208 #define Q81_MAX_MUX 0x40 1209 #define Q81_MAX_MODULES 0x1F 1210 1211 static uint32_t * 1212 qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf) 1213 { 1214 uint32_t module, mux_sel, probe, lo_val, hi_val; 1215 1216 for (module = 0; module < Q81_MAX_MODULES; module ++) { 1217 if (valid[module]) { 1218 for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { 1219 probe = clock | Q81_ADDRESS_REGISTER_ENABLE | 1220 mux_sel | (module << 9); 1221 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1222 probe); 1223 1224 lo_val = READ_REG32(ha,\ 1225 Q81_CTL_XG_PROBE_MUX_DATA); 1226 1227 if (mux_sel == 0) { 1228 *buf = probe; 1229 buf ++; 1230 } 1231 1232 probe |= Q81_UP; 1233 1234 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1235 probe); 1236 hi_val = READ_REG32(ha,\ 1237 Q81_CTL_XG_PROBE_MUX_DATA); 1238 1239 *buf = lo_val; 1240 buf++; 1241 *buf = hi_val; 1242 buf++; 1243 } 1244 } 1245 } 1246 1247 return(buf); 1248 } 1249 1250 static int 1251 qls_get_probe_dump(qla_host_t *ha, uint32_t *buf) 1252 { 1253 1254 uint8_t sys_clock_valid_modules[0x20] = { 1255 1, // 0x00 1256 1, // 0x01 1257 1, // 0x02 1258 0, // 0x03 1259 1, // 0x04 1260 1, // 0x05 1261 1, // 0x06 1262 1, // 0x07 1263 1, // 0x08 1264 1, // 0x09 1265 1, // 0x0A 1266 1, // 0x0B 1267 1, // 0x0C 1268 1, // 0x0D 1269 1, // 0x0E 1270 0, // 0x0F 1271 1, // 0x10 1272 1, // 0x11 1273 1, // 0x12 1274 1, // 0x13 1275 0, // 0x14 1276 0, // 0x15 1277 0, // 0x16 1278 0, // 0x17 1279 0, // 0x18 1280 0, // 0x19 1281 0, // 0x1A 1282 0, // 0x1B 1283 0, // 0x1C 1284 0, // 0x1D 1285 0, // 0x1E 1286 0 // 0x1F 1287 }; 1288 1289 uint8_t pci_clock_valid_modules[0x20] = { 1290 1, // 0x00 1291 0, // 0x01 1292 0, // 0x02 1293 0, // 0x03 1294 0, // 0x04 1295 0, // 0x05 1296 1, // 0x06 1297 1, // 0x07 1298 0, // 0x08 1299 0, // 0x09 1300 0, // 0x0A 1301 0, // 0x0B 1302 0, // 0x0C 1303 0, // 0x0D 1304 1, // 0x0E 1305 0, // 0x0F 1306 0, // 0x10 1307 0, // 0x11 1308 0, // 0x12 1309 0, // 0x13 1310 0, // 0x14 1311 0, // 0x15 1312 0, // 0x16 1313 0, // 0x17 1314 0, // 0x18 1315 0, // 0x19 1316 0, // 0x1A 1317 0, // 0x1B 1318 0, // 0x1C 1319 0, // 0x1D 1320 0, // 0x1E 1321 0 // 0x1F 1322 }; 1323 1324 uint8_t xgm_clock_valid_modules[0x20] = { 1325 1, // 0x00 1326 0, // 0x01 1327 0, // 0x02 1328 1, // 0x03 1329 0, // 0x04 1330 0, // 0x05 1331 0, // 0x06 1332 0, // 0x07 1333 1, // 0x08 1334 1, // 0x09 1335 0, // 0x0A 1336 0, // 0x0B 1337 1, // 0x0C 1338 1, // 0x0D 1339 1, // 0x0E 1340 0, // 0x0F 1341 1, // 0x10 1342 1, // 0x11 1343 0, // 0x12 1344 0, // 0x13 1345 0, // 0x14 1346 0, // 0x15 1347 0, // 0x16 1348 0, // 0x17 1349 0, // 0x18 1350 0, // 0x19 1351 0, // 0x1A 1352 0, // 0x1B 1353 0, // 0x1C 1354 0, // 0x1D 1355 0, // 0x1E 1356 0 // 0x1F 1357 }; 1358 1359 uint8_t fc_clock_valid_modules[0x20] = { 1360 1, // 0x00 1361 0, // 0x01 1362 0, // 0x02 1363 0, // 0x03 1364 0, // 0x04 1365 0, // 0x05 1366 0, // 0x06 1367 0, // 0x07 1368 0, // 0x08 1369 0, // 0x09 1370 0, // 0x0A 1371 0, // 0x0B 1372 1, // 0x0C 1373 1, // 0x0D 1374 0, // 0x0E 1375 0, // 0x0F 1376 0, // 0x10 1377 0, // 0x11 1378 0, // 0x12 1379 0, // 0x13 1380 0, // 0x14 1381 0, // 0x15 1382 0, // 0x16 1383 0, // 0x17 1384 0, // 0x18 1385 0, // 0x19 1386 0, // 0x1A 1387 0, // 0x1B 1388 0, // 0x1C 1389 0, // 0x1D 1390 0, // 0x1E 1391 0 // 0x1F 1392 }; 1393 1394 qls_wr_mpi_reg(ha, 0x100e, 0x18a20000); 1395 1396 buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf); 1397 1398 buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf); 1399 1400 buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf); 1401 1402 buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf); 1403 1404 return(0); 1405 } 1406 1407 static void 1408 qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf) 1409 { 1410 uint32_t type, idx, idx_max; 1411 uint32_t r_idx; 1412 uint32_t r_data; 1413 uint32_t val; 1414 1415 for (type = 0; type < 4; type ++) { 1416 if (type < 2) 1417 idx_max = 8; 1418 else 1419 idx_max = 16; 1420 1421 for (idx = 0; idx < idx_max; idx ++) { 1422 val = 0x04000000 | (type << 16) | (idx << 8); 1423 WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val); 1424 1425 r_idx = 0; 1426 while ((r_idx & 0x40000000) == 0) 1427 r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX); 1428 1429 r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA); 1430 1431 *buf = type; 1432 buf ++; 1433 *buf = idx; 1434 buf ++; 1435 *buf = r_idx; 1436 buf ++; 1437 *buf = r_data; 1438 buf ++; 1439 } 1440 } 1441 } 1442 1443 static void 1444 qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf) 1445 { 1446 1447 #define Q81_RS_AND_ADR 0x06000000 1448 #define Q81_RS_ONLY 0x04000000 1449 #define Q81_NUM_TYPES 10 1450 1451 uint32_t result_index, result_data; 1452 uint32_t type; 1453 uint32_t index; 1454 uint32_t offset; 1455 uint32_t val; 1456 uint32_t initial_val; 1457 uint32_t max_index; 1458 uint32_t max_offset; 1459 1460 for (type = 0; type < Q81_NUM_TYPES; type ++) { 1461 switch (type) { 1462 case 0: // CAM 1463 initial_val = Q81_RS_AND_ADR; 1464 max_index = 512; 1465 max_offset = 3; 1466 break; 1467 1468 case 1: // Multicast MAC Address 1469 initial_val = Q81_RS_ONLY; 1470 max_index = 32; 1471 max_offset = 2; 1472 break; 1473 1474 case 2: // VLAN filter mask 1475 case 3: // MC filter mask 1476 initial_val = Q81_RS_ONLY; 1477 max_index = 4096; 1478 max_offset = 1; 1479 break; 1480 1481 case 4: // FC MAC addresses 1482 initial_val = Q81_RS_ONLY; 1483 max_index = 4; 1484 max_offset = 2; 1485 break; 1486 1487 case 5: // Mgmt MAC addresses 1488 initial_val = Q81_RS_ONLY; 1489 max_index = 8; 1490 max_offset = 2; 1491 break; 1492 1493 case 6: // Mgmt VLAN addresses 1494 initial_val = Q81_RS_ONLY; 1495 max_index = 16; 1496 max_offset = 1; 1497 break; 1498 1499 case 7: // Mgmt IPv4 address 1500 initial_val = Q81_RS_ONLY; 1501 max_index = 4; 1502 max_offset = 1; 1503 break; 1504 1505 case 8: // Mgmt IPv6 address 1506 initial_val = Q81_RS_ONLY; 1507 max_index = 4; 1508 max_offset = 4; 1509 break; 1510 1511 case 9: // Mgmt TCP/UDP Dest port 1512 initial_val = Q81_RS_ONLY; 1513 max_index = 4; 1514 max_offset = 1; 1515 break; 1516 1517 default: 1518 printf("Bad type!!! 0x%08x\n", type); 1519 max_index = 0; 1520 max_offset = 0; 1521 break; 1522 } 1523 1524 for (index = 0; index < max_index; index ++) { 1525 for (offset = 0; offset < max_offset; offset ++) { 1526 val = initial_val | (type << 16) | 1527 (index << 4) | (offset); 1528 1529 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\ 1530 val); 1531 1532 result_index = 0; 1533 1534 while ((result_index & 0x40000000) == 0) 1535 result_index = 1536 READ_REG32(ha, \ 1537 Q81_CTL_MAC_PROTO_ADDR_INDEX); 1538 1539 result_data = READ_REG32(ha,\ 1540 Q81_CTL_MAC_PROTO_ADDR_DATA); 1541 1542 *buf = result_index; 1543 buf ++; 1544 1545 *buf = result_data; 1546 buf ++; 1547 } 1548 } 1549 } 1550 } 1551 1552 static int 1553 qls_get_ets_regs(qla_host_t *ha, uint32_t *buf) 1554 { 1555 int ret = 0; 1556 int i; 1557 1558 for(i = 0; i < 8; i ++, buf ++) { 1559 WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \ 1560 ((i << 29) | 0x08000000)); 1561 *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD); 1562 } 1563 1564 for(i = 0; i < 2; i ++, buf ++) { 1565 WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \ 1566 ((i << 29) | 0x08000000)); 1567 *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD); 1568 } 1569 1570 return ret; 1571 } 1572 1573 int 1574 qls_mpi_core_dump(qla_host_t *ha) 1575 { 1576 int ret; 1577 int i; 1578 uint32_t reg, reg_val; 1579 1580 qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump; 1581 1582 ret = qls_pause_mpi_risc(ha); 1583 if (ret) { 1584 printf("Failed RISC pause. Status = 0x%.08x\n",ret); 1585 return(-1); 1586 } 1587 1588 memset(&(mpi_dump->mpi_global_header), 0, 1589 sizeof(qls_mpid_glbl_hdr_t)); 1590 1591 mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE; 1592 mpi_dump->mpi_global_header.hdr_size = 1593 sizeof(qls_mpid_glbl_hdr_t); 1594 mpi_dump->mpi_global_header.img_size = 1595 sizeof(qls_mpi_coredump_t); 1596 1597 memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump", 1598 sizeof(mpi_dump->mpi_global_header.id)); 1599 1600 qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr, 1601 Q81_NIC1_CONTROL_SEG_NUM, 1602 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)), 1603 "NIC1 Registers"); 1604 1605 qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr, 1606 Q81_NIC2_CONTROL_SEG_NUM, 1607 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)), 1608 "NIC2 Registers"); 1609 1610 qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr, 1611 Q81_NIC1_XGMAC_SEG_NUM, 1612 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)), 1613 "NIC1 XGMac Registers"); 1614 1615 qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr, 1616 Q81_NIC2_XGMAC_SEG_NUM, 1617 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)), 1618 "NIC2 XGMac Registers"); 1619 1620 if (ha->pci_func & 1) { 1621 for (i = 0; i < 64; i++) 1622 mpi_dump->nic2_regs[i] = 1623 READ_REG32(ha, i * sizeof(uint32_t)); 1624 1625 for (i = 0; i < 64; i++) 1626 mpi_dump->nic1_regs[i] = 1627 qls_rd_ofunc_reg(ha, 1628 (i * sizeof(uint32_t)) / 4); 1629 1630 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0); 1631 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1); 1632 } else { 1633 for (i = 0; i < 64; i++) 1634 mpi_dump->nic1_regs[i] = 1635 READ_REG32(ha, i * sizeof(uint32_t)); 1636 1637 for (i = 0; i < 64; i++) 1638 mpi_dump->nic2_regs[i] = 1639 qls_rd_ofunc_reg(ha, 1640 (i * sizeof(uint32_t)) / 4); 1641 1642 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0); 1643 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); 1644 } 1645 1646 qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr, 1647 Q81_XAUI1_AN_SEG_NUM, 1648 (sizeof(qls_mpid_seg_hdr_t) + 1649 sizeof(mpi_dump->serdes1_xaui_an)), 1650 "XAUI1 AN Registers"); 1651 1652 qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr, 1653 Q81_XAUI1_HSS_PCS_SEG_NUM, 1654 (sizeof(qls_mpid_seg_hdr_t) + 1655 sizeof(mpi_dump->serdes1_xaui_hss_pcs)), 1656 "XAUI1 HSS PCS Registers"); 1657 1658 qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr, 1659 Q81_XFI1_AN_SEG_NUM, 1660 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)), 1661 "XFI1 AN Registers"); 1662 1663 qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr, 1664 Q81_XFI1_TRAIN_SEG_NUM, 1665 (sizeof(qls_mpid_seg_hdr_t) + 1666 sizeof(mpi_dump->serdes1_xfi_train)), 1667 "XFI1 TRAIN Registers"); 1668 1669 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr, 1670 Q81_XFI1_HSS_PCS_SEG_NUM, 1671 (sizeof(qls_mpid_seg_hdr_t) + 1672 sizeof(mpi_dump->serdes1_xfi_hss_pcs)), 1673 "XFI1 HSS PCS Registers"); 1674 1675 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr, 1676 Q81_XFI1_HSS_TX_SEG_NUM, 1677 (sizeof(qls_mpid_seg_hdr_t) + 1678 sizeof(mpi_dump->serdes1_xfi_hss_tx)), 1679 "XFI1 HSS TX Registers"); 1680 1681 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr, 1682 Q81_XFI1_HSS_RX_SEG_NUM, 1683 (sizeof(qls_mpid_seg_hdr_t) + 1684 sizeof(mpi_dump->serdes1_xfi_hss_rx)), 1685 "XFI1 HSS RX Registers"); 1686 1687 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr, 1688 Q81_XFI1_HSS_PLL_SEG_NUM, 1689 (sizeof(qls_mpid_seg_hdr_t) + 1690 sizeof(mpi_dump->serdes1_xfi_hss_pll)), 1691 "XFI1 HSS PLL Registers"); 1692 1693 qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr, 1694 Q81_XAUI2_AN_SEG_NUM, 1695 (sizeof(qls_mpid_seg_hdr_t) + 1696 sizeof(mpi_dump->serdes2_xaui_an)), 1697 "XAUI2 AN Registers"); 1698 1699 qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr, 1700 Q81_XAUI2_HSS_PCS_SEG_NUM, 1701 (sizeof(qls_mpid_seg_hdr_t) + 1702 sizeof(mpi_dump->serdes2_xaui_hss_pcs)), 1703 "XAUI2 HSS PCS Registers"); 1704 1705 qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr, 1706 Q81_XFI2_AN_SEG_NUM, 1707 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)), 1708 "XFI2 AN Registers"); 1709 1710 qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr, 1711 Q81_XFI2_TRAIN_SEG_NUM, 1712 (sizeof(qls_mpid_seg_hdr_t) + 1713 sizeof(mpi_dump->serdes2_xfi_train)), 1714 "XFI2 TRAIN Registers"); 1715 1716 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr, 1717 Q81_XFI2_HSS_PCS_SEG_NUM, 1718 (sizeof(qls_mpid_seg_hdr_t) + 1719 sizeof(mpi_dump->serdes2_xfi_hss_pcs)), 1720 "XFI2 HSS PCS Registers"); 1721 1722 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr, 1723 Q81_XFI2_HSS_TX_SEG_NUM, 1724 (sizeof(qls_mpid_seg_hdr_t) + 1725 sizeof(mpi_dump->serdes2_xfi_hss_tx)), 1726 "XFI2 HSS TX Registers"); 1727 1728 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr, 1729 Q81_XFI2_HSS_RX_SEG_NUM, 1730 (sizeof(qls_mpid_seg_hdr_t) + 1731 sizeof(mpi_dump->serdes2_xfi_hss_rx)), 1732 "XFI2 HSS RX Registers"); 1733 1734 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr, 1735 Q81_XFI2_HSS_PLL_SEG_NUM, 1736 (sizeof(qls_mpid_seg_hdr_t) + 1737 sizeof(mpi_dump->serdes2_xfi_hss_pll)), 1738 "XFI2 HSS PLL Registers"); 1739 1740 qls_rd_serdes_regs(ha, mpi_dump); 1741 1742 qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr, 1743 Q81_CORE_SEG_NUM, 1744 (sizeof(mpi_dump->core_regs_seg_hdr) + 1745 sizeof(mpi_dump->mpi_core_regs) + 1746 sizeof(mpi_dump->mpi_core_sh_regs)), 1747 "Core Registers"); 1748 1749 ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0], 1750 Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT); 1751 1752 ret = qls_get_mpi_shadow_regs(ha, 1753 &mpi_dump->mpi_core_sh_regs[0]); 1754 1755 qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr, 1756 Q81_TEST_LOGIC_SEG_NUM, 1757 (sizeof(qls_mpid_seg_hdr_t) + 1758 sizeof(mpi_dump->test_logic_regs)), 1759 "Test Logic Regs"); 1760 1761 ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0], 1762 Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT); 1763 1764 qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr, 1765 Q81_RMII_SEG_NUM, 1766 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)), 1767 "RMII Registers"); 1768 1769 ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0], 1770 Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT); 1771 1772 qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr, 1773 Q81_FCMAC1_SEG_NUM, 1774 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)), 1775 "FCMAC1 Registers"); 1776 1777 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0], 1778 Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1779 1780 qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr, 1781 Q81_FCMAC2_SEG_NUM, 1782 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)), 1783 "FCMAC2 Registers"); 1784 1785 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0], 1786 Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1787 1788 qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr, 1789 Q81_FC1_MBOX_SEG_NUM, 1790 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)), 1791 "FC1 MBox Regs"); 1792 1793 ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0], 1794 Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1795 1796 qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr, 1797 Q81_IDE_SEG_NUM, 1798 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)), 1799 "IDE Registers"); 1800 1801 ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0], 1802 Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT); 1803 1804 qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr, 1805 Q81_NIC1_MBOX_SEG_NUM, 1806 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)), 1807 "NIC1 MBox Regs"); 1808 1809 ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0], 1810 Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1811 1812 qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr, 1813 Q81_SMBUS_SEG_NUM, 1814 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)), 1815 "SMBus Registers"); 1816 1817 ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0], 1818 Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT); 1819 1820 qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr, 1821 Q81_FC2_MBOX_SEG_NUM, 1822 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)), 1823 "FC2 MBox Regs"); 1824 1825 ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0], 1826 Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1827 1828 qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr, 1829 Q81_NIC2_MBOX_SEG_NUM, 1830 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)), 1831 "NIC2 MBox Regs"); 1832 1833 ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0], 1834 Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1835 1836 qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr, 1837 Q81_I2C_SEG_NUM, 1838 (sizeof(qls_mpid_seg_hdr_t) + 1839 sizeof(mpi_dump->i2c_regs)), 1840 "I2C Registers"); 1841 1842 ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0], 1843 Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT); 1844 1845 qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr, 1846 Q81_MEMC_SEG_NUM, 1847 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)), 1848 "MEMC Registers"); 1849 1850 ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0], 1851 Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT); 1852 1853 qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr, 1854 Q81_PBUS_SEG_NUM, 1855 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)), 1856 "PBUS Registers"); 1857 1858 ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0], 1859 Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT); 1860 1861 qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr, 1862 Q81_MDE_SEG_NUM, 1863 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)), 1864 "MDE Registers"); 1865 1866 ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0], 1867 Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT); 1868 1869 qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr, 1870 Q81_INTR_STATES_SEG_NUM, 1871 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)), 1872 "INTR States"); 1873 1874 qls_get_intr_states(ha, &mpi_dump->intr_states[0]); 1875 1876 qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr, 1877 Q81_PROBE_DUMP_SEG_NUM, 1878 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)), 1879 "Probe Dump"); 1880 1881 qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]); 1882 1883 qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr, 1884 Q81_ROUTING_INDEX_SEG_NUM, 1885 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)), 1886 "Routing Regs"); 1887 1888 qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]); 1889 1890 qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr, 1891 Q81_MAC_PROTOCOL_SEG_NUM, 1892 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)), 1893 "MAC Prot Regs"); 1894 1895 qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]); 1896 1897 qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr, 1898 Q81_ETS_SEG_NUM, 1899 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)), 1900 "ETS Registers"); 1901 1902 ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]); 1903 1904 qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr, 1905 Q81_SEM_REGS_SEG_NUM, 1906 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)), 1907 "Sem Registers"); 1908 1909 for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { 1910 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) | 1911 (Q81_CTL_SEMAPHORE >> 2); 1912 1913 ret = qls_mpi_risc_rd_reg(ha, reg, ®_val); 1914 mpi_dump->sem_regs[i] = reg_val; 1915 1916 if (ret != 0) 1917 mpi_dump->sem_regs[i] = Q81_BAD_DATA; 1918 } 1919 1920 ret = qls_unpause_mpi_risc(ha); 1921 if (ret) 1922 printf("Failed RISC unpause. Status = 0x%.08x\n",ret); 1923 1924 ret = qls_mpi_reset(ha); 1925 if (ret) 1926 printf("Failed RISC reset. Status = 0x%.08x\n",ret); 1927 1928 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000); 1929 1930 qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr, 1931 Q81_MEMC_RAM_SEG_NUM, 1932 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)), 1933 "MEMC RAM"); 1934 1935 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1936 Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT); 1937 if (ret) 1938 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret); 1939 1940 qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr, 1941 Q81_WCS_RAM_SEG_NUM, 1942 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)), 1943 "WCS RAM"); 1944 1945 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1946 Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT); 1947 if (ret) 1948 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret); 1949 1950 qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr, 1951 Q81_WQC1_SEG_NUM, 1952 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)), 1953 "WQC 1"); 1954 1955 qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr, 1956 Q81_WQC2_SEG_NUM, 1957 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)), 1958 "WQC 2"); 1959 1960 qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr, 1961 Q81_CQC1_SEG_NUM, 1962 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)), 1963 "CQC 1"); 1964 1965 qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr, 1966 Q81_CQC2_SEG_NUM, 1967 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)), 1968 "CQC 2"); 1969 1970 return 0; 1971 }
Cache object: 452f4c60b34c61c181f4120c23103dfb
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]