qls_dump.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2014 Qlogic Corporation
    5  * All rights reserved.
    6  *
    7  *  Redistribution and use in source and binary forms, with or without
    8  *  modification, are permitted provided that the following conditions
    9  *  are met:
   10  *
   11  *  1. Redistributions of source code must retain the above copyright
   12  *     notice, this list of conditions and the following disclaimer.
   13  *  2. Redistributions in binary form must reproduce the above copyright
   14  *     notice, this list of conditions and the following disclaimer in the
   15  *     documentation and/or other materials provided with the distribution.
   16  *
   17  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   18  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   21  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   22  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   23  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   24  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   25  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   26  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   27  *  POSSIBILITY OF SUCH DAMAGE.
   28  *
   29  * $FreeBSD$
   30  */
   31 
   32 /*
   33  * File: qls_dump.h
   34  */
   35 
   36 #ifndef _QLS_DUMP_H_
   37 #define _QLS_DUMP_H_
   38 
   39 #define Q81_MPID_COOKIE 0x5555aaaa
   40 
   41 typedef struct qls_mpid_glbl_hdr
   42 {
   43         uint32_t        cookie;
   44         uint8_t         id[16];
   45         uint32_t        time_lo;
   46         uint32_t        time_hi;
   47         uint32_t        img_size;
   48         uint32_t        hdr_size;
   49         uint8_t         info[220];
   50 } qls_mpid_glbl_hdr_t;
   51 
   52 typedef struct qls_mpid_seg_hdr
   53 {
   54         uint32_t        cookie;
   55         uint32_t        seg_num;
   56         uint32_t        seg_size;
   57         uint32_t        extra;
   58         uint8_t         desc[16];
   59 } qls_mpid_seg_hdr_t;
   60 
   61 enum
   62 {
   63         Q81_MPI_CORE_REGS_ADDR          = 0x00030000,
   64         Q81_MPI_CORE_REGS_CNT           = 127,
   65         Q81_MPI_CORE_SH_REGS_CNT        = 16,
   66         Q81_TEST_REGS_ADDR              = 0x00001000,
   67         Q81_TEST_REGS_CNT               = 23,
   68         Q81_RMII_REGS_ADDR              = 0x00001040,
   69         Q81_RMII_REGS_CNT               = 64,
   70         Q81_FCMAC1_REGS_ADDR            = 0x00001080,
   71         Q81_FCMAC2_REGS_ADDR            = 0x000010c0,
   72         Q81_FCMAC_REGS_CNT              = 64,
   73         Q81_FC1_MBX_REGS_ADDR           = 0x00001100,
   74         Q81_FC2_MBX_REGS_ADDR           = 0x00001240,
   75         Q81_FC_MBX_REGS_CNT             = 64,
   76         Q81_IDE_REGS_ADDR               = 0x00001140,
   77         Q81_IDE_REGS_CNT                = 64,
   78         Q81_NIC1_MBX_REGS_ADDR          = 0x00001180,
   79         Q81_NIC2_MBX_REGS_ADDR          = 0x00001280,
   80         Q81_NIC_MBX_REGS_CNT            = 64,
   81         Q81_SMBUS_REGS_ADDR             = 0x00001200,
   82         Q81_SMBUS_REGS_CNT              = 64,
   83         Q81_I2C_REGS_ADDR               = 0x00001fc0,
   84         Q81_I2C_REGS_CNT                = 64,
   85         Q81_MEMC_REGS_ADDR              = 0x00003000,
   86         Q81_MEMC_REGS_CNT               = 256,
   87         Q81_PBUS_REGS_ADDR              = 0x00007c00,
   88         Q81_PBUS_REGS_CNT               = 256,
   89         Q81_MDE_REGS_ADDR               = 0x00010000,
   90         Q81_MDE_REGS_CNT                = 6,
   91         Q81_CODE_RAM_ADDR               = 0x00020000,
   92         Q81_CODE_RAM_CNT                = 0x2000,
   93         Q81_MEMC_RAM_ADDR               = 0x00100000,
   94         Q81_MEMC_RAM_CNT                = 0x2000,
   95         Q81_XGMAC_REGISTER_END          = 0x740,
   96 };
   97 
   98 #define Q81_PROBE_DATA_LENGTH_WORDS     ((64*2) + 1)
   99 #define Q81_NUMBER_OF_PROBES            34
  100 
  101 #define Q81_PROBE_SIZE          \
  102                 (Q81_PROBE_DATA_LENGTH_WORDS * Q81_NUMBER_OF_PROBES)
  103 
  104 #define Q81_NUMBER_ROUTING_REG_ENTRIES  48
  105 #define Q81_WORDS_PER_ROUTING_REG_ENTRY 4
  106 
  107 #define Q81_ROUT_REG_SIZE               \
  108         (Q81_NUMBER_ROUTING_REG_ENTRIES * Q81_WORDS_PER_ROUTING_REG_ENTRY)
  109 
  110 #define Q81_MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) +\
  111                                          (4096 * 1) + (4 * 2) +\
  112                                          (8 * 2) + (16 * 1) +\
  113                                          (4 * 1) + (4 * 4) + (4 * 1))
  114 
  115 #define Q81_WORDS_PER_MAC_PROT_ENTRY    2
  116 #define Q81_MAC_REG_SIZE                \
  117                 (Q81_MAC_PROTOCOL_REGISTER_WORDS * Q81_WORDS_PER_MAC_PROT_ENTRY)
  118 
  119 #define Q81_MAX_SEMAPHORE_FUNCTIONS 5
  120 
  121 #define Q81_WQC_WORD_SIZE       6
  122 #define Q81_NUMBER_OF_WQCS      128
  123 #define Q81_WQ_SIZE             (Q81_WQC_WORD_SIZE * Q81_NUMBER_OF_WQCS)
  124 
  125 #define Q81_CQC_WORD_SIZE       13
  126 #define Q81_NUMBER_OF_CQCS      128
  127 #define Q81_CQ_SIZE             (Q81_CQC_WORD_SIZE * Q81_NUMBER_OF_CQCS)
  128 
  129 struct qls_mpi_coredump {
  130         qls_mpid_glbl_hdr_t     mpi_global_header;
  131 
  132         qls_mpid_seg_hdr_t      core_regs_seg_hdr;
  133         uint32_t                mpi_core_regs[Q81_MPI_CORE_REGS_CNT];
  134         uint32_t                mpi_core_sh_regs[Q81_MPI_CORE_SH_REGS_CNT];
  135 
  136         qls_mpid_seg_hdr_t      test_logic_regs_seg_hdr;
  137         uint32_t                test_logic_regs[Q81_TEST_REGS_CNT];
  138 
  139         qls_mpid_seg_hdr_t      rmii_regs_seg_hdr;
  140         uint32_t                rmii_regs[Q81_RMII_REGS_CNT];
  141 
  142         qls_mpid_seg_hdr_t      fcmac1_regs_seg_hdr;
  143         uint32_t                fcmac1_regs[Q81_FCMAC_REGS_CNT];
  144 
  145         qls_mpid_seg_hdr_t      fcmac2_regs_seg_hdr;
  146         uint32_t                fcmac2_regs[Q81_FCMAC_REGS_CNT];
  147 
  148         qls_mpid_seg_hdr_t      fc1_mbx_regs_seg_hdr;
  149         uint32_t                fc1_mbx_regs[Q81_FC_MBX_REGS_CNT];
  150 
  151         qls_mpid_seg_hdr_t      ide_regs_seg_hdr;
  152         uint32_t                ide_regs[Q81_IDE_REGS_CNT];
  153 
  154         qls_mpid_seg_hdr_t      nic1_mbx_regs_seg_hdr;
  155         uint32_t                nic1_mbx_regs[Q81_NIC_MBX_REGS_CNT];
  156 
  157         qls_mpid_seg_hdr_t      smbus_regs_seg_hdr;
  158         uint32_t                smbus_regs[Q81_SMBUS_REGS_CNT];
  159 
  160         qls_mpid_seg_hdr_t      fc2_mbx_regs_seg_hdr;
  161         uint32_t                fc2_mbx_regs[Q81_FC_MBX_REGS_CNT];
  162 
  163         qls_mpid_seg_hdr_t      nic2_mbx_regs_seg_hdr;
  164         uint32_t                nic2_mbx_regs[Q81_NIC_MBX_REGS_CNT];
  165 
  166         qls_mpid_seg_hdr_t      i2c_regs_seg_hdr;
  167         uint32_t                i2c_regs[Q81_I2C_REGS_CNT];
  168 
  169         qls_mpid_seg_hdr_t      memc_regs_seg_hdr;
  170         uint32_t                memc_regs[Q81_MEMC_REGS_CNT];
  171 
  172         qls_mpid_seg_hdr_t      pbus_regs_seg_hdr;
  173         uint32_t                pbus_regs[Q81_PBUS_REGS_CNT];
  174 
  175         qls_mpid_seg_hdr_t      mde_regs_seg_hdr;
  176         uint32_t                mde_regs[Q81_MDE_REGS_CNT];
  177 
  178         qls_mpid_seg_hdr_t      xaui1_an_hdr;
  179         uint32_t                serdes1_xaui_an[14];
  180 
  181         qls_mpid_seg_hdr_t      xaui1_hss_pcs_hdr;
  182         uint32_t                serdes1_xaui_hss_pcs[33];
  183 
  184         qls_mpid_seg_hdr_t      xfi1_an_hdr;
  185         uint32_t                serdes1_xfi_an[14];
  186 
  187         qls_mpid_seg_hdr_t      xfi1_train_hdr;
  188         uint32_t                serdes1_xfi_train[12];
  189 
  190         qls_mpid_seg_hdr_t      xfi1_hss_pcs_hdr;
  191         uint32_t                serdes1_xfi_hss_pcs[15];
  192 
  193         qls_mpid_seg_hdr_t      xfi1_hss_tx_hdr;
  194         uint32_t                serdes1_xfi_hss_tx[32];
  195 
  196         qls_mpid_seg_hdr_t      xfi1_hss_rx_hdr;
  197         uint32_t                serdes1_xfi_hss_rx[32];
  198 
  199         qls_mpid_seg_hdr_t      xfi1_hss_pll_hdr;
  200         uint32_t                serdes1_xfi_hss_pll[32];
  201 
  202         qls_mpid_seg_hdr_t      xaui2_an_hdr;
  203         uint32_t                serdes2_xaui_an[14];
  204 
  205         qls_mpid_seg_hdr_t      xaui2_hss_pcs_hdr;
  206         uint32_t                serdes2_xaui_hss_pcs[33];
  207 
  208         qls_mpid_seg_hdr_t      xfi2_an_hdr;
  209         uint32_t                serdes2_xfi_an[14];
  210 
  211         qls_mpid_seg_hdr_t      xfi2_train_hdr;
  212         uint32_t                serdes2_xfi_train[12];
  213 
  214         qls_mpid_seg_hdr_t      xfi2_hss_pcs_hdr;
  215         uint32_t                serdes2_xfi_hss_pcs[15];
  216 
  217         qls_mpid_seg_hdr_t      xfi2_hss_tx_hdr;
  218         uint32_t                serdes2_xfi_hss_tx[32];
  219 
  220         qls_mpid_seg_hdr_t      xfi2_hss_rx_hdr;
  221         uint32_t                serdes2_xfi_hss_rx[32];
  222 
  223         qls_mpid_seg_hdr_t      xfi2_hss_pll_hdr;
  224         uint32_t                serdes2_xfi_hss_pll[32];
  225 
  226         qls_mpid_seg_hdr_t      nic1_regs_seg_hdr;
  227         uint32_t                nic1_regs[64];
  228 
  229         qls_mpid_seg_hdr_t      nic2_regs_seg_hdr;
  230         uint32_t                nic2_regs[64];
  231 
  232         qls_mpid_seg_hdr_t      intr_states_seg_hdr;
  233         uint32_t                intr_states[MAX_RX_RINGS];
  234 
  235         qls_mpid_seg_hdr_t      xgmac1_seg_hdr;
  236         uint32_t                xgmac1[Q81_XGMAC_REGISTER_END];
  237 
  238         qls_mpid_seg_hdr_t      xgmac2_seg_hdr;
  239         uint32_t                xgmac2[Q81_XGMAC_REGISTER_END];
  240 
  241         qls_mpid_seg_hdr_t      probe_dump_seg_hdr;
  242         uint32_t                probe_dump[Q81_PROBE_SIZE];
  243 
  244         qls_mpid_seg_hdr_t      routing_reg_seg_hdr;
  245         uint32_t                routing_regs[Q81_ROUT_REG_SIZE];
  246 
  247         qls_mpid_seg_hdr_t      mac_prot_reg_seg_hdr;
  248         uint32_t                mac_prot_regs[Q81_MAC_REG_SIZE];
  249 
  250         qls_mpid_seg_hdr_t      sem_regs_seg_hdr;
  251         uint32_t                sem_regs[Q81_MAX_SEMAPHORE_FUNCTIONS];
  252 
  253         qls_mpid_seg_hdr_t      ets_seg_hdr;
  254         uint32_t                ets[8+2];
  255 
  256         qls_mpid_seg_hdr_t      wqc1_seg_hdr;
  257         uint32_t                wqc1[Q81_WQ_SIZE];
  258 
  259         qls_mpid_seg_hdr_t      cqc1_seg_hdr;
  260         uint32_t                cqc1[Q81_CQ_SIZE];
  261 
  262         qls_mpid_seg_hdr_t      wqc2_seg_hdr;
  263         uint32_t                wqc2[Q81_WQ_SIZE];
  264 
  265         qls_mpid_seg_hdr_t      cqc2_seg_hdr;
  266         uint32_t                cqc2[Q81_CQ_SIZE];
  267 
  268         qls_mpid_seg_hdr_t      code_ram_seg_hdr;
  269         uint32_t                code_ram[Q81_CODE_RAM_CNT];
  270 
  271         qls_mpid_seg_hdr_t      memc_ram_seg_hdr;
  272         uint32_t                memc_ram[Q81_MEMC_RAM_CNT];
  273 };
  274 typedef struct qls_mpi_coredump qls_mpi_coredump_t;
  275 
  276 #define Q81_BAD_DATA    0xDEADBEEF
  277 
  278 #endif /* #ifndef  _QLS_DUMP_H_ */
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FreeBSD/Linux Kernel Cross Reference sys/dev/qlxge/qls_dump.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/qlxge/qls_dump.h
